Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.

Abstract: A method and apparatus to deskew dead cycles is described using a block aligner. In one example a method includes receiving a sequence of bytes into a first buffer from each lane of a multiple lane peripheral device bus and receiving the sequence of bytes into a second buffer delayed one clock cycle from the first buffer. The method further includes providing the sequence of bytes from the first buffer to an output buffer, counting clock cycles of data as the data is received into the first and second buffers, upon reaching a predetermined count, inserting a dead cycle into the output buffer, and after inserting the dead cycle providing the sequence of bytes from the second buffer instead of the first buffer to the output buffer.

Abstract: A deskewing apparatus includes a power supply connector, a oscillator, a first switch unit, a second switch unit, a first logic member, a second logic member, a clock generator and a plurality of output channels. The oscillator generates an electrical signal with a predetermined frequency and sinusoidal waveform. The first switch unit and the second switch unit each generates on/off signals by controlling power on/off. The first logic member and the second logic member generate logic signals according to the corresponding on/off signals from the first switch unit and the second switch unit. The clock generator multiplies the frequency of the electrical signal based on the combination of the logic signals and converting the electrical signal from sinusoidal waveform into rectangular waveform. The output channels output the converted electrical signal.

Abstract: Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby shared servers provide resources, software, and data to computers and other devices on demand. In several embodiments, the object storage system includes a ring implementation used to associate object storage commands with particular physical servers such that certain guarantees of consistency, availability, and performance can be met. In other embodiments, the object storage system includes a synchronization protocol used to order operations across a distributed system. In a third set of embodiments, the object storage system includes a metadata management system. In a fourth set of embodiments, the object storage system uses a structured information synchronization system. Features from each set of embodiments can be used to improve the performance and scalability of a cloud computing object storage system.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: A method for compensating for sleep clock slew is disclosed. The method may conserve battery power. The method includes operating in a discontinuous receive mode. A measured sleep clock slew is determined. Discontinuous receive mode parameters are adjusted based on the measured sleep clock slew. Discontinuous receive mode wake-up procedures are performed. The discontinuous receive mode parameters may include a sleep time and a search time. Other aspects, embodiments, and features are also claimed and described.

Abstract: A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.

Abstract: A method and apparatus for performing real time clock (RTC) calibration through frame number calculation are provided, where the method is applied to an electronic device. The method includes the steps of: before power failure of the electronic device occurs, obtaining an original time value from an RTC of the electronic device and storing the original time value and a frame number of a first frame into a storage unit; and after the electronic device is powered on since elimination of the power failure, obtaining a frame number of a second frame and performing at least one calculation operation according to the frame number of the second frame, the frame number of the first frame, and the original time value to determine a calibrated time value of the RTC, and updating the RTC with at least one of the calibrated time value and a derivative of the calibrated time value.

Abstract: A system and method for synchronizing multiple backplanes within an information handling system are disclosed. An information handling system includes a first controller that may be operable to generate a time command at a predetermined time interval. A backplane including a second controller is communicatively coupled to the first controller. The second controller may be operable to receive the time command from the first controller and calculate a skew for the time command based at least on a location of the backplane. The second controller may further be operable to adjust a time domain of the backplane based on the calculated skew for the time command to synchronize the backplane.

Abstract: A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing analysis steps includes identifying cells on and in parallel with a signal path that are driven by a same signal and determining an output transition time and a delay using the characterisation data for the cell. The correcting steps includes providing further characterisation data for some of the cells; correcting the output transition time for some of the cells by increasing the output transition time by an amount dependent upon the Miller capacitance for the cell and using the correction to the output transition time to correct an input transition time for a next cell; and calculating a time taken for a data signal to travel along the signal path from the delay times.

Abstract: In one embodiment, a semiconductor integrated code (SIC) may be provided in a binary format by a processor manufacturer. This SIC may include platform independent code of the processor manufacturer. Such code may include embedded processor logic to initialize the processor and at least one link that couples the processor to a memory, and embedded memory logic to initialize the memory. Other embodiments are described and claimed.

Abstract: A method of correcting a duty ratio of a data strobe signal is provided. By the method, a duty ratio of a data strobe signal output from a semiconductor memory device is detected and a duty ratio of a clock signal input to the semiconductor memory device is adjusted based on the duty ratio of the data strobe signal.

Abstract: A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal, reception data is generated. A data adjustment circuit delays the transmission data on the basis of a TAP2 value. By synchronizing the delayed transmission data with the adjusted clock signal, adjusted reception data is generated. A data adjustment control circuit generates the TAP2 value on the basis of a result of a comparison between the reception data and the adjusted reception data, and outputs to a clock adjustment control circuit an instruction to update the TAP value.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: Clock pulses of a variable speed clock are adjusted relative to system utilization. A load monitor periodically collects sensor measurements of resources and based on the sensor measurements, the load monitor adjusts the clock speed up or down.

Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract: Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit.

Abstract: A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.

Abstract: A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a synchronization/desynchronization controller configured to synchronize or desynchronize the clock of the processor with respect to the clock of the submodule, depending on the result of the monitoring. Specifically, the processor clock is synchronized to the submodule clock when the frequency of access to the submodule by the processor is high, and the processor clock is desynchronized with respect to the submodule clock when the access frequency is low.

Abstract: A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

Abstract: One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or not it is necessary to shift a phase of the sampling clock, and up/down counts a counter in accordance with a shift direction when judging that it is necessary to shift the phase, a limit value storage section which stores a variance range limit value of the phase shift, and a shift limit judging section which judges whether or not a value of the counter exceeds the limit value of the phase shift, notifies a host device of an error when judging that the counter value exceeds the limit value, and shifts the phase of the sampling clock in accordance with the counter value of the counter when judging that the counter value does not exceed the limit value.

Abstract: According to one embodiment, there is provided a host controller, which samples reception data in a VDS mode and an FDS mode, includes a VDS phase register which holds a phase shift amount in the VDS mode, an FDS phase register which holds a phase shift amount in the FDS mode, a mode setting unit configured to indicate in which of the VDS mode and the FDS mode data is sampled, a sampling position setting unit which selects the phase shift amount set in one of the VDS and the FDS phase register in accordance with a setting value of the mode setting unit, and provides the selected phase shift amount as a sampling position, and a clock phase shift unit which shifts a phase of an input clock signal in accordance with the shift amount, and provides the shifted input clock signal as a sampling clock.

Abstract: A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.

Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

Abstract: One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.

Abstract: According to one embodiment, an apparatus includes a first processing unit operating according to a first clock, a second processing unit operating according to a second clock running separately from the first clock, and a synchronization controller coupled to the first communication unit and the second communication unit. The synchronization controller is configured to (i) cause the first communication unit to generate a first indication of time at which the first processing unit transmits a signal to the second processing unit, according to the first clock, (ii) cause the second processing unit to generate a second indication of time at which the second processing unit receives the signal, according to the second clock, and (iii) determine an offset between the first clock and the second clock based on the first indication of time and the second indication of time.

Abstract: A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus.

Abstract: A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and also used internally as feedback. Based on the clock output, the window comparator circuit collapses the thresholds while sampling input Bipolar return to zero data.

Abstract: A method and system for providing an improved compliance clock service are described. An example method comprises establishing a system compliance clock (SCC) for a storage system that provides a compliant storage service, and establishing, for a volume in the storage system, a volume compliance clock (VCC). A current value of the SCC may be periodically updated based on hardware ticks monitored at the associated storage node. The volume compliance clock is to update its value based on a current value of the SCC.

Abstract: A stackable form-factor Peripheral Component Interconnect (PCI) device can be configured as a host controller or a master/target for use on a PCI assembly. PCI device may comprise a multiple-input switch coupled to a PCI bus, a multiplexor coupled to the switch, and a reconfigurable device coupled to one of the switch and multiplexor. The PCI device is configured to support functionality from power-up, and either control function or add-in card function.

Abstract: There is provided a serial reception circuit that can suppress the occurrence of a bit error due to long-period jitter while suppressing the power consumption. A serial reception circuit for receiving a serial signal in synchronization with a clock signal samples the serial signal in synchronization with multiphase sampling clock signals out of phase with the clock signal, determines based on sampled signals that a sampling phase having little effect of phase variation of the serial signal on a sampling result is an optimum phase, performs a reception operation in which a signal sampled by the optimum phase is reception data, and has, as determination operations for the optimum phase, a first mode and a second mode in which optimality of an optimum phase determined in the first mode is determined based on a sampling result of a reduced number of samplings.

Abstract: A method is described for performing an automatic internal trimming operation that can compensate process variation and supply voltage variation in an integrated circuit. A reference signal is applied when the integrated circuit is in an automatic internal trimming mode, and integrated circuit timing is trimmed into a predetermined target range after applying predefined reference cycles.

Abstract: Disclosed herein is a device that includes a first register temporarily storing first information indicative of a reference latency, a second register temporarily storing second information indicative of an offset latency, a third register temporarily storing third information indicative of one of first and second operation modes, and a logic circuit configured to produce latency information in response to the first information when the third information is indicative of the first operation mode and to both of the first information and the second information when the third information is indicative of the second operation mode.

Abstract: In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge.

Abstract: A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes receiving, at a processing unit, a request to change a clock steering rate used to control a TOD-clock offset value for the processing unit, the TOD-clock offset defined as a function of a start time (s), a base offset (b), and a steering rate (r). The unit schedules a next episode start time with which to update the TOD-clock offset value. After updating TOD-clock offset value (d) at the scheduled time, TOD-clock offset value is added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.

Abstract: An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal. The invention includes determining a phase shift relationship between the source clock signal and a signal. When the phase shift relationship is below a predetermined threshold the data is transferred between the source clock domain and the receiving clock domain using a first plurality of stage operations. When the phase shift relationship is above the predetermined threshold, the data is transferred between the source clock domain and the receiving clock domain using a second plurality of stage operations that delay data transfer an additional half period of the source clock signal.

Abstract: A skew adjustor that can reduce inter-pair skew between differential signals received via a cable is disclosed. In one embodiment, a skew adjustor includes: a skew detector that receives signals from a cable, and provides a detected skew amount when skew is detected between two of the signals; an offset controller for receiving the detected skew amount, and for providing a delay control signal in response thereto; and a skew delay circuit that receives the signals and the delay control signal, and enables one or more delay stages in a path of a first arriving of the two skewed signals based on the delay control signal, such that an adjusted skew between the two skewed signals at an output of the skew delay circuit is less than the detected skew amount by an amount corresponding to the enabled one or more delay stages.

Abstract: A measured device coupled to test equipment providing at least two test factors and receiving a test result is disclosed. The measured device includes a combinatorial logic circuit and a main circuit. The combinatorial logic circuit includes a first storage module and a second storage module. The first storage module stores the test factors according to a first operation clock. The second storage module stores and outputs at least two output factors according to a second operation clock. The frequency of the second operation clock is higher than the frequency of the first operation clock. When the test factors are stored in the first storage module, the test factors stored in the first storage module are served as the output factors and the output factors are output and stored in the second storage module. The main circuit generates the test result according to the output factors output by the second storage module.

Abstract: A method and apparatus for a multiple lane transmission system that provides a fixed, low-latency mode of operation with reduced lane-lane skew while process, voltage, and temperature (PVT) variation, as well as other sources of variation, occur over time. Multiplexing techniques are utilized within each transmission lane to allow programmably adaptive use of phase alignment circuitry for various modes of operation. As a result, power consumption and semiconductor die area are reduced because multiple copies of phase alignment circuitry within each transmission lane are not required. Also, injection of additional jitter on the serial outputs due to continuous operation of phase alignment circuitry is prevented. Rather, multiplexers within the phase alignment circuitry selectively adapt the timing architecture to that required by the selected mode of operation.

Abstract: A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal.

Abstract: This disclosure relates to providing an information signal to one or more sub-systems within a wireless communications device, where the information signal enables the sub-systems to operate based on virtually corrected reference frequency clock signal(s).

Abstract: Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.

Abstract: A method for compensating for variations in timing of data sent to a processor on data bit lines relative to a strobe clock sent to the processor on a strobe clock line that can be used in a dual data rate (DDR) memory identifies discrete minimum and maximum time offset values for test data in selected data bit patterns for the data bit lines. The discrete minimum time offset value is the minimum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock. The discrete minimum and maximum time offset values identify a valid range when the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock.

Abstract: To make it possible to appropriately set a capturing timing for a pixel value. For this, the present invention includes a pixel array unit 2 composed of pixels 21 arranged in a row direction and a column direction in a matrix manner and a latch unit 62 provided for each column constituting the pixel array unit 2 and configured to convert a pixel value of the pixel 21 into a digital pixel value to hold the pixel value. Also, the present invention includes a column scanning unit 4 for selecting the latch unit 62, a capturing unit 9 for sequentially capturing the pixel value held by the latch unit selected by the column scanning unit 4 in synchronism with a predetermined clock, and a delay unit 10 for delaying a clock for driving the capturing unit 9 in a plurality of stages. With the configuration described above, first dummy data is set in the latch unit 62-m at the near end, and second dummy data is set in the latch unit 62-0 at the far end.

Abstract: The embodiments disclose a method for encoder frequency-shift compensation, including, determining frequency values of an input encoder signal, analyzing an encoder index clock signal and the input encoder signal to determine values of frequency-shifts and compensating for the values of the frequency-shifts to generate a frequency-shift compensated clock.

Abstract: A serial data receiver circuit apparatus to receive serial data delimited by a first bit length, the circuit apparatus includes: a serial/parallel converter circuit to convert the serial data into parallel data of a second bit length that is smaller than the first bit length; a data hold circuit to hold a plurality of parallel data; a detector circuit to detect a delimiter position in the received serial data; a detected position hold circuit to generate a select signal to select data included in the parallel data stored in the data hold circuit; and a selector circuit to select data in units of the second bit length starting from the data delimiter position based on the select signal.