Built-in Hardware For Diagnosing Or Testing Within-system Component (e.g., Microprocessor Test Mode Circuit, Scan Path) Patents (Class 714/30)
  • Patent number: 8056025
    Abstract: An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is between a top metallization level and a base level on which the functional block is formed in the IC device. The access pad at the metallization level provides a contact to access an underlying circuit of the functional block so that the functional integrity of the functional block of the IC device can be verified during probing.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: November 8, 2011
    Assignee: Altera Corporation
    Inventors: Vijay Chowdhury, Che Ta Hsu, Ada Yu
  • Patent number: 8055946
    Abstract: A semiconductor IC capable of debugging two or more processors at the same time using a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin-Chan Kang, Sun-Kyu Kim
  • Patent number: 8051350
    Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: November 1, 2011
    Assignee: Via Technologies Inc.
    Inventor: Wayne Tseng
  • Patent number: 8051343
    Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
  • Patent number: 8051260
    Abstract: A method for safeguarding data stored in a memory of a data storage system includes monitoring values of a subset of environmental variables associated with the data-storage system and updating a portion of a table containing values of environmental variables associated with the data-storage system. The table includes values for environmental variables that are not in the subset of environmental variables monitored. The values of the environmental variables are then inspected. On the basis of the inspection, a condition in which there exists a high-risk of data loss is determined.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: November 1, 2011
    Assignee: EMC Corporation
    Inventors: Steven T. McClure, Scott B. Gordon, Robert Decrescenzo, Timothy M. Johnson, Zhi-Gang Liu
  • Patent number: 8042012
    Abstract: Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. The quantizing circuit may include an analog-to-digital converter, a switch coupled to the memory element and a feedback signal path coupled to the output of the analog-to-digital converter and to the switch.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: October 18, 2011
    Assignee: Micron Technology, Inc.
    Inventor: R. Jacob Baker
  • Patent number: 8041999
    Abstract: A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method implements one of a selectable plurality of control levels in the command window based on the number of the at least one zero-bit scans.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: October 18, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 8041553
    Abstract: A computer-based system for testing a circuit design for implementation within an integrated circuit device can include a design application (205) providing simulation instructions for testing a circuit design and a simulation driver (225) receiving the simulation instructions and translating the simulation instructions into control protocol instructions specifying operations of an integrated circuit control protocol. The system can include a simulation environment (240). The simulation environment can include a communication module (245) communicating with the simulation driver, a simulation cable driver (250) receiving the control protocol instructions from the simulation driver via the communication module, and a control module (255). The simulation cable driver further can translate the control protocol instructions into signaling information corresponding to the integrated circuit control protocol.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: October 18, 2011
    Assignee: Xilinx, Inc.
    Inventors: Adrian M. Hernandez, Michael E. Darnall
  • Patent number: 8037355
    Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: October 11, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 8037387
    Abstract: Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test pattern 100a given in advance for a logic circuit into an intermediate test pattern 100b of a bit constitution of different logic values, where the constitution elements of the initial test pattern 100a are at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test pattern 100a which meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: October 11, 2011
    Assignees: Japan Science & Technology Agency, Kyushu Institute of Technology, System JD Co., Ltd.
    Inventors: Seiji Kajihara, Kohei Miyase, Xiaqing Wen, Yoshihiro Minamoto, Hiroshi Date
  • Patent number: 8030649
    Abstract: Various techniques for testing multicore processors in an integrated circuit. Each core includes a plurality of registers configured to form at least two scan chains. In one embodiment, a verification unit located in the integrated circuit is electrically coupled to outputs of the scan chains. The verification unit is configured to determine the validity of the outputs of the scan chains and to indicate a malfunction of the integrated circuit if the outputs are determined not to be valid.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventor: Michael K. Gschwind
  • Patent number: 8024627
    Abstract: A semiconductor memory device including a plurality of banks, each including a plurality of memory cells, a pattern signal generator configured to generate pattern signals having combinations in response to an input signal applied through an arbitrary pad in a compression test mode. Input paths are configured to transfer the plurality of pattern signals to the corresponding banks.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: September 20, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seong-Hwi Song
  • Patent number: 8024612
    Abstract: A method is disclosed for determining a configuration for a computer tomograph for the purpose of error diagnosis, a module, a computer tomograph and a system of appropriate design. The computer tomograph includes a multiplicity of detector modules. In at least one embodiment, a respective detector module is designed to have an identification device which is intended to provide a signature, the signature being uniquely associated with the respective module. The detector module transmits the measurement data it captures and its signature. The digital, electronic signature allows remote maintenance of the computer tomograph.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: September 20, 2011
    Assignee: Siemens Aktiengesellschaft
    Inventor: Thomas Hilderscheid
  • Patent number: 8024613
    Abstract: The method comprises and executes constitutional information collection processing of collecting constitutional information of the apparatus, constitutional information of a logical unit which is a logical existence obtained by abstracting the apparatus, constitutional information of the application and constitutional information of the dependency relation of the performance established among the apparatus, the logical unit and the application; performance information collection processing of collecting each performance information of the apparatus, the logical unit and the application; and saturation indication detection processing of analyzing a correlation between a change value with time of the performance information of the apparatus and a change value with time of the performance information of the logical unit having the dependency relation of the performance with respect to the apparatus for a predetermined period, and detecting that the apparatus has the saturation indication, when a correlation coef
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: September 20, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki OCHI, Nobuo Beniyama, Toshiaki Matsuo
  • Patent number: 8024614
    Abstract: A debugger includes: a break detecting circuit which, when the state of a microprocessor core corresponds to a previously set condition, generates a break request signal for requesting a transition of the microprocessor core to a debug state; a trigger detecting circuit which, when a predetermined signal of additional hardware corresponds to a previously set condition, generates a trigger request signal for requesting observation of the predetermined signal; and, an execution control circuit which, when the trigger request signal has been transmitted, outputs a trigger signal for observing the predetermined signal by means of a logic analyzer and outputs a break signal for causing the microprocessor core to transition to the debug state.
    Type: Grant
    Filed: July 4, 2007
    Date of Patent: September 20, 2011
    Assignee: NEC Corporation
    Inventor: Kouhei Nadehara
  • Patent number: 8015550
    Abstract: A system for hazards analysis includes: a memory device for storing a program; a processor in communication with the memory device, the processor operative with the program to: access the memory device to obtain information specifying a system to be analyzed; build functional block diagrams using the information specifying the system to be analyzed; receive user-input hazards analysis elements; and use the functional block diagrams, the user-input hazards analysis elements and tree fault analysis for hazards analysis.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: September 6, 2011
    Assignee: Siemens Corporation
    Inventors: Brian Berenbach, Marcus Kornek
  • Patent number: 8015447
    Abstract: A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Limited
    Inventors: Hideo Yamashita, Ryuji Kan
  • Patent number: 8015448
    Abstract: A storage controller including a first controller. The first controller includes a memory module, a test access port controller, the test access port controller configured to control a built in self-test operation on the memory module, and a register configured to store a first instruction. In response to the storage controller detecting a test access port interface being accessible to the storage controller, the test access port controller is configured to control the built in self-test operation on the memory module of the first controller by having either (i) a second instruction sent from the test access port controller to the first controller or (ii) the first instruction sent from the register to the first controller. The first controller is configured to perform the built in self-test operation on the memory module in response to having received the first instruction or having received the second instruction.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: September 6, 2011
    Assignee: Marvell International Ltd.
    Inventor: Dinesh Jayabharathi
  • Patent number: 8010935
    Abstract: An electronic design automation (EDA) tool for and method of optimizing a placement of process monitors (PMs) in an integrated circuit (IC). In one embodiment, the EDA tool includes: (1) a critical path/cell identifier configured to identify critical paths and critical cells in the IC, (2) a candidate PM position identifier coupled to the critical path/cell identifier and configured to identify a set of candidate positions for the PMs, (3) a cluster generator coupled to the critical path/cell identifier and configured to associate the critical cells to form clusters thereof and (4) a PM placement optimizer coupled to the candidate PM position identifier and the cluster generator and configured to place a PM within each of the clusters by selecting among the candidate positions.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: August 30, 2011
    Assignee: LSI Corporation
    Inventors: Alexander Tetelbaum, Sreejit Chakravarty
  • Patent number: 8010826
    Abstract: Reconfigurable circuits, methods, and systems with reconfigurable interconnect devices, clusters of reconfigurable logic devices, and a programming interface configured to receive configuration data to configure a first combination of the reconfigurable interconnect and logic devices to implement a circuit, and to remap a portion of the received configuration data, corresponding to a defective cluster, from the defective cluster to another non-defective cluster of the plurality of clusters to configure a second combination of the reconfigurable interconnect and logic devices to implement the circuit.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: August 30, 2011
    Assignee: Meta Systems
    Inventors: Frédéric Réblewski, Olivier V. LePape
  • Publication number: 20110209003
    Abstract: An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.
    Type: Application
    Filed: February 18, 2011
    Publication date: August 25, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuya MATSUKAWA
  • Publication number: 20110209002
    Abstract: A programmable characterization-debug-test engine (PCDTE) on an integrated circuit chip. The PCDTE includes an instruction memory that receives and stores instructions provided on a chip interface, and a configuration memory that receives and stores configuration values provided on the chip interface. The PCDTE also includes a controller that configures a plurality of address counters and data registers in response to the configuration values. The controller also executes the instructions, wherein read/write addresses and write data are retrieved from the counters in response to the instructions. The retrieved read/write addresses and write data are used to access a memory under test. Multiple ports of the memory under test may be simultaneously accessed. Multiple instructions may be linked. The instructions may specify special counting functions within the counters and/or specify integrated (linked) counters.
    Type: Application
    Filed: February 18, 2011
    Publication date: August 25, 2011
    Applicant: MOSYS, INC.
    Inventor: Rajesh Chopra
  • Patent number: 8006148
    Abstract: A test mode control circuit of a semiconductor memory device includes an input unit configured to input test mode data for at least one of a plurality of test modes, and a test mode controlling unit configured to enable/disable a test mode according to the number of inputs of the test mode data.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: August 23, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Bo-Yeun Kim
  • Patent number: 8001427
    Abstract: A method and system of indexing into trace data based on entries in a log buffer. At least some of the illustrative embodiments are methods comprising executing a traced program on a target device. The traced program writes entries to a log buffer within the target device, and the traced program also contemporaneously writes an index value for each entry to a register. The index value written to the register becomes part of trace data regarding the traced program and correlates each entry to a respective portion of the trace data. Using the information one may either or both: display on a display device a portion of the trace data (the portion selected based on selecting an entry from the log buffer); or display on the display a portion of the log buffer (the portion selected based on selecting an entry from the trace data).
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: August 16, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Oliver P. Sohm, Brian Cruickshank, Manisha Agarwala
  • Patent number: 8001423
    Abstract: A universal on-board system is provided for automatic fault detection and on-the-spot repair instructions that includes a module adapted to be coupled to a wide variety of platforms and Line Replaceable Units.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: August 16, 2011
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Carolyn Spier, Daniel E. Mills
  • Patent number: 8000826
    Abstract: One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: August 16, 2011
    Assignee: Synopsys, Inc.
    Inventors: Jianfeng Luo, Subarnarekha Sinha, Qing Su, Charles C. Chiang
  • Patent number: 8001453
    Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Uemura, Yasuyuki Inoue
  • Patent number: 7992048
    Abstract: Provided is a computer system including at least one host computer; and at least one storage system, characterized in that: the storage system has a disk drive and a disk controller, and provides a storage area of the disk drive as at least one logical unit; upon detecting a failure in a logical path serving as an access route from the host computer to the logical unit, the host computer specifies logical paths for accessing the same logical unit that is connected to the logical path where the failure is detected; the host computer executes failure detecting processing for the specified logical paths to judge whether the specified logical paths are normal or not; the host computer selects normal logical paths out of the specified logical paths; and the host computer accesses the logical unit via the normal logical paths selected.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: August 2, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Komatsu, Makoto Aoki
  • Patent number: 7991727
    Abstract: Some embodiments of a fact type abstraction mechanism of a rule engine have been presented. In one embodiment, a fact type abstraction layer is provided to a rule engine core to allow the rule engine core to access facts of multiple different types. Further, the rule engine core is used to process the facts of multiple different types against a predetermined set of rules without converting the facts of multiple different types into a native type.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: August 2, 2011
    Assignee: Red Hat, Inc.
    Inventors: Mark Proctor, Edson Tirelli
  • Patent number: 7987453
    Abstract: A method, apparatus, and computer instructions for determining computer flows autonomically using hardware assisted thread stack and cataloged symbolic data. When a new thread is spawned during execution of a computer program, new thread work area is allocated by the operating system in memory for storage of call stack information for the new thread. Hardware registers are set with values corresponding to the new thread work area. Upon context switch, values of the registers are saved in a context save area for future restoration. When call stack data is post-processed, the operating system or a device driver copies call stack data from the thread work areas to a consolidated buffer and each thread is mapped to a process. Symbolic data may be obtained based on the process identifier and address of the method/routine that was called/returned in the thread. Corresponding program flow is determined using retrieved symbolic data and call stack data.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jimmie Earl DeWitt, Jr., Frank Eliot Levine, Christopher Michael Richardson, Robert John Urquhart
  • Patent number: 7987438
    Abstract: A design structure embodied in a machine readable storage medium for at designing, manufacturing, and/or testing a design is disclosed for initializing expansion adapters installed in a computer system having similar expansion adapters that include detecting an expansion adapter installed in a computer system having a plurality of expansion adapters, the detected expansion adapter having an option ROM containing initialization code, identifying similar expansion adapters installed in the computer system that correspond to the detected expansion adapter, each of the identified similar expansion adapters having an option ROM containing initialization code, disabling the option ROM of each of the identified similar expansion adapters, and initializing the plurality of expansion adapters installed in the computer system without executing the initialization code of the identified similar expansion adapters.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert H. C. Lin, Prasenjit Roy, William B. Schwartz
  • Patent number: 7987387
    Abstract: There is provided a file sharing system which allows accessing a memory that stores failure information and using the failure information even in a case where a CPU is shut down. When a failure occurs on a substrate, a control circuit on the substrate detects the failure and stores the information on the failure to an NVRAM. In a normal case, an OS loads the failure information and transmits it to a PC for maintenance. Upon shut down of the OS, a BMC loads the failure information from the NVRAM according to an instruction from the PC for maintenance. If an operator operates a manual switch upon power shut down, the BMC operates with the power supply from a battery, and the failure information is obtained from the NVRAM.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: July 26, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Shigenori Murakami, Akira Murotani
  • Patent number: 7984344
    Abstract: An integrated circuit includes a memory circuit, a read address register coupled to a read address port of the memory circuit, a write address register coupled to a write address port of the memory circuit, and a multiplexer configurable to transmit a read address bit from the write address register to the read address register in response to a read control signal. The read address register loads the read address bit into the memory circuit through the read address port during a test of the memory circuit. The integrated circuit may include a multiplexer configurable to transmit a write address bit from the read address register to the write address register in response to a write control signal. The write address register loads the write address bit into the memory circuit through the write address port during the test of the memory circuit.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: July 19, 2011
    Assignee: Altera Corporation
    Inventors: Chin Hai Ang, Tze Sin Tan, Ala-Uddin Ismail, Siew Ling Yeoh
  • Patent number: 7984351
    Abstract: A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: July 19, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jonathan M. Owen, Michael J. Osborn
  • Patent number: 7984331
    Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: July 19, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7984350
    Abstract: Logic circuitry has a test point to detect a signal about a delay fault propagating on a logic path between an input terminal and an output terminal, the test point being coupled to the logic path, wherein the test point includes a delay component to delay timing to detect the signal about a delay fault propagating on the logic path by predetermined time.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: July 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Shuji Hamada
  • Patent number: 7984347
    Abstract: A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: July 19, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 7984352
    Abstract: A system comprises built-in self-test (BIST) logic configured to perform a BIST, processing logic coupled to the BIST logic and storage logic coupled to the processing logic. The storage logic comprises debug context information associated with a debugging session. Prior to performance of the BIST, the processing logic stores the debug context information to a destination. After performance of the BIST, the processing logic is reset, and the processing logic restores the debug context information from the destination to the storage logic.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 19, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Karl F. Greb
  • Patent number: 7979746
    Abstract: Processor assemblies and modules are provided. One processor assembly includes first and second processors, and first and second input/output (I/O) interfaces coupled to the first and second processors. The first and/or second I/O interfaces are configured to compare outputs of the first and second processors, and render the first and second processors inactive if the outputs are different. One processor module includes first and second buses coupled to first and second processor assemblies. The first processor assembly includes first and second processors coupled to first and second I/O interfaces, wherein the first I/O interface is coupled to the first bus and the second I/O interface is coupled to the second bus. The second processor assembly includes third and fourth processors coupled to third and fourth I/O interfaces, wherein the third I/O interface is coupled to the first bus and the fourth I/O interface is coupled to the second bus.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: July 12, 2011
    Assignee: Honeywell International Inc.
    Inventors: Brian Cornelius, Mitch Fletcher, James Alexander Ross, David Scheid
  • Patent number: 7979745
    Abstract: An on-chip debug emulator is capable of connecting to the target device and the host device for remotely debugging the program in the target device. The on-chip debug emulator contains a debug communication control unit. This debug communication control unit contains a plurality of serial communication circuits, the plurality of serial communication circuits are commonly provided with a clock signal. The debug communication control unit controls communications with the target device based on commands output from the host device. Each of The plurality of serial communication circuits contains a data buffer and serially transmits data stored in the data buffer to and from the target device while synchronized with the clock signal. Namely, the plurality of serial communication circuits communicate in parallel while operating synchronized with the same clock. The on-chip debug emulator can in this way be made utilizing a low-cost microcomputer not containing any parallel communication circuits.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: July 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Moroda
  • Patent number: 7979749
    Abstract: A method and infrastructure for a diagnosis and/or repair mechanism in a computer system, that includes an auxiliary service system running on the computer system.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Joefon Jann, Pratap Chandra Pattnaik, Ramanjaneya Sarma Burugula
  • Patent number: 7979759
    Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Carnevale, Elianne A. Bravo, Kevin C. Gower, Gary A. Van Huben, Donald J. Ziebarth
  • Patent number: 7979754
    Abstract: A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: July 12, 2011
    Assignee: Oracle America, Inc.
    Inventors: Robert J. Drost, Ronald Ho, Justin M. Schauer
  • Patent number: 7975193
    Abstract: Described embodiments provide for end-of-life (EOL) checking for NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device operative to store one or more data elements. In the illustrative implementation, the EOL data processing and storage management paradigm allows for the storage of data according using a selected EOL enforcement algorithm that can utilize current and/or historical correction levels. The NAND data storage EOL checking module can be operable to cooperate with one or more NAND data store components to execute one or more selected EOL operations to protect stored data.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: July 5, 2011
    Assignee: LSI Corporation
    Inventor: Joshua Johnson
  • Publication number: 20110161735
    Abstract: A semiconductor device is capable of being coupled to first and second debuggers, the first and second debuggers being capable of debugging a program in the semiconductor device. The semiconductor device includes a first chip, and a second chip that is coupled to the first chip. The first chip includes a first processing unit that executes a first instruction group, and a first debug control unit capable of being coupled to the first debugger to control a communication with the first debugger.
    Type: Application
    Filed: March 4, 2011
    Publication date: June 30, 2011
    Applicant: Renesas Electronics Corporation
    Inventor: Shinji Niijima
  • Patent number: 7966581
    Abstract: Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: June 21, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Dadi Setiadi, Hai Li, Haiwen Xi, Hongyue Liu
  • Patent number: 7966536
    Abstract: A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ralf Ludewig, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Tobias Webel
  • Patent number: 7962794
    Abstract: A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: June 14, 2011
    Assignee: Broadcom Corporation
    Inventors: James D. Bennett, Jeyhan Karaoguz
  • Patent number: 7961885
    Abstract: In one embodiment, a system comprises JTAG functionality that implements at least a portion of a JTAG protocol. The JTAG functionality supports a test data in (TDI) line, a test data out (TDO) line, a test rest (TR) line, a test mode state (TMS) line, and a test clock (TCLK) line. The system further comprises a debug interface to communicatively couple the system to a debug device external to the system. The debug interface comprises a transmit (TX) line, receive (RX) line, and a clock (CLK) line. The system transmits data output by the JTAG functionality on the TDI input on the RX line of the debug interface and receives data from the debug device on the TX line of the debug interface and provides the received data to the JTAG functionality on the TDO line, TR line and the TMS line.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: June 14, 2011
    Assignee: Honeywell International Inc.
    Inventors: Edwin D. Cruzado, William J. Dalzell, Brian R. Bernier
  • Patent number: 7962814
    Abstract: A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises sequencing through a sequence of the states, and detecting a predetermined sequence of the states. The predetermined sequence of the states represents a no-operation for at least one of the modes and also represents a mode change command.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: June 14, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda