Built-in Hardware For Diagnosing Or Testing Within-system Component (e.g., Microprocessor Test Mode Circuit, Scan Path) Patents (Class 714/30)
  • Patent number: 7966581
    Abstract: Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: June 21, 2011
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Dadi Setiadi, Hai Li, Haiwen Xi, Hongyue Liu
  • Patent number: 7966536
    Abstract: A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ralf Ludewig, Walter Niklaus, Dietmar Schmunkamp, Scott Barnett Swaney, Tobias Webel
  • Patent number: 7962794
    Abstract: A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: June 14, 2011
    Assignee: Broadcom Corporation
    Inventors: James D. Bennett, Jeyhan Karaoguz
  • Patent number: 7962814
    Abstract: A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises sequencing through a sequence of the states, and detecting a predetermined sequence of the states. The predetermined sequence of the states represents a no-operation for at least one of the modes and also represents a mode change command.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: June 14, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 7961885
    Abstract: In one embodiment, a system comprises JTAG functionality that implements at least a portion of a JTAG protocol. The JTAG functionality supports a test data in (TDI) line, a test data out (TDO) line, a test rest (TR) line, a test mode state (TMS) line, and a test clock (TCLK) line. The system further comprises a debug interface to communicatively couple the system to a debug device external to the system. The debug interface comprises a transmit (TX) line, receive (RX) line, and a clock (CLK) line. The system transmits data output by the JTAG functionality on the TDI input on the RX line of the debug interface and receives data from the debug device on the TX line of the debug interface and provides the received data to the JTAG functionality on the TDO line, TR line and the TMS line.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: June 14, 2011
    Assignee: Honeywell International Inc.
    Inventors: Edwin D. Cruzado, William J. Dalzell, Brian R. Bernier
  • Patent number: 7962792
    Abstract: A non-volatile storage subsystem maintains, and makes available to a host system, monitor data reflective of a likelihood of a data error occurring. The monitor data may, for example, include usage statistics and/or sensor data. The storage subsystem transfers the monitor data to the host system over a signal interface that is separate from the signal interface used for standard storage operations. This interface may be implemented using otherwise unused pins/signal lines of a standard connector, such as a CompactFlash or SATA connector. Special hardware may be provided in the storage subsystem and host system for transferring the monitor data over these signal lines, so that the transfers occur with little or no need for host-software intervention. The disclosed design reduces or eliminates the need for host software that uses non-standard or “vendor-specific” commands to retrieve the monitor data.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: June 14, 2011
    Assignee: SiliconSystems, Inc.
    Inventors: Mark S. Diggs, David E. Merry, Jr.
  • Patent number: 7962793
    Abstract: A method, apparatus, and computer instructions for self-diagnosing remote I/O enclosures with enhanced FRU callouts. When a failure is detected on a RIO drawer, a data processing system uses the bulk power controller to provide an alternate path, rather than using the existing RIO links, to access registers on the I/O drawers. The system logs onto the bulk power controller, which provides a communications path between the data processing system and the RIO drawer. The communications path allows the data processing system to read all of the registers on the I/O drawer. The register information in the I/O drawer is then analyzed to diagnose the I/O failure. Based on the register information, the data processing system identifies a field replacement unit to repair the I/O failure.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mike C. Duron, Mark D. McLaughlin
  • Patent number: 7958413
    Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: June 7, 2011
    Assignee: Marvell International Ltd.
    Inventors: Winston Lee, Albert Wu, Chorng-Lii Liou
  • Patent number: 7958438
    Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Uemura, Yasuyuki Inoue
  • Patent number: 7958405
    Abstract: An automatic testing system and method for judging whether a universal serial bus device is configured to a computer are provided. The automatic testing system includes a computer and a testing device for testing the universal serial bus device. By judging whether the universal serial bus device is configured to the computer, the automatic testing system could determine the timing of performing an automatic testing procedure on the universal serial bus device.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: June 7, 2011
    Assignee: Primax Electronics Ltd.
    Inventor: Pei-Ming Chang
  • Patent number: 7958472
    Abstract: To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: June 7, 2011
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux, Yasunari Kanzawa
  • Publication number: 20110126051
    Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.
    Type: Application
    Filed: October 13, 2010
    Publication date: May 26, 2011
    Inventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge
  • Patent number: 7949920
    Abstract: A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all flip-flops in the core. The partial residual test mode spans across a subset of the cores and allows to bound the number of cores that a full residual test mode may span across. The interaction of the cores among one another at the top-level is analyzed and the minimum number of flip-flops in a core that must participate in a intermediate test mode is selected. Algorithms are devised to analyze the interactions among the cores and build data structures which are used for identifying intermediate test modes. Using a reconfigurable scan segment architecture, intermediate test modes are implemented that are designed to work with all known test compression solutions.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 24, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Varadarajan R. Devanathan, Chennagiri P. Ravikumar
  • Patent number: 7949914
    Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: May 24, 2011
    Assignee: ARM Limited
    Inventors: Peter Logan Harrod, Edmond John Simon Ashfield, Thomas Sean Houlihane, Paul Kimelman, Simon John Craske, Michael John Williams
  • Patent number: 7949913
    Abstract: A method for storing a memory defect map is disclosed whereby a memory component is tested for defects at the time of manufacture and any memory defects detected are stored in a memory defect map and used to optimize the system performance. The memory defect map is updated and the system's remapping resources optimized as new memory defects are detected during operation.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: May 24, 2011
    Assignee: Dell Products L.P.
    Inventors: Forrest E. Norrod, Jimmy D. Pike, Tom L. Newell
  • Patent number: 7949919
    Abstract: The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test signal through the shared pins. Pins necessary for the microelectronic device are therefore reduced.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: May 24, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsiang-Huang Wu, Ming-Je Li, Jih-Nung Lee
  • Patent number: 7945824
    Abstract: An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: May 17, 2011
    Assignee: Rambus Inc.
    Inventors: Adrian E. Ong, Naresh Baliga
  • Patent number: 7944234
    Abstract: Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kirsten S. Lunzer, Jeffrey J. Rooney
  • Patent number: 7945831
    Abstract: Various apparatuses, methods and systems for dual JTAG controllers with shared pins disclosed herein. For example, some embodiments provide a boundary scan apparatus having a first boundary scan circuit with a first plurality of control inputs, a second boundary scan circuit with a second plurality of control inputs, and a plurality of boundary scan control signals connected to the first plurality of control inputs on the first boundary scan circuit and to the second plurality of control inputs on the second boundary scan circuit. At least two of the plurality of boundary scan control signals are connected between the first boundary scan circuit and the second boundary scan circuit in a crossover fashion.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: May 17, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Robert B. Wong
  • Patent number: 7945823
    Abstract: A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator (202) that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (216). An address range selector circuit (230) can limit the range of addresses generated by an address generator (234). Once defective addresses for a first range have been detected, an address range selector circuit (230) can test another range. An entire address range can thus be tested regardless of the depth of a fault address store (216).
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: May 17, 2011
    Assignee: Netlogic Microsystems, Inc.
    Inventors: Ramesha Doddamane, Eswar Vadlamani, Gopalakrishnan Perur Krishnan, Tarjinder Singh
  • Publication number: 20110113286
    Abstract: A scan test circuit for a memory with a first memory cell column, a second memory cell column that replaces a failed column of the first memory cell column, a first switching circuit that connects one of the memory cell columns to a first peripheral circuit disposed at an input side, and a second switching circuit that connects one of the memory cell columns to a second peripheral circuit disposed at an output side, comprises: a test priority control circuit that controls the switching circuits to establish at least two patterns of connections of the memory cell columns to the peripheral circuits; and a test point circuit that includes scan flip-flop circuits employed in a scan test for detecting a delay fault of the peripheral circuits, and is disposed between the memory cell columns and the first switching circuit.
    Type: Application
    Filed: November 8, 2010
    Publication date: May 12, 2011
    Inventors: Yukitsugu TAKASUKA, Masaki Asai
  • Patent number: 7941702
    Abstract: An ECU that controls an engine of a vehicle includes a MPU and an IC that monitors the operation of the MPU. The MPU is programmed to execute a verification result check and test selection function for selecting a test for verifying the function of the MPU. The MPU runs the selected test, and transmits a test result indicating the result of the test to the IC. The IC checks whether the test result from the MPU is correct or incorrect, and transmits a verification result to the MPU.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: May 10, 2011
    Assignee: DENSO Corporation
    Inventor: Akira Ito
  • Patent number: 7936875
    Abstract: A method and a circuit for protecting a digital quantity stored in a microcontroller including a JTAG interface, including the step of making the digital quantity dependent from a value stored in non-volatile fashion in the microcontroller and made inaccessible if signals are present at the input of the JTAG interface.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: May 3, 2011
    Assignee: STMicroelectronics S.A.
    Inventor: Fabio Sozzani
  • Patent number: 7930601
    Abstract: A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Joseph Eckelman, Donato O. Forlenza, Orazio P. Forlenza, William J. Hurley, Thomas J. Knips, Gary William Maier, Phong T. Tran
  • Patent number: 7930592
    Abstract: A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael Richard Ouellette, Jeremy Rowland
  • Patent number: 7930165
    Abstract: A method and corresponding equipment for emulation of a target programmable unit, which has at least one CPU, by means of an external emulation device, which is coupled to the target programmable unit by means of a communication link, comprising: transferring predetermined initialization data through the communication link to the emulation device for initializing the emulation; transferring through the communication link to the emulation device a CPU clock signal and emulation data; emulating the target programmable unit in the external emulation device using the transferred emulation data; ascertaining respective trace data from the emulation in the external emulation device and storing and/or outputting the trace data; deriving respective target integrity-control data and emulation integrity-control data from respective target-internal data and emulation-internal data; and transferring the derived target integrity-control data from the target programmable unit to the external emulation device.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: April 19, 2011
    Assignee: Accemic GmbH & Co. KG
    Inventors: Alexander Weiss, Alexander Lange
  • Patent number: 7930604
    Abstract: A system for receiving serial messages from a device under test includes a deserializer configured to i) receive the serial messages and, ii) based on the serial messages, form data frames. A frame sync module is configured to form Joint Task Action Group (JTAG) data bits based on the data frames. A plurality of virtual JTAG test access ports are configured to i) receive the JTAG data bits and ii) shift the JTAG data bits between the plurality of virtual JTAG test access ports.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: April 19, 2011
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Ho, Daniel Smathers
  • Patent number: 7925949
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: April 12, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Patent number: 7921346
    Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Bryan J. Robbins, Phong T. Tran
  • Patent number: 7917821
    Abstract: A system on chip (SOC) may include function blocks, and a scan chain in each of the function blocks, the scan chains being adapted to conduct scan test operations in sync with a respective one of a plurality of clock signals having a different phase relative to each other, wherein during an isolation mode, the scan chains test combination circuits of the function blocks, and during an interface mode, the scan chains of adjacent ones of the function blocks test combination circuits between the adjacent ones of the function blocks.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: March 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hoi-Jin Lee
  • Patent number: 7917823
    Abstract: A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: David Dehnert, Matthew Heath
  • Patent number: 7917818
    Abstract: A semiconductor device includes a volatile memory for storing a first instruction group, a first processing unit for executing the first instruction group, a nonvolatile memory for storing a second instruction group, a second processing unit for executing a second instruction group, a control signal output unit for outputting a control signal to specify permission or prohibition of executing a debugging function to the first processing unit, and a debug control unit for controlling execution of the debugging function by the first processing unit based on the control signal.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: March 29, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Shinji Niijima
  • Patent number: 7913120
    Abstract: A data processing system 2 has a memory 6 with a memory address space incorporating a plurality of domains, each domain comprising a set of memory addresses as defined by programmable domain specifying data 32. A processor core 8 executes program instructions fetched from the memory 6. Diagnostic control circuitry 20 is responsive to the domain in which a currently executing program instruction is stored to selectively disable diagnostic circuitry 14, 16, 18 used to perform diagnostic functions upon the data processing system 2. The diagnostic control circuitry 20 is responsive to diagnostic-capability-defining data 36 associated with the domains to indicate which diagnostic circuitry 14, 16, 18 is enabled for which domains.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: March 22, 2011
    Assignee: ARM Limited
    Inventors: Michael John Williams, Daniel Kershaw
  • Patent number: 7913142
    Abstract: A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithmetic unit to a test mode, in which a first scan chain of the first arithmetic unit is accessible; reading the first test data from the second memory unit; shifting the first test data which have been read through the first scan chain of the first arithmetic unit switched to the test mode for providing test result data for the first arithmetic unit; checking the provided test result data for plausibility for providing a test result for the first arithmetic unit.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: March 22, 2011
    Assignee: Robert Bosch GmbH
    Inventor: Axel Aue
  • Patent number: 7913121
    Abstract: A method for debugging a read only memory (ROM) in a wireless target device is disclosed. A wireless communication link is established between the target device and a host computer. A debug mode change command is received from the host computer by the application program running on the target device via a wireless communication interface in the target device. The wireless communication interface is parsed with the monitor program. A debug instruction is received by the monitor program from a debugger in the host computer where the debug instruction includes an entry address and a jump address. The application program jumps to the received jump address upon reaching the entry address location. An acknowledgement is transmitted from the target device to the debugger in the host computer, and, in response to the acknowledgement, a second debug instruction is received from the debugger in the host computer.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: March 22, 2011
    Assignee: Broadcom Corporation
    Inventor: Wenkwei Lou
  • Patent number: 7912669
    Abstract: A process for a prognosis of faults in electronic circuits identifies parameters of a circuit under test. An upper and a lower limit is determined for one or more components of the circuit under test. A population of faulty and non-faulty circuits are generated for the circuit under test, and feature vectors are generated for each faulty and non-faulty circuit. The feature vectors are stored in a fault dictionary, and a feature vector for an implementation of the circuit under test in a field operation is generated. The feature vector for the implementation of the circuit under test in the field operation is compared to the feature vectors in the fault dictionary.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: March 22, 2011
    Assignee: Honeywell International Inc.
    Inventor: Sumit K. Basu
  • Patent number: 7913123
    Abstract: An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: March 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ra'ed Mohammad Al-Omari, Alexander Erik Mericas, William John Starke
  • Patent number: 7908530
    Abstract: A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: March 15, 2011
    Assignee: Faraday Technology Corp.
    Inventor: Cheng-Chien Chen
  • Patent number: 7908520
    Abstract: ASICs or like fabrication-preprogrammed hardware provide controlled power and recovery signals to a computing system that is made up of commercial, off-the-shelf components—and that has its own conventional hardware and software fault-protection systems, but these are vulnerable to failure due to external and internal events, bugs, human malice and operator error. The computing system preferably includes processors and programming that are diverse in design and source. The hardware infrastructure uses triple modular redundancy to test itself as well as the computing system, and to remove failed elements—powering up and loading data into spares. The hardware is very simplified in design and programs, so that bugs can be thoroughly rooted out. Communications between the protected system and the hardware are protected by very simple circuits with duplex redundancy.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: March 15, 2011
    Assignee: A. Avizienis and Associates, Inc.
    Inventor: Algirdas Avizienis
  • Patent number: 7904768
    Abstract: A probing system for an integrated circuit device, which transmits a testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes a test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform a test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing.
    Type: Grant
    Filed: May 3, 2008
    Date of Patent: March 8, 2011
    Assignee: National Tsing Hua University
    Inventors: Cheng-Wen Wu, Chih-Tsun Huang, Yu-Tsao Hsing
  • Patent number: 7904701
    Abstract: Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventors: Anthony Babella, Allan Wong, Lance Cheney, Brian D. Rauchfuss
  • Patent number: 7904653
    Abstract: A disk order examining system for a dual-controller redundant storage device and method thereof, implementing in a dual-controller redundant device with a master controller and a slave controller. Examining if the linkage orders of the disks to the master controller are the same as those of the slave controller by sequentially writing random values into each disk of a disk concatenation, and then reading out to discriminate their sequence.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: March 8, 2011
    Assignee: Inventec Corporation
    Inventors: Chih-Wei Chen, Hsiao-Fen Lu
  • Publication number: 20110050272
    Abstract: A test controller switches the operation of output stages in an integrated circuit between a normal operation mode and a test mode. The output stages are respectively connected to switch elements. A level shifter generates a switch signal for controlling activation and deactivation of the switch elements in accordance with the normal operation mode and the test mode.
    Type: Application
    Filed: September 2, 2009
    Publication date: March 3, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventor: Hiroyuki KIMURA
  • Patent number: 7900090
    Abstract: Systems and methods (“utility”) for providing a computer system with a mechanism to record live data on a continuous basis which may be analyzed subsequent to a fault condition is provided. The utility uses the existing DRAM memory of a computer system as a retentive DRAM (RDRAM) device that may be used to store the data. To accomplish this, software and firmware is provided for continuously refreshing the DRAM memory across resets that are due to fault conditions. Further, non-maskable interrupts (NMI) are used to flag a variety of fault conditions to the computer system. To make the utility platform independent, a standardized power and configuration interface is used to implement a computer system reset that preserves the contents of the RDRAM.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: March 1, 2011
    Assignee: Oracle America, Inc.
    Inventors: Sanjay Agrawal, Thomas W. Simons, Peter Heffernan, Daniel J. Delfatti, Jr.
  • Patent number: 7895484
    Abstract: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: February 22, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Tanaka, Yuji Nakagawa
  • Patent number: 7895488
    Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: February 22, 2011
    Assignee: Marvell International Ltd.
    Inventor: Darren Bertanzetti
  • Publication number: 20110041010
    Abstract: A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system.
    Type: Application
    Filed: October 27, 2010
    Publication date: February 17, 2011
    Inventor: Albrecht MAYER
  • Patent number: 7890790
    Abstract: According to some embodiments, a first bus may be monitored, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: February 15, 2011
    Assignee: Intel Corporation
    Inventor: Steven Tu
  • Patent number: 7890804
    Abstract: A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor memory bus to the memory bus in the first operational mode. In the second operational mode the device accepts from the test bus a starting memory address for memory reads and writes, and automatically and independently of the test bus adjusts a memory address for reads and writes during burst memory operations.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 15, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Gregory J. Mann, Robert S. Hoffman
  • Publication number: 20110029813
    Abstract: An interface processes memory redundancy data on an application specific integrated circuit (ASIC) with self-repairing random access memory (RAM) devices. The interface includes a state machine, a counter, and an array of registers. The state machine is coupled to a redundancy chain. The redundancy chain includes coupled redundant elements of respective memory elements on the ASIC. In a shift-in mode, the interface shifts data from each of the elements in the redundancy chain and compresses the data in the array of registers. The interface communicates with a test access port coupled to one or more eFuse devices to store and retrieve the compressed data. In a shift-out mode, the interface decompresses the data stored in the array of registers and shifts the decompressed data to each unit in the redundancy chain. The interface functions absent knowledge of the number, bit size and type of self-repairing RAM devices in the redundancy chain.
    Type: Application
    Filed: August 2, 2009
    Publication date: February 3, 2011
    Applicant: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
    Inventors: Rosalee Gunderson, Dale Beucler, Louise A. Koss