Built-in Hardware For Diagnosing Or Testing Within-system Component (e.g., Microprocessor Test Mode Circuit, Scan Path) Patents (Class 714/30)
  • Patent number: 9812223
    Abstract: A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: November 7, 2017
    Assignee: SK Hynix Inc.
    Inventor: Tae Hoon Kim
  • Patent number: 9810740
    Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: November 7, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9804911
    Abstract: A method includes holding a definition of multiple software-implemented tests for testing one or more hardware units of an Integrated Circuit (IC), and of invocation conditions that specify whether the tests are permitted to run. The tests are applied to the hardware units at least partially in parallel, using a processor in the IC, by repeatedly tracking respective execution states of the tests and evaluating the invocation conditions, and invoking a test that currently does not run but is permitted to run in accordance with the invocation conditions.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: October 31, 2017
    Assignee: APPLE INC.
    Inventors: Amir Nahir, Randal S. Thelen, Yair Dagan, Yuval Gonczarowski
  • Patent number: 9785462
    Abstract: A method and apparatus for registering a user-handler in hardware for transactional memory is herein described. A user-accessible register is to hold a reference to a transactional handler. An event register may also be provided to specify handler events, which may be done utilizing user-level software, privileged software, or by hardware. When an event is detected execution vectors to the transaction handler based on the reference to the transactional handler held in the user-accessible register. The transactional handler handles the event and then execution returns to normal flow.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Gad Sheaffer, Shlomo Raikin, Vadim Bassin
  • Patent number: 9766964
    Abstract: A process to detect a failure of a constituent system (110 . . . 113) in a system of systems (1) consisting of a number of constituent systems (111 . . . 113) which exchange messages through a communications system (120), in which every constituent system (111 . . .
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: September 19, 2017
    Assignee: FTS COMPUTERTECHNIK GMBH
    Inventor: Hermann Kopetz
  • Patent number: 9766999
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to increment upon occurrence of a non-precise event in the processing device. The processing device also includes a precise event based sampling (PEBS) enable control communicably coupled to the performance counter. The processing device also includes a PEBS handler to generate and store a PEBS record including an architectural metadata defining a state of the processing device at a time of generation of the PEBS record. The processing device further includes a non-precise event based sampling (NPEBS) module communicably coupled to the PEBS control and the PEBS handler. The NPEBS module causes the PEBS handler to generate the PEBS record for the non-precise event upon overflow of the performance counter.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Jonathan D. Combs, Michael W. Chynoweth, Jason W. Brandt, Corey D. Gough
  • Patent number: 9761328
    Abstract: A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. The semiconductor device may generate a plurality of control codes from the command/address signals in a test mode according to a combination of the command/address signals. The semiconductor device may output a first output datum generated by serializing the plurality of control codes, and the first output datum, through a single pad.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: September 12, 2017
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Yong Suk Joo
  • Patent number: 9746516
    Abstract: A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches table. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. The related latches table is created by tracing from a target latch.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: August 29, 2017
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, William V. Huott, Mary P. Kusko
  • Patent number: 9746518
    Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 29, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9733306
    Abstract: Remote evaluation, e.g., web-based evaluation, lowers the evaluation barrier by allowing an engineer to gain experience with an integrated circuit (IC) using a client (e.g. a web browser) on a remote computer (e.g., a machine remote from the IC being evaluated but local to the engineer) to activate a test set-up that is maintained at a location that is far away from the engineer.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: August 15, 2017
    Assignee: ANALOG DEVICES GLOBAL
    Inventors: Richard E. Schreier, Alexander Newcombe, Ross Willett, Andre Straker
  • Patent number: 9727754
    Abstract: Some embodiments include a method for processing a scan chain in an integrated circuit, the method comprising receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; storing the scan chain in a first plurality of latches; storing the secret key pattern in a second plurality of latches; comparing the secret key pattern to a reference key pattern, the reference key pattern stored in a third plurality of latches; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benedikt Geukes, Bodo Hoppe, Matteo Michel, Juergen Wakunda
  • Patent number: 9720040
    Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: August 1, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
  • Patent number: 9710367
    Abstract: A set of automated unit test components is stored. The automated unit test components include executable code for testing a backup system. The set of automated unit test components are displayed on an electronic screen. A selection of a subset of the unit test components from a user is received. An automated test case is created based on the selected subset of automated unit test components. The automated test case is stored. After the automated test case is created, the automated test case is parsed to derive a manual test case corresponding to the automated test case. The manual test case is stored.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 18, 2017
    Assignee: EMC IP Holding Company LLC
    Inventor: Shylaja Nagineni
  • Patent number: 9710349
    Abstract: A system having a plurality of application computer circuits is disclosed. A first application computer circuit is arranged to process a first application. A trace collection circuit collects trace information from the first application computer circuit. A second application computer circuit is arranged to receive and store the collected trace information in a first mode and to process a second application in a second mode.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: July 18, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Karthik R. Sankar, Gary L. Swoboda
  • Patent number: 9710340
    Abstract: A BIOS storage device including driver variable records, a corruption detection engine and a corruption remediation engine, wherein the corruption detection engine is to evaluate a plurality of driver variable records stored in an area of a BIOS storage device for corruption, and a corruption remediation engine is to replace a corrupt driver variable record with a last known good version of the driver variable record.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 18, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Jayne E. Scott
  • Patent number: 9697364
    Abstract: The present invention prevents unauthorized functions from being installed to a predetermined storage unit in the background through a communication function that is being used for authorized communication operations and further prevents confidential information from being read out and stolen from the predetermined storage unit. A semiconductor device adopts an exclusive control unit that exclusively controls communication performed by a communication unit capable of communicating with the outside and access to a predetermined storage unit. For example, the communication status of the communication unit is determined based on whether a communication clock is active or inactive, and the exclusive control is exercised based on the determination result.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: July 4, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Honzumi
  • Patent number: 9690278
    Abstract: A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective previous basic block. The branch selector node is further configured to select one of the at least one control signal based on one or more intended destinations for the at least one control signal, and provide the selected control signal to a data selector node within the current basic block. The data selector node is configured to select a data signal based on the selected control signal, where the selected data signal is from the respective previous basic block that is associated with the selected control signal.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: June 27, 2017
    Assignee: Altera Corporation
    Inventors: Doris Chen, Deshanand Singh
  • Patent number: 9678853
    Abstract: A trace of a bounded liveness failure of a system component is received, by one or more processors, along with fairness constraints and liveness assertion conditions. One or more processors generate randomized values for unassigned input values and register values, of the trace, and simulate traversal of each of a sequence of states of the trace. One or more processors determine whether traversing the sequence of states of the trace results in a repetition of a state, and responsive to determining that traversing the sequence of states of the trace does result in a repetition of a state, and the set of fairness constraints are asserted within the repetition of a state, and that the continuous liveness assertion conditions are maintained throughout the repetition of the state, a concrete counterexample of a liveness property of the system component is reported.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jason R. Baumgartner, Raj Kumar Gajavelly, Alexander Ivrii, Pradeep Kumar Nalla
  • Patent number: 9665468
    Abstract: Methods for invasive debug of a processor without processor execution of instructions are disclosed. As a part of a method, a memory mapped I/O of the processor is accessed using a debug bus and an operation is initiated that causes a debug port to gain access to registers of the processor using the memory mapped I/O. The invasive debug of the processor is executed from the debug port via registers of the processor.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 30, 2017
    Assignee: Intel Corporation
    Inventors: Karthikeyan Avudaiyappan, Brian McGee
  • Patent number: 9658909
    Abstract: An information processing apparatus includes a storage configured to store trace information relating to execution conditions of monitoring subjects, and a determination value, the determination value being a number of the monitoring subjects using a specific resource that can be used by the monitoring subjects, and a processor configured to increase the determination value by a predetermined value when one of the monitoring subjects starts to use the specific resource, reduce the determination value by the predetermined value when one of the monitoring subjects stops using the specific resource, and delete the trace information stored in the storage when the determination value indicates that none of the monitoring subjects are using the specific resource.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 23, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Takafumi Torino
  • Patent number: 9640279
    Abstract: A system-on-chip (SOC) (10) is interfaced with a memory (20) formed by a plurality of stacked memory integrated circuit dies (20a-20n). The SOC (10) includes a memory controller (100) that has a built-in self-test (BIST) system (1000) for performing the testing and repair of memory (20). BIST system (1000) includes a microcode processor (1130) that communicates externally to the SOC (10) through a Joint Test Action Group interface (120) and is coupled to a BIST state machine (1140) for executing a memory specific test sequence to detect faults in memory (20). The microcode processor (1130) further communicates with a repair state machine (1150) to execute memory specific repair procedures responsive to memory faults being detected.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: May 2, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Donovan Popps, Amjad Qureshi
  • Patent number: 9626284
    Abstract: The embodiments described herein include a host that includes an operating system and a storage simulation module in communication with the host. The storage simulation module includes a pseudo-adapter configured to emulate a storage adapter and a pseudo-storage device coupled to the pseudo-adapter, wherein the pseudo-storage device is configured to emulate a storage device. The storage simulation module is configured to simulate an error event for the pseudo-adapter and/or the pseudo-storage device upon receipt of an operation from the operating system.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: April 18, 2017
    Assignee: VMware, Inc.
    Inventors: Lan Xue, Sreevathsa Sathyanarayana, Thor Donbaek Jensen, Erik Lorimer, James Truong
  • Patent number: 9626274
    Abstract: A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Ahmad Yasin, Rajshree A. Chabukswar, Ofer Levy, Michael W. Chynoweth, Charlie J. Hewett
  • Patent number: 9618575
    Abstract: Disclosed herein is a device that includes a plurality of first terminals; a first circuit including a plurality of first nodes; a buffer circuit including a plurality of second nodes connected to the first terminals through a plurality of first interconnection lines, respectively, and a plurality of third nodes connected to the first nodes of the first circuit through a plurality of second interconnection lines, respectively; and a second circuit configured to perform at least one of first and second operations. The first operation is such that a plurality of first signals, that appear respectively on the first interconnection lines, are outputted in series, and the second operation is such that a plurality of second signals, that are supplied in series, are transferred respectively to the first interconnection lines.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 11, 2017
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Teppei Miyaji, Yoshinori Matsui
  • Patent number: 9612941
    Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include defining multiple data fabrication rules, each of the data fabrication rules including a fabrication time and a data operation. a simulation of a software application is initiated, the simulation including a sequence of simulation times, and upon detecting, during the simulation, one or more first given fabrication rules having respective fabrication times matching one or more first simulation times, fabricated data is generated in response to performing the respective data operation of each of the detected one or more first given fabrication rules. Upon detecting, during the simulation, a second given fabrication rule whose fabrication time matches a second simulation time subsequent to the one or more first simulation times, the data operation of the second given fabrication rule is performed on a subset of the fabricated data.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Akram Bitar, Oleg Blinder, Ronen Levy, Tamer Salman
  • Patent number: 9594616
    Abstract: Provided are a method for implementing counting control of a counter in a network chip, and a network chip. The method includes: periodically generating a counting value scanning message; reading a counting value of a corresponding counter item according to the generated counting value scanning message; analyzing and judging whether the read counting value is less than a preset overflow threshold; and informing the processor to handle counting abnormality of the counter when the read counting value is not less than the preset overflow threshold. The system can realize the periodic diagnosis on the counting state of the counter in the network chip by using a packet generator and a message processing engine, so as to prevent the processor from constantly sampling the counter to check the state of the counter, and ensure the calculation performance of the processor.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: March 14, 2017
    Assignee: ZTE CORPORATION
    Inventors: Haiming Jiang, Jiancheng Liu
  • Patent number: 9575122
    Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: February 21, 2017
    Assignee: Texas Intruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9570117
    Abstract: An integrated circuit includes circuitry performing memory operations. The power from only one of a first power lead and a second power lead is sufficient for the circuitry to operate. A package encasing the integrated circuit. Leads on the package electrically couple power and data from an exterior of the package to the integrated circuit encased by the package, including the first power lead, the second power lead, and a ground lead. An isolation circuit electrically couples the circuitry to the first power lead but not the second lead at a first time, and electrically couples the circuitry to the second power lead but not the first power lead at a second time.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: February 14, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hsiang-Lan Lung, Tu-Shun Chen
  • Patent number: 9569575
    Abstract: A digital circuit design method includes: before performing physical design: performing a logic synthesis according to a Register Transfer Level (RTL) design and a plurality of constraints to at least generate a netlist, a standard delay format file and a first constraint file; retrieving information of at least a specific node of circuit from the first constraint file to generate a second constraint file; generating an updated standard delay format file at least according to the standard delay format file and the second constraint file, wherein a delay of the specific node of the updated standard delay format file is less than a delay of the specific node of the standard delay format file; and using the netlist and the updated standard delay format file to perform a pre-post-layout simulation.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: February 14, 2017
    Assignee: Realtek Semiconductor Corp.
    Inventors: Shun-Te Tseng, Chi-Shun Weng
  • Patent number: 9558307
    Abstract: A system and method for providing a scalable server-implemented regression query environment for remote testing and analysis of a chip-design model receives chip-design information, including the chip-design model to be tested and one or more attributes for testing the chip design model; receives a first regression simulation test request from the client-side integration client; initiates a proxy instance for a first regression simulation test to be executed by an application programming interface (API), based on the first regression simulation test request; selects, by the API, the attributes for testing the chip-design model; executes, by the API, the first regression simulation test on the chip-design model using the selected attributes; monitors, by a server-side database manager, the first regression simulation test during execution of the first regression simulation test; and stores, by the server-side database manager, one or more results of the first regression simulation test in a database.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: January 31, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tal Yanai, Yuval Konrad
  • Patent number: 9558019
    Abstract: A system, method, computer program product, and carrier are described for obtaining a software flaw indication resulting from an emulation of a first instance of a thread at least partly in response to a first input from a user interface or indicating a virtually instantiated service via a data flow between a user interface and an operating system, the virtually instantiated service including at least a virtual instance; and accessing another instance of the virtually instantiated service at least partly in response to the user interface after indicating the virtually instantiated service via the data flow between the user interface and the operating system or manipulating a second instance of the thread at least partly in response to a second input arriving from the user interface after beginning the emulation of the first instance of the thread.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: January 31, 2017
    Assignee: Invention Science Fund I, LLC
    Inventors: Alexander J. Cohen, Edward K. Y. Jung, Royce A. Levien, Robert W. Lord, Mark A. Malamud, John D. Rinaldo, Jr., Lowell L. Wood, Jr.
  • Patent number: 9558090
    Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 31, 2017
    Assignee: Altera Corporation
    Inventors: Andrea Olgiati, Matthew Pond Baker, Steven Teig
  • Patent number: 9552279
    Abstract: A data bus network interface module for enabling reception and transmission of application messages to/from at least one host processing module of an integrated digital signal processing device via a data bus network is described. The data bus network interface module being arranged to receive at least one data bus message from at least one remote network node via the data bus network, read an identifier field of the received at least one data bus message, and make data content of the received at least one data bus message available to at least one debug module if the identifier field comprises an identifier value defined for debug use.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: January 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Mark Maiolani, Ray C. Marshall, Gary L. Miller
  • Patent number: 9547483
    Abstract: For optimizing executable code, during a first compilation of a source code, a set of signatures is inserted in a first executable code. A signature in the set of signatures includes a combination of executable instructions. During an execution of the first executable in a debugger an instruction to call a counter code is executed from a location of the signature to increment a counter corresponding to the signature. A value of the counter is provided to a compiler to correspond with the location of the signature in the first executable code. The source code is recompiled into a second executable code, optimizing a portion of the second executable code responsive to the value exceeding a threshold. The portion is related to the location of the signature in the first executable code.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: January 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan S. Boxall, Steven Cooper, Allan H. Kielstra, Trong Truong
  • Patent number: 9542303
    Abstract: Disclosed embodiments provide a system, machine-readable medium, and a method that may test computer application functions. A system provides for testing a computer application function by analyzing a testing characteristic of the computer application function information. Based on the analysis of the testing characteristic, the computer application function may be activated for testing in any one of a plurality of test environments. The test environment is selected according to the testing characteristic that indicates the effects that the testing of the selected computer application has on the test environment. This allows users to select a test environment based on the effects that it has on a test system.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 10, 2017
    Assignee: SAP SE
    Inventors: Andreas Kemmler, Torsten Kamenz
  • Patent number: 9524205
    Abstract: Techniques relate to fingerprint-based processor malfunction detection. A determination is made whether a fingerprint is present in software that is currently executing on the processor of the computer system. The fingerprint includes a representation of a sequence of behavior that occurs on the processor while the software is executing. The fingerprint corresponds to a type of malfunction. In response to determining that the fingerprint is not present in the software currently executing on the processor, monitoring of the software executing on the processor to determine whether the fingerprint is present continues. In response to determining that the fingerprint is present in the software executing on the processor, it is determined that the malfunction has occurred according to a type of the fingerprint that is present.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: December 20, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles R. Frazier, Michael Karl Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 9519025
    Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: December 13, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9507688
    Abstract: An execution history tracing method includes tracing an execution history of a CPU upon executing, in a semiconductor device including the CPU, a program by using the CPU, for one or a tracing target, from outside the semiconductor device via software. The execution history tracing method includes recording, in a buffer, target information as trace information about an execution of the one or the tracing target, for each instruction cycle in which the target information is produced as the execution history; and performing data sorting by using the software to group the trace information about the execution of the one or the tracing target, the trace information being recorded for the each instruction execution cycle, for each of the one or the tracing target.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: November 29, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Shuhei Sato, Takashi Sato
  • Patent number: 9501343
    Abstract: A method of operating a non-volatile memory device including first buffer memory cells and main memory cells, where the first buffer memory cells store first data, the main memory cells store second data, which is read from the first buffer memory cells, or recovered first data, which is recovered from the second data through a correction process, includes reading data, which is stored in sample buffer memory cells included in the first buffer memory cells, as sample data when an accumulated number of read commands, which are executed on the non-volatile memory device, reaches a reference value. The method includes counting the number of errors included in the sample data based an error correction code, and determining whether the main memory cells store the second data or the recovered first data based on the number of the errors relative to the first threshold value.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: November 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Ryun Kim
  • Patent number: 9443615
    Abstract: Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: September 13, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Jason M. Johnson, Justin Wood, Gregory S. Hendrix, Mark D. Franklin, Daniel F. Eichenberger
  • Patent number: 9424166
    Abstract: An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: August 23, 2016
    Assignee: ULTRASOC TECHNOLOGIES LIMITED
    Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
  • Patent number: 9406401
    Abstract: A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: August 2, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Yen Lo, Ding-Ming Kwai, Jin-Fu Li, Yun-Chao Yu, Che-Wei Chou
  • Patent number: 9405649
    Abstract: A debugging circuit comprises a debugging interface, a switch unit coupled to the debugging interface, a controller coupled to the switch unit, a platform controller hub (PCH), and a central processing unit (CPU). The PCH and the CPU are coupled to the switch unit. The debugging interface is coupled between the switch unit and a debugging device. The switch unit receives a control signal from the controller, and selectively outputs a first data signal from the PCH or a second data signal from the CPU to the debugging device through the debugging interface according to the control signal.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: August 2, 2016
    Assignees: HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wu Zhou, Meng-Liang Yang
  • Patent number: 9405604
    Abstract: An integrated circuit (IC) having a debug access port coupled to a processing circuit without a dedicated sideband interface is disclosed. In one embodiment, an IC includes a processor circuit and a DAP. The IC also includes a communications fabric over which communications transactions may be conveyed between the various functional circuits of the IC using a fabric protocol. Both the DAP and the processing circuit are coupled to the communications fabric. The IC also includes a translation circuit coupled between the processing circuit and the communications fabric. The translation circuit may translate transactions conveyed between the processing circuit and the DAP from or to a debug protocol to or from the fabric protocol. Thus, the DAP and the processing circuit may communicate according to the debug protocol without a dedicated sideband coupled therebetween.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: August 2, 2016
    Assignee: Apple Inc.
    Inventor: Nitin Bhargava
  • Patent number: 9401223
    Abstract: A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: July 26, 2016
    Assignee: Oracle International Corporation
    Inventors: Thomas A Ziaja, Murali M. R. Gala
  • Patent number: 9383410
    Abstract: The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: July 5, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9384312
    Abstract: A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.
    Type: Grant
    Filed: May 25, 2013
    Date of Patent: July 5, 2016
    Assignee: Altera Corporation
    Inventors: Kalen B. Brunham, Gordon Raymond Chiu, Joshua David Fender
  • Patent number: 9360522
    Abstract: Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates from an expected signal. Fault detection circuits may also be configured to identify instances where two or more or N or more signals deviate from an expected signal. Mechanisms may also be provided to assure the reliability of fault detection circuitry itself.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: June 7, 2016
    Assignee: Altera Corporation
    Inventor: Bruce B. Pedersen
  • Patent number: 9352747
    Abstract: A vehicle travel control system includes a first unit configured to calculate a target longitudinal acceleration/deceleration control command of the own vehicle based on a distance or a relative speed between the own vehicle and a forward obstacle, traveling route information from a vehicle navigation system or a Global Positioning System, and input information such as a vehicle speed set by a driver; a second unit configured to calculate a target longitudinal acceleration/deceleration control command according to a lateral jerk that acts on the own vehicle; and an arbitration unit configured to perform, based on the target longitudinal acceleration/deceleration control command calculated by the second unit, arbitration of the target longitudinal acceleration/deceleration control command calculated by the first unit, wherein output from the arbitration unit is set as a command to control the target longitudinal acceleration/deceleration control command of the own vehicle.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: May 31, 2016
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Keiichiro Nagatsuka, Makoto Yamakado, Mitsuhide Sasaki, Mikio Ueyama
  • Patent number: 9316690
    Abstract: An Automated Test Equipment (ATE) system is configured to test a Device Under Test (DUT). The ATE system stores a Procedure Description Language program. The ATE system interprets the program, thereby causing a configured scan path to be set up in the DUT and causing bit values to be loaded into that scan path. During testing, it is sometimes desirable to change only bit values in certain scan path bit locations. In a data recirculation operation, the ATE system shifts bit values, on a bit-by-bit basis, out of the configured scan path via the TDO terminal of the DUT and shifts back in either the shifted out bit value or a replacement bit value. The shift back into the configured scan path occurs via the TDI terminal of the DUT so that each bit value in the scan path is replaced with its previous value or a replacement value.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: April 19, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Songlin Zuo, Michael Laisne