Built-in Hardware For Diagnosing Or Testing Within-system Component (e.g., Microprocessor Test Mode Circuit, Scan Path) Patents (Class 714/30)
  • Patent number: 8683266
    Abstract: The object of the invention is in particular the validation of configuration of a system comprising a plurality of elements, at least one reference being associated with each element of the said plurality of elements. After at least one reference key has been calculated (410) according to at least one expected reference of each element of the said plurality of elements, a theoretical configuration report of the said system, comprising the said at least one reference key, is generated (420). Similarly, at least one verification key is calculated (455) according to at least one reference of each element of the said plurality of elements, and a real configuration report of the said system, comprising the said at least one verification key, is generated (460). A configuration error is detected if the values of the said verification key and reference key of the said real and theoretical configuration reports are different.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: March 25, 2014
    Assignee: AIRBUS Operations S.A.S.
    Inventors: Raphael Migliasso, Olivier Bastien, Miguel Estrada-Fernandez
  • Patent number: 8683280
    Abstract: Aspects of the invention relate to low power BIST-based testing. A low power test generator may comprise a pseudo-random pattern generator unit, a toggle control unit configured to generate toggle control data based on bit sequence data generated by the pseudo-random pattern generator unit, and a hold register unit configured to generate low power test pattern data by replacing, based on the toggle control data received from the toggle control unit, data from some or all of outputs of the pseudo-random pattern generator unit with constant values during various time periods. The low power test generator may further comprise a phase shifter configured to combine bits of the low power test pattern data for driving scan chains.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: March 25, 2014
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie
  • Patent number: 8677306
    Abstract: A network-fabric used for testing with an external or internal tester is shown for a Structured ASIC. In one embodiment, the Structured ASIC uses a microprocessor, network-aware IO routing fabric comprising network agents in a scalable novel configuration, with the network-aware IO having a plurality of blocks connected in series in a plurality of paths in the fabric leading to and from the microprocessor and memory and/or logic, the blocks acting as intelligent network agents under processor control to determine what state they can assume, whether to pass a data signal or not along these paths, comprising open loops and closed loops running to and from the microprocessor and memory and/or logic, primarily for testing and determining the state of the memory and logic. In another embodiment a JTAG controller may receive JTAG test commands from an external testing apparatus and set up to communicate along the fabric.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 18, 2014
    Assignee: EASIC Corporation
    Inventors: Alexander Andreev, Andrey Nikitin, Marian Serbian, Massimo Verita
  • Patent number: 8677095
    Abstract: An apparatus and method to allocate memory in a storage system. Firmware running the method uses an iterative approach to find the best optimal memory configuration for a particular storage system given a variety of configuration data parameters stored as persistent data in non-volatile flash memory. The configuration data relates to resources in the environment that the storage system is found in, such as the number of virtual ports, targets and initiators supported by a storage system IOC. The configuration data is alterable, to allow flexibility in updating and changing parameters, and is employed at runtime when the storage system powers on, to enable the most flexible resource allocation.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: March 18, 2014
    Assignee: LSI Corporation
    Inventors: Roger T. J Clegg, Brad D. Besmer, Guy Kendall
  • Publication number: 20140068332
    Abstract: An electronic device which has a self diagnosis function and a self diagnosis method using the same are provided. The electronic device includes: an interface which receives a user's selection signal for a hardware of an object to be diagnosed; and a controller which provides a plurality of lines connected to the hardware of the object to be diagnosed with a signal for diagnosis according to the selection signal which is received through the interface and calculates a diagnosis result for the hardware of diagnosis object according to a comparison result of the signal for diagnosis with a return signal which is returned from the hardware of the object to be diagnosed by a loop-back.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 6, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-hun CHOI, Hyun-ho KIM, Sang-eun LEE, Ju-hyun CHOE, Eun-young KIM, Ji-won KIM
  • Publication number: 20140068333
    Abstract: A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implemented using a few terminals of the ASIC.
    Type: Application
    Filed: October 21, 2013
    Publication date: March 6, 2014
    Applicant: Marvell International Technology LTD
    Inventors: Richard D. Taylor, Mark D. Montierth, Melvin D. Bodily, Gary Zimmerman, John D. Marshall
  • Publication number: 20140053023
    Abstract: A method is shown to provide remote access to one or more debug access points whose functions include capabilities other than accessing memories across an application interface such as USB, IEEE 802.3 (Ethernet) and other protocols. The capabilities available include all or many of the capabilities provided by a dedicated debug interface.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 20, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Gary L. Swoboda, Jason L. Peck
  • Patent number: 8655637
    Abstract: An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: February 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jose L. Flores, Lewis Nardini, Maria B. H. Gill
  • Patent number: 8656236
    Abstract: Techniques related to remotely boundary scanning of an integrated circuit embedded in a target computing system are disclosed herein. In an example, a host computing system includes a first peripheral port and a second peripheral port. A port-to-port boundary scan assembly is to interface boundary scan data between the first and the second peripheral ports. Thereby the boundary scan data can be routed from the second peripheral bus to the target computing system via a network port at the host computing system.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: February 18, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kamran H Casim, Russ W Herrell, Martin Goldstein
  • Patent number: 8656220
    Abstract: A system-on-chip (SoC) includes a core, a plurality of power domain blocks, and a power control circuit including a debug circuit. The power control circuit is configured to control power supplied to the core and each of the power domain blocks, and the debug circuit is configured to debug the power control circuit.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegon Lee, Hyunsun Ahn
  • Patent number: 8650519
    Abstract: A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, using feedback from the event monitors the test generator patterns may be manipulated to preferentially generate patterns that may exercise signal paths that are being monitored in subsequent simulations.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: February 11, 2014
    Assignee: Apple Inc.
    Inventor: Fritz A. Boehm
  • Patent number: 8645759
    Abstract: A debugging mechanism receives arithmetic operation data inputs for causing an arithmetic unit to perform an arithmetic operation, and a control signal used for the arithmetic operation. The debugging mechanism includes a debug control unit which includes (1) a counter that performs a counting operation cyclically according to the processor clock operation, and (2) an OR circuit that receives the control signal and a counter signal that is output when the counter value becomes a specific value, and outputs an output signal generated by performing a logical OR operation of the control signal and the counter signal. The debugging mechanism also includes a debug storage unit which stores the arithmetic operation data, the counter value, and the control signal when the output of the OR circuit is valid.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: February 4, 2014
    Assignee: Fujitsu Limited
    Inventors: Yoshiteru Ohnuki, Hideo Yamashita
  • Patent number: 8645588
    Abstract: The present invention provides embodiments of an apparatus used to implement a pipelined serial ring bus. One embodiment of the apparatus includes one or more ring buses configured to communicatively couple registers associated with logical elements in a processor. The ring bus(s) are configured to concurrently convey information associated with a plurality of load or store operations.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: February 4, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher D. Bryant, David Kaplan
  • Patent number: 8645022
    Abstract: A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: February 4, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Kentaro Yoshimura, Kohei Sakurai, Nobuyasu Kanekawa, Yuichiro Morita, Yoshiaki Takahashi, Kenichi Kurosawa, Toshimichi Minowa, Masatoshi Hoshino, Yasuhiro Nakatsuka, Kotaro Shimamura, Kunihiko Tsunedomi, Shoji Sasaki
  • Patent number: 8645753
    Abstract: The present disclosure discloses a power system with hot-swap with a buck converter. The power system comprises a front stage, a hot-swap stage and a load stage; wherein the hot-swap stage comprises: a buck converter having a switch operate at ON/OFF state to provide a desired output voltage to the load stage with low power loss and optimized thermal design.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 4, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Eric Yang, ZhengXing Li, Yuancheng Ren
  • Patent number: 8645779
    Abstract: A method for scan testing an integrated circuit that includes a plurality of on-chip logic modules includes configuring the integrated circuit for module level scan testing and chip level scan testing by way of an external automatic test pattern generator (ATPG) tool. The ATPG tool generates first and second sets of test patterns for module level and chip level scan testing of the integrated circuit. The ATPG tool generates the second set of test patterns by excluding the design faults which have already been targeted during the module level scan testing, from the first set of test patterns and reduces the overall time required for scan testing the integrated circuit.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rajan Aggarwal, Ashutosh Anand, Ankit Bhargava, Mishika Singla, Prashant K. Sonone
  • Publication number: 20140032965
    Abstract: A monitoring device includes a detection unit which is inserted between the device to be monitored and a processing apparatus performing processing for the device to be monitored and detects a failure which occurs in the device to be monitored, a notification unit generating failure information indicating a content of the failure detected by the detection unit and notifying the generated failure information and the occurrence of the failure to the processing apparatus, and an acquisition unit acquiring status information after the occurrence of the failure of the device to be monitored from the device to be monitored and storing the acquired status information in a storage unit as the failure occurs.
    Type: Application
    Filed: May 26, 2013
    Publication date: January 30, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Nina Tsukamoto, Shinnosuke Matsuda
  • Patent number: 8640007
    Abstract: A test system including a storage device and a protocol analyzer coupled to the storage device. The storage device can include a diagnostic data transmission unit configured to transmit diagnostic data related to an operation of the storage device, and a host interface unit including a first selector configured to receive idle characters and the diagnostic data, wherein the first selector selectively transmits the idle characters or the diagnostic data. The protocol analyzer can be configured to autonomously receive the idle characters or the diagnostic data via the host interface unit.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: January 28, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Martin E. Schulze
  • Patent number: 8639981
    Abstract: A system and method of various SoC design verification techniques. A model of an SoC design is simulated in an emulator, and the emulator is connected to a debugger. Scripts are conveyed from a host computer to the debugger. The debugger translates the commands in the scripts from a first language into commands in a second language. The debugger then conveys the commands in the second language to the emulator. The debugger is also configured to utilize the same scripts to perform tests on an actual SoC on a development board.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: January 28, 2014
    Assignee: Apple Inc.
    Inventor: Andrew K. Chong
  • Patent number: 8635497
    Abstract: A system includes one or more processors; one or more trace debug circuits configured to monitor one or more of instruction, data, and watchpoint buses of the one or more processors, and record information determined from said monitoring; and a sequence processing unit configured to provide a control signal to a trace debug circuit of the one or more trace debug circuits, wherein in response to the control signal, the trace debug circuit controls one or more of said monitoring and recording, and a system on a chip comprises the one or more processors, the one or more trace debug circuits, and the sequence processing unit.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: January 21, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gary L. Miller, Mark Maiolani, William C. Moyer
  • Patent number: 8629680
    Abstract: A central processing unit (CPU) test system includes a CPU socket, a CPU core controller, and a CPU test device. The CPU core controller stores a start voltage message. The CPU test device includes a voltage detection pin, an analog to digital (A/D) converter, and a microcontroller. The voltage detection pin detects a voltage of an electronic device connected to the CPU socket. The A/D converter converts the detected voltage into a digital signal. The microcontroller controls the CPU core controller to output the start voltage to the CPU socket according to the digital signal. The microcontroller stores a predetermined start voltage message. The microcontroller reads the start voltage message after controlling the CPU core controller to output the start voltage, and determines whether the CPU core controller supplies the start voltage to the CPU socket by comparing the read start voltage message with the predetermined start voltage message.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: January 14, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd, Hon Hai Precision Industry Co., Ltd.
    Inventors: Ying-Bin Fu, Ting Ge, Ya-Jun Pan
  • Patent number: 8630187
    Abstract: A system for testing a network switching apparatus includes one or more port connections external to the network switching apparatus. The one or more port connections are configured to interconnect selected ports of the network switching apparatus to transfer packets between the selected ports. Further, the system includes a test manager configured to automatically generate a plurality of test scenarios for testing a processing operation to be performed by the network switching apparatus on packets. The test scenarios define paths for forwarding packets multiple times among the ports of the network switching apparatus. The system also includes a packet generator configured to transmit packets to at least a first port of the network switching apparatus to test a processing operation performed by the network switching apparatus.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: January 14, 2014
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Gustavo Rodberg, Alexay Groisman, Izik Ovadia-Goldberg, Felix Kaufman, Raviv Shasha
  • Publication number: 20140013158
    Abstract: The technology disclosed relates to real-time collection and flexible reporting of test data. In particular, it is useful when collecting packet counts during tests of network devices that simulate thousands or even millions of data sessions conducted through a device under test (“DUT”).
    Type: Application
    Filed: September 9, 2013
    Publication date: January 9, 2014
    Applicant: Spirent Communications, Inc.
    Inventors: BRIAN SILVERMAN, TOM MCBEATH, ABHITESH KASTUAR, SERGEY RATHON
  • Publication number: 20140013156
    Abstract: A method of managing an image forming apparatus through a network, the method including: logging in to a server through a diagnostic control unit application from a user terminal; receiving, by the user terminal, device information of an image forming apparatus from the image forming apparatus; requesting for and receiving, by the user terminal, diagnostic control unit information corresponding to the received device information from the server; performing a diagnostic control on the image forming apparatus through the diagnostic control unit application by using the received diagnostic control unit information; and uploading results of performing the diagnostic control on the server.
    Type: Application
    Filed: July 5, 2013
    Publication date: January 9, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seung-jin CHO
  • Publication number: 20140013157
    Abstract: Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information.
    Type: Application
    Filed: July 9, 2013
    Publication date: January 9, 2014
    Inventor: Andrew Brian Thomas Hopkins
  • Patent number: 8627145
    Abstract: This invention is an apparatus and method for monitoring an electronic apparatus. At least one capture unit captures data to be monitored. A repeater corresponding to each capture unit repeats the captured data. A first-in-first-out buffer corresponding to each capture unit temporarily stores the captured data. The buffered data supplies a utilization unit. Captured data may be merged after repeating. The capture unit may be in a different voltage domain than the repeater, buffer and utilization unit.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: January 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Publication number: 20140006863
    Abstract: A semiconductor memory apparatus includes a test circuit configured to receive a plurality of sequentially-changing test input patterns, compress the received test input patterns at each clock signal, and output the compressed patterns as variable test data.
    Type: Application
    Filed: December 10, 2012
    Publication date: January 2, 2014
    Applicant: SK Hynix Inc.
    Inventors: Hyung Gyun YANG, Hyung Dong LEE, Yong Kee KWON, Young Suk MOON
  • Patent number: 8621295
    Abstract: A circuit module includes a shift register constituting part of a scan chain within a semiconductor integrated circuit, a control unit for controlling an operation of the shift register using a control signal generated within the semiconductor integrated circuit and a selection unit for selecting between a short-circuit path through which a scan signal is loaded and an ordinary path through which the scan signal is loaded after being made to go through the shift register, where the ordinary path is selected when the operation of the shift register is permitted by the control signal and the short-circuit path is selected when the operation of the shift register is not permitted.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: December 31, 2013
    Assignee: Fujitsu Limited
    Inventor: Yutaka Tamiya
  • Patent number: 8619599
    Abstract: Methods and systems for implementing self-testing of packet processing devices are disclosed. For example, a packet-processing device can include a plurality of ports having a receive media access controller (RX MAC) and a transmit media access controller (TX MAC). The TX MAC of a first port is selectably configurable to loop back packets to its respective RX MAC during the self-testing. The packet-processing device can further include a switching engine configured to provide a test packet received from a packet generator to the TX MAC of the first port, and route to the TX MAC of one or more second ports at least the test packet received from the RX MAC of the first port, or a copy of the received test packet, after the received test packet or its copy has been looped-back one or more times between the TX MAC and the RX MAC of the first port.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: December 31, 2013
    Assignee: Marvell International Ltd.
    Inventor: Vladimir Even
  • Patent number: 8620511
    Abstract: A diagnostic platform adapted for coupling to a scanner to download data from vehicle computers. The system stores information regarding vehicle identifications, drivability symptoms, vehicle system and component tests and service codes which can be registered by the vehicle on-board computer. System software permits user input of vehicle identification and, in one mode, displays a fault library from which the user can select, whereupon the system selects from the library tests pertinent to diagnosing causes of selected faults and displays them in a hierarchically ranked order based on likelihood of success. The user can then initiate any displayed test. In other modes, the system initially displays one of the libraries of system or component tests, from which the user selects, whereupon the system highlights icons which can be selected for initiating pertinent test procedures. Selected test procedures include links to engine analyzer or scanner hardware or other appropriate test modules.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: December 31, 2013
    Assignee: Snap-On Incorporated
    Inventor: Paul J. Rother
  • Publication number: 20130346800
    Abstract: In one embodiment, an SOC includes multiple components including a CPU complex and one or more non-CPU components such as peripheral interface controllers, memory controllers, media components, etc. The SOC also includes an SOC debug control unit, which is coupled to receive detected debug events from the components. Each component may include a local debug control unit that is configured to monitor for various debug events within that component. The debug events may be specific to the component. The local debug control units may transmit detected events to the SOC debug control unit. The SOC debug control unit may detect one or more events from one or more components, and may halt the components of the SOC responsive to detecting the selected events.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Inventors: Manu Gulati, James D. Ramsay, Erik P. Machnicki, Jianlin Yu
  • Publication number: 20130339790
    Abstract: A system and method for a common unified debug architecture for integrated circuits and System on Chips (SoCs) are provided. A system consistent with the present disclosure may comprise of an integrated circuit or SoC which includes a display port, plurality of logic blocks, and debug logic. The debug logic may receive debug data from one or more of the plurality of logic blocks in response to the integrated circuit or SoC operating in a debug mode. In addition, control logic coupled to the debug logic. The control logic provides display data to the display port in response to the integrated circuit operating in an operational mode. The control logic further directs high-speed debug data to the display port in response to the integrated circuit or SoC operating in the debug mode. The high-speed debug data is to be based on the debug data.
    Type: Application
    Filed: March 15, 2013
    Publication date: December 19, 2013
    Inventors: Sankaran M. Menon, Rajendra S. Yavatkar, Eyal Dolev, Sridhar Valluru, Ramana Rachakonda
  • Patent number: 8612813
    Abstract: A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Valerie H. Chickanosky, Kevin W. Gorman, Suzanne Granato, Michael R. Ouellette
  • Patent number: 8607088
    Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: December 10, 2013
    Assignee: Texas Intruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 8601145
    Abstract: Manageability ports for inter-processor communication links, along with associated systems and methods, are generally provided.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: December 3, 2013
    Assignee: Marvell International Ltd.
    Inventor: Peter D. Mueller
  • Patent number: 8595389
    Abstract: A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kristan D. Davis, Kahn C. Evans, Alan Gara, David L. Satterfield
  • Patent number: 8595555
    Abstract: A method of debugging an integrated circuit (IC) can include receiving, within a debugging system implemented within the IC, a debug command from a system external to the IC and, responsive to the debug command, initiating a debug function specified by the debug command for a processor system embedded on the IC. An IC also is provided that can include a programmable circuitry (e.g., a programmable fabric) coupled via an interface to processor system embedded in the IC. A debugging system can be implemented within the programmable fabric to communicate with the processor system via the interface.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: November 26, 2013
    Assignee: Xilinx, Inc.
    Inventor: Bradley L. Taylor
  • Patent number: 8595554
    Abstract: Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Bellofatto, Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Philip Heidelberger, Gerard V. Kopcsay, Thomas A. Liebsch, Martin Ohmacht, Don D. Reed, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • Patent number: 8589746
    Abstract: A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: November 19, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Publication number: 20130297974
    Abstract: A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module, a system clock module for providing internal clock signals, and a reset detection unit which during a debug mode prevents the system clock module from receiving a reset signal.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 7, 2013
    Applicant: Microchip Technology Incorporated
    Inventors: Justin Milks, Thomas Edward Perme, Sundar Balasubramanian, Kushala Javagal
  • Publication number: 20130290785
    Abstract: In some examples, a computer system includes a first component associated with a first power domain and a second component associated with a second power domain. The computer system also includes a debug port with a debug port pin shared by a debug operation pin of the first component and a corresponding debug operation pin of the second component. The computer system also includes a switch associated with the debug port pin to selectively isolate the debug operation pin of the first component from leakage current of the corresponding debug operation pin of the second component.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Inventors: Huong M. TRUONG, Jason W. WHITEMAN, Prill J. PATEL
  • Patent number: 8572449
    Abstract: An on-chip testing unit can be implemented in an integrated circuit (e.g., a SoC) to validate the operation of cache memories associated with a processor of the integrated circuit. For each testing instruction to be executed by the processor for testing a cache memory, the testing unit can intercept information (e.g., address, data, and/or control signals) generated by the processor in response to executing the instruction. The testing unit can determine whether information generated by the processor matches corresponding expected information associated with the instruction. This can enable the testing unit to determine whether the processor can correctly identify an address from which the next instruction is to be fetched, can ensure consistency between data in the cache memories and persistent storage devices, and whether the processor is operating as expected. An error notification can be generated if the information generated by the processor does not match the expected information.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: October 29, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Sivakumar Ardhanari, Vardhamana G Hegde, Madhanagopalan Sambath Kumar, Balakuteswar V Voleti
  • Patent number: 8572448
    Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: October 29, 2013
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Hong Ho, Daniel Smathers
  • Patent number: 8566484
    Abstract: A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: David L. Satterfield, James C. Sexton
  • Patent number: 8560891
    Abstract: A computer implemented method of embedded dynamic random access memory (EDRAM) macro disablement. The method includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows. Each line of the EDRAM macro is iteratively tested, the testing including attempting at least one write operation at each line of the EDRAM macro. It is determined that an error occurred during the testing. Write perations for an entire row of EDRAM macros associated with the EDRAM macro are disabled based on the determining.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh, Pak-kin Mak
  • Patent number: 8560904
    Abstract: Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. A method for identifying a reference scan cell is provided, the method including, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The method further includes, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: October 15, 2013
    Assignee: Teseda Corporation
    Inventors: Rich Ackerman, John Raykowski
  • Patent number: 8554953
    Abstract: The Advanced Logic System (ALS) is a complete control system architecture, based on a hardware platform rather than a software-based microprocessor system. It is significantly different from other PLC-type control system architectures, by implementing a FPGA in the central control unit. Standard FPGA logic circuits are used rather than a software-based microprocessor which eliminate problems with software based microprocessor systems, such as software common-mode failures. It provides a highly reliable system suitable for safety critical control systems, including nuclear plant protection systems. The system samples process inputs, provides for digital bus communications, applies a control logic function, and provides for controlled outputs. The architecture incorporates advanced features such as diagnostics, testability, and redundancy on multiple levels. It additionally provides significant improvements in failure detection, isolation, and mitigation for the highest level of integrity and reliability.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: October 8, 2013
    Assignee: Westinghouse Electric Company LLC
    Inventors: Steen Ditlev Sorensen, Sten Sogaard
  • Patent number: 8549368
    Abstract: A multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. The first and second sets of processor cores include first and second memory blocks and corresponding first and second built-in-self-testing (BIST) engines of different architectures. A control circuit configures the first and second TAP controllers and the connection between the first and second sets of processor cores and the first and second debug ports, for initiating the first and second BIST engines for testing the memory blocks using a predetermined test mode. A debug access module provides secure access to the first and second debug ports.
    Type: Grant
    Filed: May 19, 2012
    Date of Patent: October 1, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amar Nath Deogharia, Ankush Srivastava
  • Patent number: 8543950
    Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: September 24, 2013
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L.-T.) Wang, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horng Lin, Hsin-Po Wang
  • Patent number: 8543863
    Abstract: Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: September 24, 2013
    Assignee: Microsoft Corporation
    Inventors: Engin Ipek, Thomas Moscibroda, Douglas C. Burger, Edmund B. Nightingale, Jeremy P. Condit