Abstract: A computer-on-Module debug card assembly and a control system thereof comprising: a carrier module with a carrier board and electronic components thereon wherein the carrier board is provided with a plurality of I/O connectors and at least a bus; a debug module electrically connected to the carrier board and comprising a debug card and electronic components thereon wherein the debug card is equipped with a detecting component, at least a bus, and a plurality of switch buttons used to check switching; a COM express system electrically connected to the debug card and comprising a COM express board and electronic components thereon wherein the COM express board is provided with modular components and at least a bus. As such, it is able to identify messages for a CPU-bearing COM express board and a carrier board in the COM express system during debugging, streamlining the procedure and saving time.

Abstract: A redundant two-processor controller having a first processor (1) and a second processor (1) for the synchronous execution of a control program. The controller having at least a first multiplexer (70, 91) for optionally connecting at least a first peripheral unit (72, 95) to be actuated to one of the two processors (1, 2), and at least a first Comparison unit (70, 91) for monitoring the synchronization state of the two processors (1, 2) and for detecting a synchronization error. A restoration control unit (44) is designed to monitor the execution of at least one test program by the two processors (1, 2) after the occurrence of a synchronization error and to evaluate the test results, and which is designed to configure at least the first multiplexer (70, 91).

Abstract: A computer protection system comprises a mobile detection module adapted to detect at least one event indicating a likelihood of movement of a computer and, in response to detecting the at least one event, automatically place a drive device of the computer in a suspend state.

Abstract: A file protecting method and system and a memory controller and a memory storage apparatus using the same are provided. The file protecting method includes performing a file protection enabling procedure for a file to generate an entry value backup according to at least one entry value corresponding to at least one cluster storing the file, which is recorded in a file allocation document, store the entry value backup in a secure storage area and change the entry value corresponding to the cluster storing the file in the file allocation document, wherein the file cannot be read according to the changed entry value. Accordingly, the file stored in the memory storage apparatus the can be effectively protected from being accessed by an un-authorized person.

Abstract: A programmable characterization-debug-test engine (PCDTE) on an integrated circuit chip. The PCDTE includes an instruction memory that receives and stores instructions provided on a chip interface, and a configuration memory that receives and stores configuration values provided on the chip interface. The PCDTE also includes a controller that configures a plurality of address counters and data registers in response to the configuration values. The controller also executes the instructions, wherein read/write addresses and write data are retrieved from the counters in response to the instructions. The retrieved read/write addresses and write data are used to access a memory under test. Multiple ports of the memory under test may be simultaneously accessed. Multiple instructions may be linked. The instructions may specify special counting functions within the counters and/or specify integrated (linked) counters.

Abstract: An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.

Abstract: An integrated circuit may be provided with system-on-chip circuitry including system-on-chip interconnects and a microprocessor unit subsystem. The subsystem may include microprocessor cores that execute instructions stored in memory. Cache may be used to cache data for the microprocessor cores. A memory coherency control unit may be used to maintain memory coherency during operation of the microprocessor unit subsystem. The memory coherency control unit may be coupled to the system-on-chip interconnects by a bus. A command translator may be interposed in the bus. The command translator may have a slave interface that communicates with the interconnects and a master interface that communicates with the memory coherency control unit. The integrated circuit may have programmable circuitry that is programmed to implement a debug master coupled to the interconnects. During debug operations, the command translator may translate commands from the debug master.

Abstract: A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. The bus is monitored for discarded speculative read and for merged write transactions in order to determine the true bus throughputs. Bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.

Abstract: A debugging circuit comprises a debugging interface, a switch unit coupled to the debugging interface, a controller coupled to the switch unit, a platform controller hub (PCH), and a central processing unit (CPU). The PCH and the CPU are coupled to the switch unit. The debugging interface is coupled between the switch unit and a debugging device. The switch unit receives a control signal from the controller, and selectively outputs a first data signal from the PCH or a second data signal from the CPU to the debugging device through the debugging interface according to the control signal.

Abstract: A serial attached Small Computer System Interface (SAS) expander comprises a SAS expander chip which comprises a first debug port and a second debug port, a controlling chip which is in communication with the first debug port through a first serial port, in communication with the second debug port through a second serial port, and in communication with a host computer through a third serial port, once the controlling chip controls the third serial port to receive a debug command from the host computer, the controlling chip sends the received debug command to the first debug port or the second debug port according to a reference table.

Abstract: Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.

Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.

Abstract: A virtual disk carousel is provided that is capable of creating disk images from optical disks and storing the disk images. The virtual disk carousel includes a bridge device configured to expose disk images stored at the virtual disk carousel to a computer by way of a standard storage device. When the computer performs read requests on the standard storage device exposed by the bridge device, the bridge device receives the requests from the computer, retrieves the appropriate portion of the disk image from the virtual disk carousel, and provides the portion of the disk image to the computer. The bridge device might also include a display and user input controls for managing the operation of the bridge device. The virtual disk carousel might also provide a user interface for managing the disk images, selecting a disk image to be exposed to the computer, and for performing other functions.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.

Abstract: An integrated circuit comprises scan test circuitry and at least one circuit core coupled to the scan test circuitry. The scan test circuitry comprises input and output scan chains coupled to respective input and output interfaces of the circuit core via respective functional logic blocks, and interface signal selection circuitry. The interface signal selection circuitry is configured to select a particular one of a functional input signal and a plurality of scan test input signals for application to one or more designated input signal lines of the input interface of the circuit core responsive to one or more control signals. By way of example only, the first and second scan test input signals may comprise respective first and second distinct address values and the designated input signal lines of the input interface of the circuit core may comprise address input signal lines of an embedded memory.

Abstract: A rack server includes multiple power supply backplanes and multiple Fan Controller Boards (FCBs). The power supply backplanes each have a connection unit. The connection unit has multiple connection terminals. One of the connection terminals is coupled to a ground terminal. Positions of the connection terminals of the connection units coupled to the ground terminal are different from each other. The FCBs are coupled to one of the corresponding power supply backplanes respectively. The FCBs each include an addressing circuit and a microcontroller. The addressing circuit is coupled to the connection terminals of the corresponding connection unit, and is used to generate an address signal by detecting and according to a coupling relationship between the connection terminals and the ground terminal. The microcontroller is coupled to the addressing circuit, and is used to receive the address signal, so as to generate corresponding address information.

Abstract: The present invention enables a safety management of safety measures as well as the non-destructive testing of safety-relevant registers which are required for the configuration of a system, wherein the test method according to the invention can be carried out during each operating phase of a system to be tested.

Abstract: A serial testing infrastructure includes the capability to execute a distributed test on multiple virtual processors. A test executable may be stored in a library and the test description, including the name of the test, the test library, and other test characteristics, may be stored in a separate test data file. The serial testing infrastructure initiates multiple distributed test executors that each launch an instance of the distributed test as a process that runs concurrently with other instances of the distributed test. Each distributed test executor monitors execution of it corresponding process until completion or timeout.

Abstract: Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting results of a self-test of pre-programmed data executed responsive to receiving the self-test command, and issuing a self-repair command responsive to the results indicating repair of the pre-programmed data is needed.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises at least one clock module comprising one or more clock dividers and associated clock divider logic, and the scan test circuitry is configured to permit testing of at least a portion of the clock divider logic. A given scan chain of the scan test circuitry may comprise first and second scan cells, with the first scan cell having a scan output coupled to a scan input of the second scan cell, and the second scan cell having a data input driven by an output of the clock divider logic.

Abstract: Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

Abstract: A debugging control system using inside-core events as trigger conditions and a method of the same are revealed. The method includes following steps. First set up at least one trigger condition and a search range of the clock cycle according to internal states of a core under debug. Pause clock and recover clock of each clock cycle within the search range. Retrieve data of scan chains of the core under debug by a shift buffer during the clock pausing. Next combine data of the scan chains by a trigger comparator circuit to form trigger signals and check whether the trigger signals satisfy the trigger condition. If the trigger condition is satisfied or the trigger signal is over the search range, the clock is paused continuingly and internal states of the scan chains of the core under debug are output otherwise the core under debug is recovered.

Abstract: A debugging device for performing a debugging process through an electronic device external connector system is provided. The debugging device performs the debugging process to a target system, and the device comprises a first external connector, a switch, and a debugging module. The first external connector is connected to the external port of the target system. The switch is connected to the first external connector, and the switch chooses to activate the debugging process. The debugging module is connected to the switch, and the debugging module receives a universal asynchronous receiver/transmitter (UART) signal provided by the target system.

Abstract: The present invention relates to the field of processing within hardware security modules, such as for example debugging of compiled programs. A debugging module includes a microprocessor and a compiled program to be executed by the microprocessor in order to carry out an operation, and is configured to exchange with an external entity, in a master/slave mode, messages relating to the operation. The compiled program includes at least one debugging instruction which whether or not it is executed does not modify the execution of the operation. The hardware security module is moreover configured to transmit, during the execution of the compiled program, data generated, for example by the debugging instruction, over a communication channel initiated by the hardware security module, to an entity external to the hardware security module.

Abstract: Systems and method for embedded trace macrocell (ETM) devices configured to dynamically interleave architecture/program tracing with microarchitecture/hardware tracing. An ETM device includes logic to enable interleaved program tracing and hardware state sampling. A core interface is configured to receive program trace and hardware state information of a microprocessor and a combining module is configured to interleave the program trace and hardware state information. A packet generation module may be configured to packetize the program trace and hardware state information into packets at operational speeds of the microprocessor.

Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors, including if the die has a defective component. An indication of the defective functional component identification is received. A determination is made if the defective functional component is one of a plurality of similar functional components that can provide the same functionality. The other similar components can be examined to determine if they are parallel components to the defective functional component. The defective functional component is disabled if it is one of the plurality of similar functional components and another component can handle the workflow that would otherwise be assigned to the defective component. Workflow is diverted from the disabled component to other similar functional components.

Abstract: A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Abstract: A semiconductor device and a test apparatus including the same, the semiconductor device including a command distributor receiving a serial command that is synchronized with a first clock signal and converting the serial command into a parallel command, a command decoder receiving the parallel command and generating a pattern sequence based on the parallel command, and a signal generator receiving the pattern sequence and generating operating signals synchronized with a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.

Abstract: A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Abstract: A system can include a processing core to execute machine readable instructions. The system can also include a memory accessible by the processor core. The memory can include preprogrammed test data that characterizes one of an impedance of a processor and a current output to the processor during execution of a test routine. The processor can include the processing core and the one of the impedance of the processor and the current output to the processor is based on a power measurement taken during execution of a test routine. The power measurement can be taken with a current sensor that is at least one of lossy or at least about 98% accurate.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.

Abstract: A method for detecting unstable signatures when testing a VLSI chip that includes adding to an LFSR one or more save and restore registers for storing an initial seed consisting of 0s and 1s; loading the initial seed into the LFSR and one or more save and restore registers; initializing a MISR and running test loops. Upon reaching a predetermined number of test loops, moving a signature of the MISR to a shadow register; then, performing a signature stability test by loading the initial seed to the LFSR; executing the predetermined number of BIST test loops, and comparing a resulting MISR signature for differences versus a previous signature stored in a MISR save and restore register, wherein unloading is performed by way of serial MISR unloads and single bit XORs.

Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Abstract: A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode.

Abstract: A computer-on-Module debug card assembly and a control system thereof comprising: a carrier module with a carrier board and electronic components thereon wherein the carrier board is provided with a plurality of I/O connectors and at least a bus; a debug module electrically connected to the carrier board and comprising a debug card and electronic components thereon wherein the debug card is equipped with a detecting component, at least a bus, and a plurality of switch buttons used to check switching; a COM express system electrically connected to the debug card and comprising a COM express board and electronic components thereon wherein the COM express board is provided with modular components and at least a bus. As such, it is able to identify messages for a CPU-bearing COM express board and a carrier board in the COM express system during debugging, streamlining the procedure and saving time.

Abstract: An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.

Abstract: Examples of memory controllers are described that may repair a memory using a bus between the memory controller and the memory. The memory controllers may include a test mode engine able to place the memory into a test mode of operation using a combination of signals over the bus, which combination of signals may be illegal in normal operation. The memory system controllers may include a BIST engine for testing the memory and obtaining information regarding memory fail information. The test mode engines may be configured to adjust a clock frequency during the test mode of operation, including stopping a clock signal in some examples between test mode commands.

Abstract: An integrated circuit with multiple clock domain tracing capability includes a debug module including a global time stamp counter for counting pulses of a reference clock signal to provide a global time stamp, a first granularity counter for counting pulses of a first clock signal to provide a first granularity count, a second granularity counter for counting pulses of a second clock signal to provide a second granularity count and a trace cache buffer for selectively storing in a first partition the global time stamp, the first granularity count, and first data synchronous to the first clock signal, and for selectively storing in a second partition the global time stamp, the second granularity count, and second data synchronous to the second clock signal.

Abstract: Methods and structure are provided for trapping incoming requests directed to hardware registers of an electronic device. The electronic device that comprises a set of hardware registers that define a configuration of the electronic device, circuitry that implements programmable logic defining which hardware registers have been flagged for trapping incoming requests, and a shadow memory that includes values corresponding to the flagged hardware registers. The circuitry is further operable to access a value in shadow memory that corresponds to a flagged hardware register, responsive to receiving a request from an external device to access the flagged hardware register.

Abstract: A data processing apparatus has at least one circuit block accessible for debugging by a debugger, the block having a set of debug status registers and a debug event register which is set by the circuit block to indicate occurrence of a debug event. Debug interface circuitry interfaces with the set of debug status registers for each circuit block. The circuitry includes at least a first portion which is in a first power domain that remains in a fully powered state while the debugger is connected to the circuitry. Status registers are provided in a second power domain which transitions between the fully powered state and at least one low power state while the debugger is connected to the circuitry. Content of the debug status registers is only accessible to the debugger when the second power domain is in the fully powered state.

Abstract: A data processing apparatus having processing circuitry and debug circuitry is debugged by operating the processing circuitry to generate data. The debug circuitry is employed to generate trace elements indicative of the operation of the processing circuitry. Trace elements are caused to be output from the data processing apparatus over a communication bus capable of connecting a plurality of devices. The communication bus is controlled by a protocol for data interchange requiring data interchange from any device on the communication bus to be controlled by a single processing system. The passing of the trace elements onto the communication bus is controlled using an interface unit of the debug circuitry. The interface unit comprises a controller arranged to allow each of the interface unit and processing circuitry to be separate processing systems which can each independently control data interchange from the data processing apparatus.

Abstract: An Accelerated Processing Unit (APU) comprising a central processing unit (CPU) core portion and a graphics processing unit (GPU) core portion coupled to the CPU core portion. The GPU core portion includes a GPU core and a dedicated GPU debugging core, the dedicated GPU debugging core enabling performance of GPU centric debug functions.

Abstract: A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit as part of verification thereof. The method also includes extracting, through the processor, a set of optimized instructions of a test algorithm involved in the verification such that the set of optimized instructions covers a maximum portion of logic functionalities associated with the design of the electronic circuit. Further, the method includes executing, through the processor, the test algorithm solely relevant to the optimized set of instructions to reduce a verification time of the design of the electronic circuit.

Abstract: Systems and methods for testing non-volatile storage devices are disclosed that provide functionality to control when testing of the non-volatile storage device is performed. In one embodiment, information stored in persistent memory indicates whether testing is enabled or disabled. For example, the testing information may indicate that testing is to be performed upon a first initialization of a non-volatile storage device, but not in connection with subsequent power-up events. Furthermore, functionality is disclosed for re-running and/or bypassing testing of the non-volatile storage device.

Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.

Abstract: In one embodiment, an SOC includes multiple components including a CPU complex and one or more non-CPU components such as peripheral interface controllers, memory controllers, media components, etc. The SOC also includes an SOC debug control unit, which is coupled to receive detected debug events from the components. Each component may include a local debug control unit that is configured to monitor for various debug events within that component. The debug events may be specific to the component. The local debug control units may transmit detected events to the SOC debug control unit. The SOC debug control unit may detect one or more events from one or more components, and may halt the components of the SOC responsive to detecting the selected events.

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.

Abstract: Systems, methods, and machine-readable and executable instructions are provided for operating a test infrastructure simulation. Operating a test infrastructure simulation can include executing a test on a number of units under test (UUT) coupled to a test infrastructure and determining capabilities of the test infrastructure based on results of the test executed on the number of UUTs coupled to the test infrastructure.