Access Processor Affected (e.g., I/o Processor, Mmu, Or Dma Processor, Etc.) Patents (Class 714/5.11)
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Patent number: 9658919Abstract: A data processing apparatus includes error detection and correction circuitry with an associated hard-error memory buffer. When a correctable hard-error is detected associated with a memory access to a memory, if the hard-error memory buffer is already full, then this correctable hard-error is escalated to be handled as an uncorrectable hard-error. The escalated uncorrectable hard-error is then handled by uncorrectable error handling circuitry (fatal error circuitry) which may trigger an abort of corresponding processing operations by a processor core and force the relinquishing of resources within other circuit elements such as a store buffer.Type: GrantFiled: April 14, 2015Date of Patent: May 23, 2017Assignee: ARM LimitedInventors: Chiloda Ashan Senerath Pathirane, Allan John Skillman
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Patent number: 9626111Abstract: A mirrored storage system comprising a system controller coupled to a first storage system comprising a primary controller and a first storage and to a second storage system comprising a secondary controller and a second storage. The second storage contains an image of data stored in the first storage. The system controller receives data to be written to storage and sends the data to the primary controller of the first storage system and to the secondary controller of the second storage system. The system controller instructs the primary controller to write the data to the first storage of the first storage system in an ordered manner; and instructs the secondary controller to write the data sequentially to a data area on the second storage of the second storage system. Writing the data sequentially to the second storage improves the write performance.Type: GrantFiled: January 7, 2016Date of Patent: April 18, 2017Assignee: International Business Machines CorporationInventors: Michael Diederich, Frank Krick, Thorsten Muehge, Erik Rueger
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Patent number: 9594640Abstract: A backup/recovery system for a computing environment includes a computing device that executes an agent to obtain a recovery plan (RP) comprising one or more provisioning steps to be performed for provisioning a plurality of resources associated with a source computing environment. The RP including configuration information associated with a hardware configuration and a software configuration of a source computing environment functioning at a first operational level in which the configuration information being sufficient to restore a target computing environment to at least a portion of the first operational level of the source computing environment. From this obtained information, the agent translates the configuration information into a specified format, and outputs the translated configuration information to a computer-readable file.Type: GrantFiled: November 25, 2014Date of Patent: March 14, 2017Assignee: VCE IP Holding Company LLCInventor: Nilay Chheda
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Patent number: 9595979Abstract: Embodiments relate to a system with multiple erasure codes, and selecting and encoding for a write file with one of the codes to mitigate costs associated with storage recovery. The codes include a fast recovery code for frequently accessed data and a higher storage efficiency code for less frequently accessed data. State data is tracked to ascertain frequency of access to the file. One of the erasure codes is dynamically selected based on the tracked data, with the focus of the code select to lower recovery costs, and the data is encoded with the selected erasure code. Accordingly, the original coding of the write file is subject to change based on the tracked state data.Type: GrantFiled: January 20, 2015Date of Patent: March 14, 2017Assignee: International Business Machines CorporationInventors: Mario Blaum, James L. Hafner, David A. Pease, Mohit Saxena, Mingyuan Xia
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Patent number: 9588780Abstract: A method, apparatus and computer program product that allows for maintaining correct states of all sub-components in a state machine, even as sub-components leave the state machine and later rejoin in some previous state. Preferably, this is achieved without requiring the system to remember the states of all sub-components or a log of every event that was fed into the state machine. Thus, the technique does not require any knowledge of the previous state of the sub-components nor the need to preserve a complete log of events that were fed into the state machine. The state machine may be used to enhance the operation of a technological process, such as a workload management environment.Type: GrantFiled: August 20, 2015Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Michael Gerard Fitzpatrick, Andrew Hilliard Arrowood, Gary Owen McAfee, Sue L. Huang
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Patent number: 9591076Abstract: A method begins by a processing module of a dispersed storage network (DSN) determining that a set of storage units has less than a desired number of active storage units, where the DSN includes a plurality of storage units that randomly are active or inactive. The method continues with the processing module identifying another active storage unit of the storage units that is not currently part of the set of storage units and adding the other active storage unit to the set of storage units. For encoded data stored by the set of storage units, the method continues with the processing module increasing a pillar width number of a dispersed storage error encoding function, maintaining a decode threshold number of the dispersed storage error encoding function, creating new encoded data slices for the encoded data, and storing the new encoded data slices in the other active storage unit.Type: GrantFiled: July 22, 2015Date of Patent: March 7, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Teague Scott Algie, Jason K. Resch
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Patent number: 9588779Abstract: A method, apparatus and computer program product that allows for maintaining correct states of all sub-components in a state machine, even as sub-components leave the state machine and later rejoin in some previous state. Preferably, this is achieved without requiring the system to remember the states of all sub-components or a log of every event that was fed into the state machine. Thus, the technique does not require any knowledge of the previous state of the sub-components nor the need to preserve a complete log of events that were fed into the state machine. The state machine may be used to enhance the operation of a technological process, such as a workload management environment.Type: GrantFiled: December 9, 2014Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Michael Gerard Fitzpatrick, Andrew Hilliard Arrowood, Jr., Gary Owen McAfee, Sue L. Huang
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Patent number: 9584363Abstract: Method and apparatus for switching between a first server and a second server, each located within a virtual private cloud and the first server being located within a first zone and the second server being located within a second zone that is physically separate from the first zone. The method and apparatus further configured to determine that the first server has experienced a failure to send or receive data. The method and apparatus further configured to enable a second port on the second server. The method and apparatus further configured to create a new route table at the second server and flush the previous route table. The method and apparatus further configured to transmit, via the second port, a request to a virtual private cloud controller to update an elastic internet protocol address with the second port information and receive data from the virtual private cloud controller.Type: GrantFiled: November 11, 2014Date of Patent: February 28, 2017Assignee: SOFTNAS, LLC.Inventor: Eric Olson
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Patent number: 9575894Abstract: A distributed processing system includes a first site and a second site, each containing at least one device having cache storage, nonvolatile storage, where, in response to moving a process running on the processor of the first site to the processor running on the second site, data in the cache storage of the first site is no longer accessed by the process, the data being read into the cache of the storage of the first site in response to the process accessing data in the non-volatile memory of the first site prior to being moved to the second site. A process running on the processor of the first site moving to the processor running on the second site and corresponding cache slots may be detected by parsing the VMFS containing virtual machine disks used by the process.Type: GrantFiled: March 27, 2015Date of Patent: February 21, 2017Assignee: EMC IP Holding Company LLCInventors: Assaf Natanzon, Brian Lake
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Patent number: 9547567Abstract: An information processing system includes a first control unit including a first memory configured to store first software, and a first controller configured to perform processing based on the first software and to update the first software in a case where an instruction to update the first software is received, and a second control unit configured to be coupled to the first control unit, the second control unit including a second memory configured to store second software that is the same as the first software, a second controller configured to perform processing based on the second software, and a first power supply circuit configured to start power supply to the second controller in a case where a failure in the first control unit is detected.Type: GrantFiled: September 24, 2013Date of Patent: January 17, 2017Assignee: FUJITSU LIMITEDInventor: Ryota Tanaka
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Patent number: 9542117Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.Type: GrantFiled: December 10, 2015Date of Patent: January 10, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi Kunimatsu, Kenichi Maeda
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Patent number: 9529683Abstract: A redundancy method, system, and apparatus, which can acquire first description information of a cloud application needing redundancy, where the first description information includes information about a source virtual machine and a source network which are used at a production site by the cloud application needing redundancy; and can generate second description information of the cloud application needing redundancy at a redundancy site based on the first description information that gives an overall description about the cloud application needing redundancy, where the second description information gives an overall description about the deployment of the cloud application needing redundancy at the redundancy site; and the redundancy site is capable of acquiring the second description information, to recover the cloud application needing redundancy at the redundancy site, thereby implementing redundancy based on a cloud application.Type: GrantFiled: June 11, 2015Date of Patent: December 27, 2016Assignee: Huawei Technologies Co., Ltd.Inventors: Xiangyang Wu, Fengshao Zou, Gaoding Fu
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Patent number: 9514038Abstract: A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.Type: GrantFiled: March 25, 2013Date of Patent: December 6, 2016Assignee: Virident Systems Inc.Inventors: Kenneth A. Okin, Vijay Karamcheti
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Patent number: 9514843Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a control unit, is disclosed to include at least the following steps. A transaction is appended to a bad-column table each time a bad column of a block within the storage unit is inspected. It is determined whether a total number of the transactions within the bad-column table is odd when the control unit determines that the last column of the block is a regular column. A transaction is appended to the bad-column table to indicate that the last column of the block is a bad column when the control unit determines that the total number of the transactions within the bad-column table is odd.Type: GrantFiled: July 9, 2014Date of Patent: December 6, 2016Assignee: SILICON MOTION, INC.Inventor: Han-Cheng Huang
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Patent number: 9501358Abstract: A method includes storing a first subset of encoded data slices of a set of encoded data slices in one local memory, LAN memory, and/or WAN memory. The method further includes storing a second subset of encoded data slices in a different one of the local memory, the LAN memory, and the WAN memory. The method further includes determining to make a change in storage of the set of encoded data slices. The method further includes determining to make an adjustment to the pillar width number based on the determined storage change. The method further includes generating adjusted encoded data slices for the set of encoded data slices based on the adjustment to the pillar width number. The method further includes storing the updated set of encoded data slices in accordance with the determined change in the storage of the set of encoded data slices.Type: GrantFiled: September 1, 2015Date of Patent: November 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Patent number: 9483246Abstract: A method, apparatus, system, and computer program product for an automated modular and secure boot firmware update. An updated boot firmware code module is received in a secure partition of a system, the updated boot firmware code module to replace one original boot firmware code module for the system. Only the one original boot firmware code module is automatically replaced with the updated boot firmware code module. The updated boot firmware code module is automatically executed with the plurality of boot firmware code modules for the system and without user intervention when the system is next booted. The updated boot firmware code module may be written to an update partition of a firmware volume, wherein the update partition of the firmware volume is read along with another partition of the firmware volume containing the plurality of boot firmware code modules when the system is booted.Type: GrantFiled: October 16, 2013Date of Patent: November 1, 2016Assignee: Intel CorporationInventors: Gyan Prakash, Saurabh Dadu, Selim Aissi, Hormuzd M. Khosravi, Duncan Glendinning, Cris Rhodes
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Patent number: 9465707Abstract: The invention introduces a POST (power-On-Self-Test) debugging method, executed by a processing unit, which contains at least the following steps. A phase number indicative of a current POST phase is set. A driver is selected from a scheduled queue. A GUID (Globally Unique Identifier) of the driver is obtained. The phase number and the GUID are stored or output, so as to recognize the phase of the driver being interrupted upon a break point of the driver. After that, the driver is executed.Type: GrantFiled: December 31, 2014Date of Patent: October 11, 2016Assignee: WISTRON CORP.Inventors: Min Hua Hsieh, Yu Hong Chen
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Patent number: 9430333Abstract: The targeted recovery of application-specific data corresponding to an application without performing recovery of the entire volume. The recovery is initiated by beginning to copy the prior state of the content of an application-specific data container from a prior snapshot to the application-specific data container in an operation volume accessible by the application. However, while the content of the application-specific data container is still being copied from the snapshot to the application-specific data container, the application is still permitted to perform read and write operations on the application-specific data container. Thus, the application-specific data container appears to the application to be fully accessible even though recovery of the content of the application-specific data container is still continuing in the background.Type: GrantFiled: March 14, 2013Date of Patent: August 30, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Andrea D'Amato, Vinod R. Shankar
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Patent number: 9407601Abstract: A system and method executed by a client for reliably communicating between the client and a server over a Fiber Channel (FC) network. The method creating a first Small Computer System Interface (SCSI) request, including a virtual connection identifier, sending the first SCSI request to the server over the FC network, determining an action based on a status of the first SCSI request, creating a second SCSI request, including the virtual connection identifier, wherein the second SCSI request is based on the determined action, and sending the second SCSI request to the server over the FC network.Type: GrantFiled: December 21, 2012Date of Patent: August 2, 2016Assignee: EMC CorporationInventor: Joseph C. Pittman
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Patent number: 9405488Abstract: A method, computer program product, and computing system for receiving, on an active storage processor from a passive storage processor, a join request indicator. The join request indicator indicates that the passive storage processor wants to transition to an active status. The active storage processor and the passive storage processor are both coupled to a data array. A status change indicator is provided from the active storage processor to the passive storage processor, wherein the status change indicator indicates that the passive-to-active transition of the passive storage processor has been initiated. A first data array status indicator is received on the active storage processor from the passive storage processor, wherein the first data array status indicator indicates the status of the data array as seen by the passive storage processor.Type: GrantFiled: June 21, 2013Date of Patent: August 2, 2016Assignee: EMC CorporationInventors: Robert P. Foley, Peter Puhov, Naizhong Chiu
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Patent number: 9390118Abstract: A computer implemented method for automatically transforming an event notification within a database notification infrastructure based on client specified formatting and/or editing procedures. The method includes transforming the event notification having a format compatible with a database using a client specific format conversion procedure into a client-compatible event notification format. Further, the method may include transforming the payload portion of the event notification having a format compatible with a database using a client specific format conversion procedure into a linear event notification format. Moreover, the method may include transforming the event notification using a client specific editing procedure. The client specified procedures may be specified during event registration by the client. The transformed and/or edited event notifications may be forwarded to the client.Type: GrantFiled: April 19, 2006Date of Patent: July 12, 2016Assignee: Oracle International CorporationInventors: Kapil Surlaker, Shailendra Mishra
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Patent number: 9385842Abstract: The present disclosure generally pertains to systems and methods for switching data at nodes of a wireless networks. In one exemplary embodiment, a node comprises memory, a first port, a second port, a virtual machine, and logic. The memory is configured to store port settings, and the virtual machine is configured to execute a remote procedure call wirelessly transmitted to the node through the wireless network. In executing the remote procedure call, the virtual machine is configured to set the port settings. The logic is configured to receive data from the first port and to transmit the data to the second port based on the port settings without processing of the data by the virtual machine such that the data streams unchanged through the node from the first port to the second port.Type: GrantFiled: May 8, 2009Date of Patent: July 5, 2016Assignee: Synapse Wireless, Inc.Inventors: David B. Ewing, Kevin R. Banks
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Patent number: 9386043Abstract: A method for use in a system with multiple processor-based devices, the method including: running a first application on a first processor-based device; maintaining a second application in a standby mode on the first processor-based device; and providing a service to each of the first and second applications on the first processor-based device by a service-providing application on the first processor-based device, wherein providing the service includes maintaining a record regarding service statuses of the first application and the second application in which the record stores a respective entry for each of the first and second applications to reflect an active service status for the first application and a standby service status of the second application.Type: GrantFiled: March 31, 2015Date of Patent: July 5, 2016Assignee: GENBAND US LLCInventor: Allain Legacy
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Patent number: 9367394Abstract: Methods and apparatuses for updating members of a data storage reliability group are provided. In one exemplary method, a reliability group includes a data zone in a first storage node and a checksum zone in a second data storage node. The method includes updating a version counter associated with the data zone in response to destaging a data object from a staging area of the data zone to a store area of the data zone without synchronizing the destaging with the state of the checksum zone. The method further includes transmitting, from the data zone to the checksum zone, an update message indicating completion of the destaging of the data object, wherein the update message includes a current value of the version counter.Type: GrantFiled: December 7, 2012Date of Patent: June 14, 2016Assignee: NetApp, Inc.Inventor: Mark Walter Storer
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Patent number: 9361141Abstract: A system for controlling, by a hypervisor, access to physical resources during execution of a virtual machine includes a physical disk and a hypervisor. The physical disk is provided by a computing device and stores at least a portion of a virtual disk. The hypervisor executes on the computing device. The hypervisor allocates, to the virtual disk, an amount of access to the physical disk. The hypervisor determines that a level of utilization of the physical disk has exceeded a threshold. The hypervisor limits, in response to the determination, access by the virtual disk to the physical disk.Type: GrantFiled: September 24, 2013Date of Patent: June 7, 2016Assignee: Citrix Systems, Inc.Inventor: Andrew Kent Warfield
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Patent number: 9348703Abstract: A system for image recovery comprises an input interface and a processor. The input interface is configured to receive a block backup volume that can be mounted. The processor is configured to determine a merged chain map by consolidating one or more incremental chain maps and to store an image using the merged chain map and a volume map.Type: GrantFiled: December 23, 2013Date of Patent: May 24, 2016Assignee: EMC CorporationInventors: Neelabh Mam, Vladimir Mandic, Ravi Shankar
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Patent number: 9348706Abstract: A method and associated systems for monitoring and maintaining a cluster of virtual machines. The cluster contains one or more pairs of a first virtual machine and a second virtual machine, in which each machine of a pair monitors the other one machine of the pair. When a first virtual machine identifies that its corresponding second virtual machine is not operating properly, the first virtual machine automatically requests that a system-management entity restart the second machine. If a certain number of restart attempts fails to restore the second machine to desired functionality, the first virtual machine automatically requests that the system-management entity recreate or reprovision the second virtual machine from a prior backup. If a certain number of such attempts fail, a system administrator is automatically notified that further action is needed.Type: GrantFiled: March 31, 2015Date of Patent: May 24, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Han Chen, Joachim H. Frank, Hui Lei, E. Michael Maximilien, Lin Yang
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Patent number: 9330105Abstract: Systems, methods, and computer readable media for lazy compression of data incoming to a data storage entity are disclosed. According to one aspect, a method for lazy compression of data incoming to a data storage entity includes defining at least a portion of the data storage area within the data storage entity as a compressed logical unit for storing at least some data in compressed form; receiving a command to write data to the compressed logical unit, and, in response to receiving the command to write data to the compressed logical unit, writing the data in uncompressed form; and monitoring for a trigger condition, wherein, upon detection of a trigger condition, at least a portion of the uncompressed data within the compressed logical unit is compressed.Type: GrantFiled: June 23, 2010Date of Patent: May 3, 2016Assignee: EMC CorporationInventors: Dennis Duprey, Mayank Ajmera, Derek Scott
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Patent number: 9311186Abstract: A method begins by a processing module dispersed storage error encoding data to produce a plurality of sets of encoded data slices in accordance with dispersed storage error coding parameters. The method continues with the processing module determining a plurality of sets of slice names corresponding to the plurality of sets of encoded data slices. The method continues with the processing module determining integrity information for the plurality of sets of slice names and sending the plurality of sets of encoded data slices, the plurality of sets of slice names, and the integrity information to a dispersed storage network memory for storage therein.Type: GrantFiled: June 1, 2015Date of Patent: April 12, 2016Assignee: CLEVERSAFE, INC.Inventors: Jason K. Resch, John Quigley, Wesley Leggette
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Patent number: 9292228Abstract: A RAID controller includes a cache memory in which write cache blocks (WCBs) are protected by a RAID-5 (striping plus parity) scheme while read cache blocks (RCBs) are not protected in such a manner. If a received cache block is an RCB, the RAID controller stores it in the cache memory without storing any corresponding parity information. When a sufficient number of WCBs to constitute a full stripe have been received but not yet stored in the cache memory, the RAID controller computes a corresponding parity block and stores the RCBs and parity block in the cache memory as a single stripe.Type: GrantFiled: February 6, 2013Date of Patent: March 22, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Anant Baderdinni, Horia Simionescu, Luca Bert
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Patent number: 9268644Abstract: A RAID module for a RAID controller that includes a thin RAID layer and a thin disk layer. The thin RAID layer sits between an operating system layer and a RAID stack, and intercepts and fields requests and I/Os made the between operating system and the RAID stack. The thin disk layer sits between the RAID stack and the disks that comprise the array, and intercepts and fields requests and I/Os made between the RAID stack and the array. The module may maintain a bitmap with an entry corresponding to each stripe of the array. When the module detects that a stripe has zero data, the entry in the bitmap for the stripe is set to 0. When the module detects that data has been written to a stripe, the entry in the bitmap for the stripe is set to 1.Type: GrantFiled: April 18, 2012Date of Patent: February 23, 2016Assignee: American Megatrends, Inc.Inventors: Srikumar Subramanian, Sankarji Gopalakrishnan, Narayanaswami Ganapathy, Paresh Chatterjee, Udita Chatterjee
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Patent number: 9262144Abstract: A method, system and computer program product for deploying a pattern. A placement engine of a hierarchical tier selects the region(s) of a next lower tier based on placement policies and constraints at the next lower tier and availability of the artifacts required by the virtual machine instance(s) in the next lower tier utilizing the summarization of resource usage and availability at the next lower tier. The placement engine at the lowest tier selects the compute node(s) in the selected region(s) of the lowest tier to place the virtual machine instances of the pattern based on placement policies and constraints at the compute node level and availability of the artifacts required by the virtual machine instance(s) of the pattern in the compute node level. In this manner, the virtual machine instances of the pattern can be effectively deployed when the resources of the cloud environment are large and geographically dispersed.Type: GrantFiled: August 20, 2014Date of Patent: February 16, 2016Assignee: International Business Machines CorporationInventors: Ajay A. Apte, Roy F. Brabson, Theodore O. Kirby, Scott C. Moonen, Donald R. Woods
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Patent number: 9257158Abstract: A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation circuit configured to generate at least one enable signal in response to a source signal and provide the enable signal to each of the repair fuse circuits in common. Since the semiconductor device may iteratively generate a rupture enable signal through a feedback scheme, the area occupied by a circuit, such as a shift register or a D flip-flop may be saved.Type: GrantFiled: July 10, 2014Date of Patent: February 9, 2016Assignee: SK Hynix Inc.Inventor: Hong-Jung Kim
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Patent number: 9256486Abstract: A synchronization controller has a synchronization determiner for determining a synchronization deviation in a CPU, an abnormality sign related information obtainer for obtaining abnormality sign related information on the basis of transaction monitoring information, and an abnormality determiner, when there is a synchronization deviation, for determining the presence/absence of a sign of abnormality in the CPU on the basis of the abnormality sign related information.Type: GrantFiled: August 21, 2012Date of Patent: February 9, 2016Assignee: NEC CorporationInventor: Takanobu Saito
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Patent number: 9250999Abstract: A method includes deploying non-volatile random access memory (NVRAM) in a memory arrangement coupled to a CPU core of a computing device via a memory bus. The method further includes configuring the CPU core to conduct NVRAM read operations directly over the memory bus, and providing an I/O logic device to process write instructions initiated by the CPU core as a Direct Memory Access (DMA) write operation on the NVRAM.Type: GrantFiled: November 19, 2013Date of Patent: February 2, 2016Assignee: Google Inc.Inventor: Luiz Andre Barroso
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Patent number: 9229879Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce power consumption using unmodified information in evicted cache lines. A method includes identifying unmodified information of a cache line stored in a cache of a processor, tracking the unmodified information using a bit vector comprising one or more bits to indicate the unmodified information of the cache line, and selectively suppressing a write operation or send operation for the unmodified information of the cache line that is evicted from the cache to an input/output (I/O) component coupled to the cache, the selective suppressing being based on the one or more bits, and the I/O component being an outer component external to the cache. Other embodiments may be described and/or claimed.Type: GrantFiled: July 11, 2011Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Mahesh K. Kumashikar, Ashok Jagannathan
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Patent number: 9213648Abstract: A computer-executable method, system, and computer program product for managing a data storage system, wherein the data storage system includes a cache and a data storage array, the computer-executable method comprising receiving a request to initialize a data storage system and initializing the data storage system by purging the cache.Type: GrantFiled: December 31, 2013Date of Patent: December 15, 2015Assignee: EMC CorporationInventors: Guido A. DiPietro, Michael J. Cooney, Gerald E. Cotter
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Patent number: 9213588Abstract: A storage system and method for identifying a faulty link the storage system is disclosed. The storage system includes a plurality of target devices and at least one expander configured to communicatively couple a plurality of initiators to the plurality of target devices. Each initiator of the plurality of initiators monitors occurrences of link disruptions independently, wherein upon detecting occurrences of a predetermined number of link disruptions within a predetermined time period, a reporting initiator reports a detection of a faulty link in the multi-initiator topology and requests an arbitrator to identify at least one peer initiator in the multi-initiator topology that shares at least one shared link with the reporting initiator. This reporting initiator and its peer initiators then jointly execute a common diagnostic process to identify the faulty link in the multi-initiator topology.Type: GrantFiled: January 28, 2014Date of Patent: December 15, 2015Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Naman Nair, Brad D. Besmer, Peter C. Rivera, James Rizzo
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Patent number: 9176823Abstract: A backup image generator can create a primary image and periodic delta images of all or part of a primary server. The images can be sent to a network attached storage device and a remote storage server. In the event of a failure of the primary server, the failure can be diagnosed to develop a recovery strategy. Based on the diagnosis, at least one delta image may be applied to a copy of the primary image to generate an updated primary image at either the network attached storage or the remote storage server. The updated primary image may be converted to a virtual server in a physical to virtual conversion at either the network attached storage device or remote storage server and users may be redirected to the virtual server. The updated primary image may also be restored to the primary server in a virtual to physical conversion. As a result, the primary data storage may be timely backed-up, recovered and restored with the possibility of providing server and business continuity in the event of a failure.Type: GrantFiled: January 3, 2014Date of Patent: November 3, 2015Assignee: DSSDR, LLCInventor: Andrew Bensinger
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Patent number: 9170890Abstract: A system and method for transferring data in a library storage system. The library storage system comprises a management server including a storage policy. A media agent is connected to the management server. A plurality of storage media and a data source are connected to the media agent. The data source is divided into at least a first and a second portion of data. The portions of data are transferred from the data source to a first and second primary storage medium using a first and a second data stream respectively. The media agent then causes the first and second portion of data to be transferred from the first and second storage medium to a third auxiliary storage medium using a third combined data stream. Auxiliary copying is performed in chunks and multiple streams are copied in parallel.Type: GrantFiled: February 28, 2014Date of Patent: October 27, 2015Assignee: Commvault Systems, Inc.Inventors: Jun Lu, Parag Gokhale
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Patent number: 9172600Abstract: An InfiniBand managed storage environment is made up of processor nodes containing HCAs and managed storage devices containing TCAs and exposing a plurality of LUNs and volumes. For each InfiniBand channel between a specific HCA and a specific TCA, the paths between the HCA and any LUN or volume exposed by the TCA are grouped into a set. Occurrence of failures on specific paths of specific sets on specific channels are determined, for example by registering for callbacks or polling for occurrence of events which adversely affect communication between endpoints. Also, I/O operations executed by processor nodes are tracked and failures thereof are detected. When the occurrence of a failure on a specific path of a set is determined, all I/O operations on all paths of the set are proactively rerouted to a separate set on a separate channel that connects the same processor node and storage device.Type: GrantFiled: December 31, 2013Date of Patent: October 27, 2015Assignee: Symantec CorporationInventor: Anurag Vora
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Patent number: 9164830Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.Type: GrantFiled: January 14, 2014Date of Patent: October 20, 2015Assignee: SEAGATE TECHNOLOGY LLCInventors: Navneeth Kankani, Mark Allen Gaertner, Rodney Virgil Bowman, Ryan James Goss, David Scott Seekins, Tong Shirh Stone
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Patent number: 9158477Abstract: Provided are a computer implemented method, computer program product, and system for maintaining state information. An available node affiliated with an unavailable device adapter and an unavailable node affiliated with an available device adapter are identified, wherein the available node is assigned a first subset of disk arrays, and wherein the unavailable node is assigned a second subset of disk arrays. The available device adapter is affiliated with the available node. First state information of the first node that describes a state of the first subset of disk arrays is updated with second state information of the second node that describes a state of the second subset of disk arrays. Access to the first subset of disk arrays and the second subset of disk arrays is provided through the available node and the available device adapter using the updated first state information.Type: GrantFiled: October 15, 2012Date of Patent: October 13, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anjul Mathur, Karl A. Nielsen
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Patent number: 9152513Abstract: Technology is disclosed for recovering I/O modules in a storage system using in-band alternate control path (ACP) architecture (“the technology”). The technology enables a storage server to transmit control commands, e.g., for recovering an I/O module, to the I/O module over a data path that is typically used to transmit data commands. The control commands are typically transmitted using ACP that is separate from the data path. By enabling transmission of control commands over the data path, the technology eliminates the need for separate medium for ACP, at least in part, to transmit the control commands. The technology can be implemented in a pure in-band ACP mode, which supports recovering an I/O module of a storage shelf in which at least one I/O module is responsive, and/or in a mixed in-band ACP mode, which supports recovery of I/O modules of a storage shelf in which all I/O modules are non-responsive.Type: GrantFiled: January 21, 2014Date of Patent: October 6, 2015Assignee: NetApp, Inc.Inventors: Mayank Saxena, Melvin McGee
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Patent number: 9146937Abstract: A client computing device having a processor and a memory receives, in response to a request, a replication layout from a replication controller. The client device initiates a data replication request at each of a plurality of data servers according to the replication layout. The client device receives, from each of the data servers, integrity information representing a state of a replication dataset at each of the servers. The client device transmits the integrity information to the replication controller.Type: GrantFiled: June 22, 2012Date of Patent: September 29, 2015Assignee: Cohort FS, LLCInventors: Matthew W. Benjamin, Adam C. Emerson, Peter Honeyman
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Patent number: 9141548Abstract: A network services processor includes an input/output bridge that avoids unnecessary updates to memory when cache blocks storing processed packet data are no longer required. The input/output bridge monitors requests to free buffers in memory received from cores and IO units in the network services processor. Instead of writing the cache block back to the buffer in memory that will be freed, the input/output bridge issues don't write back commands to a cache controller to clear the dirty bit for the selected cache block, thus avoiding wasteful write-backs from cache to memory. After the dirty bit is cleared, the buffer in memory is freed, that is, made available for allocation to store data for another packet.Type: GrantFiled: January 20, 2014Date of Patent: September 22, 2015Assignee: Cavium, Inc.Inventors: David H. Asher, Gregg A. Bouchard, Richard E. Kessler, Robert A. Sanzone
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Patent number: 9135114Abstract: A method begins by a processing module storing data files utilizing a dispersed storage error coding function that includes a pillar width parameter and a decode threshold parameter. The method continues with the processing module determining whether to adjust redundancy of the dispersed storage error coding function based on performance of the DSN. When the redundancy of the dispersed storage error coding function is to be adjusted, changing a ratio between the pillar width parameter and the decode threshold parameter and adjusting storage of one or more sets of the plurality of sets of encoded data slices based on the changing of the ratio.Type: GrantFiled: September 9, 2014Date of Patent: September 15, 2015Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Patent number: 9131090Abstract: The invention relates to an information processing apparatus which performs mirroring for synchronizing storage contents of a first storage unit and a second storage unit. If mirroring is valid when the information processing apparatus is started, the information processing apparatus detects a storage unit attached to itself. If a detection result indicates that no storage unit has been detected or one storage unit has been detected, the information processing apparatus displays, on a display unit, a connection acknowledgement screen for the storage unit which has not been detected. If the detection result indicates that two storage units have been detected, activation processing is executed for the information processing apparatus.Type: GrantFiled: November 15, 2012Date of Patent: September 8, 2015Assignee: Canon Kabushiki KaishaInventors: Koji Shimizu, Keishi Inaba, Kohei Asano, Kiyokazu Umimura, Yuji Naya, Yuichi Konosu
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Patent number: 9110739Abstract: Methods, systems, and computer-readable media are provided to allow multiple server resources to share a single connection to a client device. The single connection may be maintained between a notification queue on the server side and the client device. Multiple server resources share the notification queue. When a resource changes or a service wants to communicate information to a client, corresponding messages are sent to the notification queue over a connection within the data center. Once in the notification queue, the updates are communicated to the client device.Type: GrantFiled: June 7, 2011Date of Patent: August 18, 2015Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: John R. Burkhardt, Ransom Richardson, Jason Schleifer, Steven Lees
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Patent number: 9110834Abstract: A method begins by a processing module establishing a dispersed storage (DS) error coding function based on a number of local memories associated with the computing device, wherein a decode threshold number of the DS error coding function corresponds to the number of local memories. The method continues with the processing module encoding a data segment of data utilizing the DS error coding function to produce a set of encoded data slices, of which the decode threshold number of encoded data slices is required to recover the data and the set of encoded data slices includes a pillar width number of encoded data slices. The method continues with the processing module storing the decode threshold number of encoded data slices in the local memories and outputting a remaining number of encoded data slices of the set of encoded data slices to the dispersed storage network (DSN) memory for storage therein.Type: GrantFiled: September 9, 2014Date of Patent: August 18, 2015Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Gary W. Grube, Timothy W. Markison