Control Flow State Sequence Monitored (e.g., Watchdog Processor For Control-flow Checking) Patents (Class 714/51)
  • Patent number: 7543195
    Abstract: A method and system to enter a time out interval in a storage area network includes identifying a time slot in a sequence of time slots to insert a time out event for the event in the storage area network, determining if other events in the storage network already have corresponding other time out events in the same time slot and inserting the time out event for the event in the identified time slot along with the other time out events and the other corresponding events. Monitoring time out intervals for the events includes receiving a request to determine if events in the storage area network have timed out, identifying events associated with a current time slot, determining if the identified current time slot is empty, removing events from the identified current time slot in response to the determination and notifying a time-out handler to perform appropriate time-out related processing.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: June 2, 2009
    Assignee: NetApp, Inc.
    Inventors: Tuan Nguyen, Rahim Ibrahim, Nghiep Tran
  • Patent number: 7540026
    Abstract: A method includes stalling execution of a model specific register write function to write to a model specific register of a processor having a no-execute processor feature enabled, determining that the model specific register is a no-execute model specific register of the processor, and determining whether a no-execute field in the no-execute model specific register is being altered. Upon a determination that the no-execute field is being altered, the method further includes taking protective action to prevent disabling of the no-execute processor feature.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: May 26, 2009
    Assignee: Symantec Corporation
    Inventors: Peter Szor, Peter Ferrie
  • Patent number: 7533304
    Abstract: A method and system of signal noise reduction used for digital chips to prevent errors when signal noise occurs includes checking whether a recent received signal is logically consistent. If the recent signal is consistent, then the consistent signal is adopted. If the recent signal is not consistent, then a previous confirmed signal is adopted.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: May 12, 2009
    Assignee: Wistron Corporation
    Inventor: Tung-Sheng Lin
  • Patent number: 7529983
    Abstract: A circuit arrangement for supporting and monitoring a microcontroller, which is constructed externally of the microcontroller, comprises a watchdog circuit for monitoring the microcontroller, which circuit outputs an error signal if not reset by the microcontroller within a watchdog period, and an interrupt circuit, which feeds important system messages to the microcontroller as interrupt events for processing. In order correctly to combine interrupt processing and watchdog operation, the watchdog circuit is connected to the interrupt circuit and cooperates therewith in such a way that the interrupt circuit feeds at most a predetermined number of interrupt events to the microcontroller within a watchdog period.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: May 5, 2009
    Assignee: NXP B.V.
    Inventor: Martin Wagner
  • Patent number: 7523353
    Abstract: A scheme for monitoring links in a point-to-point architecture computer system is discussed. The scheme monitors labels for transactions to determine if they have been reissued within a user selected time window. A corresponding position in a register is updated to reflect the value of the transaction identifier. Subsequently, after the expiration of a counter, the corresponding position in the registers is compared to other predetermined positions in other registers to determine if the transaction identifier has been used (reissued). Otherwise, a possible hang condition might have occurred.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: April 21, 2009
    Assignee: Intel Corporation
    Inventor: Robert Roth
  • Patent number: 7506217
    Abstract: A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update a signature register with a successor basic block signature at an end of the basic block. In addition, the basic block is instrumented to verify that contents of the signature register match a basic block signature at a beginning of the basic block. In one embodiment, an instruction is inserted within the basic block to cause the signature register to store a predetermined value if the contents of the signature register match a basic block signature. In one embodiment, a basic block may be subdivided into a plurality of regions; each region is assigned a signature and instrumented to update the signature register at a beginning of each region. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Edson Borin, Cheng C. Wang, Youfeng Wu
  • Patent number: 7496800
    Abstract: In a method, an interrupt is generated to the processing unit every predetermined period. The predetermined period is shorter than a predetermined timeout period. A watchdog signal is changed in response to each of the generated interrupts. The interrupt generation is disabled, upon the last interrupt being generated over an estimated time when the execution of the program is estimated to be completed.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: February 24, 2009
    Assignee: Denso Corporation
    Inventors: Kazuhiro Koto, Hirokazu Komori, Tadaharu Nishimura
  • Patent number: 7496916
    Abstract: Methods, systems and articles of manufacture for performing multiple request processing. Redundant instances of executing entities service requests in a time-delayed fashion, relative to one another. In this way, a user can be returned to an earlier state by switching to the execution flow of one of the other executing entities.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: February 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Richard D. Dettinger, Frederick A. Kulack, Richard J. Stevens, Eric W. Will
  • Patent number: 7496797
    Abstract: Embodiments of the invention may provide a method to send a packet from an endpoint in an advanced switching fabric and starting a timer to run until receiving a response packet or receiving an event packet notifying of a device failure, save a copy of the sent packet, detect if the timer has expired, retransmit the packet after the timer has expired and resetting the timer; and run a faulty device detection algorithm if the packet has been retransmitted a predetermined number of times. Furthermore, some embodiments may provide an apparatus with a retransmit buffer, and an endpoint that can send a packet and save a copy of the packet in the retransmit buffer, detect if a timer expired and retransmit the packet after the timer has expired and no packet was received in response to the transmitted packet, and run a faulty device detection algorithm.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: February 24, 2009
    Assignee: Intel Corporation
    Inventors: Mo Rooholamini, Randeep Kapoor, Ward McQueen
  • Publication number: 20090044185
    Abstract: Embodiments of a workflow-based user interface for defining and managing functions implemented on mobile devices are described. A method under an embodiment utilizes a workflow-based mobile device management user interface. The method utilizes a pluggable workflow framework to achieve mobile device management externalization. The mobile device management platform is required to implement a set of basic action blocks that are used as primitives for further management policy composition. The method provides a development environment integrated with a mobile device management platform that allows assembling management (monitoring) primitives into meaningful management policies without changes to a core management platform infrastructure. The method claims addition of new primitives deployed as add-on products to enable new and advanced management policies, best integration practices with a carrier operational support system.
    Type: Application
    Filed: August 8, 2008
    Publication date: February 12, 2009
    Applicant: INNOPATH SOFTWARE, INC.
    Inventor: Eugene Krivopaltsev
  • Patent number: 7487407
    Abstract: Method and apparatus for identifying a cause for a response time problem for a transaction in a distributed computing system that includes a central server and a plurality of subsystems. Data is stored at each subsystem relating to sub-transactions of transactions performed by the subsystems. When a problem is discovered in connection with the completion of a particular transaction, each subsystem of the plurality of subsystems that was involved in the particular transaction is identified, and both instance data relating to all of the sub-transactions of the particular transaction stored at each identified subsystem and current hourly aggregate data stored at each identified subsystem is forwarded to the central server. Root-Cause Analysis is then performed using the forwarded instance data and aggregate data to identify the particular subsystem that caused the transaction problem.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Byron Christian Gehman, Sandra Lee Tipton
  • Patent number: 7484069
    Abstract: A data processing system incorporating watchpoint registers is provided. The memory accesses to be detected may be unaligned memory accesses. The watchpoint may operate in a normal mode and also in a guard mode. In the guard mode of operation a watchpoint comparator generates a match signal if the upper N bits of the memory address match the upper end bits of the watchpoint address and the length of the memory access L is such that the memory access extends to include a memory address having a different upper N bits but located at a predetermined address offset P from the watchpoint address W.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: January 27, 2009
    Assignee: ARM Limited
    Inventor: Michael John Williams
  • Patent number: 7454664
    Abstract: Commanding a JTAG bus cross point switching device by the same bus which it configures. Adding, omitting, or rearranging devices on a JTAG bus with a cross point switching device that is included in a JTAG chain. Controlling the switching device with commands on the JTAG bus which it configures.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Mike Conrad Duron, Robert Allan Faust, Forrest Clifton Gray, Ajay Kumar Mahajan, Glenn Rueban Miles
  • Patent number: 7428674
    Abstract: Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitoring the state vector includes a TAP controller, a storage circuit, and a sampling circuit. The TAP controller updates the state vector for each transition of TCK. The storage circuit stores a value of the state vector responsive to transitions of TCK while a write enable is enabled. To permit generating the write enable without additional pins and without violating a protocol for the test access port, the write enable may be generated in response to a plurality of transitions of TDI of the test access port during an interval in which TMS and TCK of the test access port have no transitions.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: September 23, 2008
    Assignee: XILINX, Inc.
    Inventor: Neil G. Jacobson
  • Patent number: 7406634
    Abstract: A method and apparatus utilizes an exception handler to implement LOAD and STORE instructions for moving data between a peripheral device and CPU registers. TLB entries for peripheral devices are flagged invalid during initialization and an exception handler occurs when LOAD or STORE instructions are executed by the CPU. The exception handler programs a data mover to perform the LOAD or STORE instruction so that the CPU will not hang up in the event that the peripheral device does not respond thereby avoiding reset of the SOC by the watchdog timer. If the peripheral device does not respond before an exception handler timer expires an error is indicated by the exception handler.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: July 29, 2008
    Assignee: Cisco Technology, Inc.
    Inventor: Sampath Kumar
  • Publication number: 20080148107
    Abstract: An electronic control device according to an embodiment of the present invention includes an arithmetic device such as a microcomputer having a watchdog timer circuit, and a runaway monitoring circuit which monitors the arithmetic device for an operational failure by receiving a pulse output from the arithmetic device, in which the watchdog timer circuit or the runaway monitoring circuit detects occurrence of a failure of the arithmetic device according to the state (high level or low level) of an indication signal (wakeup signal) which shows the operational state of the arithmetic device.
    Type: Application
    Filed: December 14, 2007
    Publication date: June 19, 2008
    Applicant: FUJITSU TEN LIMITED
    Inventors: Naoyuki Takaishi, Kazuhiro Komatsu, Tomohide Kasame, Masanori Akaza, Shinichiro Takatomi, Kazuhi Yamaguchi, Tomoko Satomi, Megumi Fukuta, Takashi Matsui
  • Patent number: 7386411
    Abstract: An exemplary automatic hi-pot test apparatus (20) includes a high voltage supply (21), a transmission device configured for transmitting an electronic device (26) to be tested, a connecting device electrically connected to the high voltage supply and configured for moving and electrically connecting with or electrically disconnecting from the electronic device, a controller (28) for controlling the connecting device and the transmission device, and a detector (27) for detecting the presence of the electronic device. When the detector detects the presence of the electronic device, the detector sends a corresponding detecting signal to the controller, such that the controller stops the electronic device and drives the connecting device to electrically connect with the electronic device whereby a hi-pot test can be performed.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: June 10, 2008
    Assignees: Innocom Technology (Shenzhen) Co., Ltd., Innolux Display Corp.
    Inventors: Yan-Kai Zhang, Jun-Hua Yang, Yi Wang
  • Patent number: 7383469
    Abstract: An application management system and method is proposed. The application management system includes a first processor and a second processor. The first processor executes an application in a computer system. The second processor includes a monitor module to monitor the execution status of the application. If the execution status of the application is abnormal, the monitor module enables the computer system to reboot, and uses the first processor to re-execute the application.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: June 3, 2008
    Assignee: Acer Incorporated
    Inventor: Li-Yen Yang
  • Patent number: 7383470
    Abstract: A method, system, and apparatus are provided for identifying unresponsive portions of a computer program. According to the method, program code that can potentially result in unresponsive behavior is wrapped in timers. A timer is started on a background thread at the beginning of the execution of a section of program code. The timer is set to expire after a specified threshold period of time has expired. A determination is made as to whether the timer expires during the execution of the section of program code. If the timer expires during the execution of the section of program code, execution is interrupted and the section of program code is identified as unresponsive and system state information is stored for use in diagnosing the computer program and remedying the unresponsive behavior. The actual system state information stored may be defined by a remote control file and may be stored at or around the time the timer expires.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: June 3, 2008
    Assignee: Microsoft Corporation
    Inventors: Benjamin Elliott Canning, Thomas Scott Coon
  • Publication number: 20080114852
    Abstract: A method and system of establishing communications between at least two independent software modules is provided. The design comprises providing a media connection between software modules, wherein the software modules employ a communications protocol and participate in a bi-directional master-slave relationship between a master module and a slave module. The design further comprises sending arbitrary data between the master and slave modules, wherein the arbitrary data is used by the master module to control and obtain status from the slave module, and sending arbitrary data further enables the slave module to return data and status information to the master module. The design also employs a communications watchdog between the master and slave modules, wherein the communications watchdog monitors communications quality between the master and slave modules and impairs functionality in the master and slave modules when communications quality degrades.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 15, 2008
    Applicant: Advanced Medical Optics, Inc.
    Inventors: Michael J. Claus, Hao V. Nguyen
  • Patent number: 7373623
    Abstract: A system and method for locating circuit deviations or circuit faults in a circuit in respect of a reference circuit. The circuit and the reference circuit are respectively describable by signal-flow graphs, the signal-flow graphs being composed of a multiplicity of interconnected function blocks. The function blocks of the circuit are first assigned to corresponding function blocks of the reference circuit. There are then ascertained those function blocks of the circuit and of the reference circuit for which assignment has not been possible, and which have disposed upstream in the signal flow at least one function block for which assignment has been possible. The result is a boundary between an assigned and a non-assigned region of the circuit and the reference circuit, respectively. A representation of the circuit and reference circuit is preferably produced in which the regions corresponding to the non-assigned function blocks are highlighted.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: May 13, 2008
    Assignee: Onespin Solutions GmbH
    Inventor: Stefan Horeth
  • Publication number: 20080072106
    Abstract: In a computer programming language environment operating with a real-time clock, a method comprises: providing an instruction in the programming language for performing an action and for specifying an explicit time for performing the action, the instruction including at least a first parameter for specifying whether the action should be performed in a case where the real-time clock indicates that the specified explicit time when the action is to be performed has passed; and providing a means for at least one of (1) signaling an error, and (2) specifying a function to be performed, in a case where the real-time clock indicates that the specified explicit time when the action is to be performed has passed.
    Type: Application
    Filed: September 20, 2006
    Publication date: March 20, 2008
    Inventor: Bruce Hamilton
  • Patent number: 7334167
    Abstract: In a circuit for detection of internal microprocessor watchdog device execution comprising a microprocessor (6) with the internal watchdog device and with an input/output line (11) transmitting information about microprocessor reset, and a device for resetting the microprocessor system, to the input/output line (11) transmitting information about microprocessor (6) reset, a clock input CK is connected, which triggers the flip-flop (12), whose data input D and an inverted reset input /R are connected to the output of the device (19) for resetting the microprocessor system, and the inverted flip-flop (12) output /Q is connected to the input of the device (19^) for resetting the microprocessor system.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: February 19, 2008
    Assignee: Advanced Digital Broadcast S.A.
    Inventor: Marcin Stabrowski
  • Patent number: 7325171
    Abstract: A measurement and data acquisition system including a real-time monitoring circuit for implementing control loop applications. The system control loop may include the real-time monitoring circuit, a data acquisition device, a processing unit, and a plurality of subsystems. The subsystems may be comprised in the data acquisition device or may be external to the data acquisition device. The real-time monitoring circuit may receive a plurality of timing signals from the plurality of subsystems and may select a control loop timing signal out of the plurality of timing signals. The real-time monitoring circuit may determine whether the operations of the control loop are performed within a particular period of time by monitoring the control loop timing signal and communicating with the processing unit. In response to an error notification, the processing unit may take appropriate action, such as shutting down the system and/or reporting an error or warning.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: January 29, 2008
    Assignee: National Instruments Corporation
    Inventor: Rafael Castro
  • Patent number: 7321213
    Abstract: A motor controller is provided with: an estimated temperature calculating means that calculates an estimated temperature of a motor; and a control unit that can perform a driving control of the motor only when the estimated temperature is not larger than a predetermined value. A mode switching means switches the control unit and the estimated temperature calculating means between in a normal operation mode in which they can drive the motor and in a sleep mode in which electric power consumption thereof is smaller than in the normal operation mode in accordance with a predetermined condition while the motor is stationary. An activating means activates the estimated temperature calculating means in the sleep mode for a predetermined active time every time a predetermined sleep time is elapsed.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: January 22, 2008
    Assignee: ASMO Co., Ltd.
    Inventors: Shigeru Kobayashi, Seiichi Watanabe, Seiichi Tanaka
  • Patent number: 7321214
    Abstract: A controller is operable in one of a plurality of operational modes, which include an estimated temperature computation performing mode for performing computing of an estimated temperature of the motor and an estimated temperature computation non-performing mode for stopping the computing of the estimated temperature of the motor. An operational mode of the controller is changed from the estimated temperature computation performing mode to the estimated temperature computation non-performing mode according to a predetermined condition in a stopped state of the motor.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: January 22, 2008
    Assignee: ASMO Co., Ltd.
    Inventors: Shigeru Kobayashi, Keizo Ishizu
  • Patent number: 7299383
    Abstract: The method is implemented with a management system of the time-triggered architecture type in association with a processor of a central processor unit that possesses a privileged execution mode to which access is protected by an instruction of the “call to system layer” type. The only system layer call that is authorized from an application task under consideration to the system layer consists in reporting a change of node in the control graph of the task in question. When the system layer has verified that the call is legal relative to the execution paths of the control graph as described in the constant tables of the application, all of the operations to be performed on the node in question by the system layer are predetermined by the constant tables of the application associated with the system layer.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: November 20, 2007
    Assignees: Commissariat a l'Energie Atomique, Areva Np
    Inventors: Vincent David, Jean Delcoigne
  • Patent number: 7299437
    Abstract: A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a multi-cycle path detector determines whether all the paths in the path set are multi-cycle paths. When the path set is a multi-cycle path, it is added to a timing exception path list that is output by an output unit.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: November 20, 2007
    Assignee: Fujitsu Limited
    Inventor: Hiroyuki Higuchi
  • Patent number: 7296186
    Abstract: The present invention is directed to a system-on-chip development apparatus for wire/wireless Internet telephone. The system-on-chip development apparatus for wire/wireless Internet telephone according to the present invention adds functions indispensable to a RISC core, constructs a core kernel section using a device integrating additional FPGAs available to support additional functions, and provides a plurality of interfaces necessary to an Internet telephone function centering around the core kernel section. With this, the number of necessary component parts can be minimized to facilitate design and simplify the configuration thereof.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: November 13, 2007
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Woon-Seob So, Dae-Hwan Hwang, Bong-Tae Kim
  • Patent number: 7293198
    Abstract: A data storage system has a first storage processor, a second storage processor, and a communications subsystem. The communications subsystem has (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a clock circuit coupled to the interfacing portion, and (iii) a controller coupled to the interfacing portion and the clock circuit. The controller is configured to enable operation of the interfacing portion to provide communications between the first and second storage processors, sense a failure within the clock circuit, and reset the interfacing portion in response to the sensed failure to enable one of the first and second storage processors to continue operation. Such resetting of the interfacing portion prevents the remaining storage processor from locking up, thus freeing that storage processor so that it is capable of continuing to operate even after the failure.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: November 6, 2007
    Assignee: EMC Corporation
    Inventors: Stephen Strickland, John V. Burroughs, Timothy Dorr
  • Publication number: 20070255980
    Abstract: A program to be executed by a computer is divided into a plurality of code blocks, and, a unique code block ID is allotted to each code block. At the moment when the execution of the program is started, the code block ID corresponding to the execution start address is written in a memory, and in the case when the control transits from the code block to other code block, by use of code block operation values obtained beforehand from these two code block IDs thereof, the code block ID in the memory is updated, and it is judged whether the updated code block ID in the memory and the code block ID allotted to the code block as the execution objective are identical or not so that a control flow error is detected.
    Type: Application
    Filed: April 12, 2007
    Publication date: November 1, 2007
    Inventors: Takashi ENDO, Toshio Okochi, Takashi Watanabe, Shunsuke Ota, Tatsuya Kameyama
  • Patent number: 7287199
    Abstract: A method capable of detecting a status of a basic input/output system (BIOS) for setting a clock is applied to a clock generating device of a computer motherboard and sets the clock according to a signal status of the BIOS or a trigger signal. A device capable of detecting the BIOS status for setting the clock is also proposed. The device has a crystal oscillator, a frequency control unit, a phase-lock-loop (PLL) spread-spectrum unit electrically connected with the crystal oscillator and the frequency control unit, a memory unit having a clock setting value stored therein, a detection control unit electrically connected with the memory unit and used to detect a signal status, and a logic control unit electrically connected with the PLL spread-spectrum unit, the frequency control unit and the detection control unit.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: October 23, 2007
    Assignee: Giga-Byte Technology Co., Ltd.
    Inventor: Yen Sheng Chang
  • Patent number: 7281040
    Abstract: A network device for use in a communication system having a technical support center operated by a technical support staff, the technical support center being in communication with the network device through a packet switching network. The network device includes one or more hardware subsystems, one or more software subsystems and means for monitoring the status of the hardware and software subsystems so that when a problem occurs with respect to one or more of the hardware and software subsystems of the network device, the network device for transmitting a first message to the technical support center to notify the technical support center of the problem, wherein the technical support staff is able to diagnose the problem without interruption to the operation of the network device.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: October 9, 2007
    Assignee: Cisco Technology, Inc.
    Inventor: John Dung-Quang Ly
  • Patent number: 7272646
    Abstract: A method and apparatus for a network monitor internals mechanism that serves to translate packet data into multiple concurrent streams of network event data is provided. The data translation is accomplished by interpreting both sides of each protocol transaction.
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: September 18, 2007
    Assignee: Securify, Inc.
    Inventors: Geoffrey Cooper, Robert Allen Shaw, Luis Filipe Pereira Valente, Kieran Gerard Sherlock
  • Patent number: 7251551
    Abstract: An on-vehicle electronic control device includes an auxiliary microprocessor and subjects a microprocessor allocated to a main part of control to an external diagnosis, thereby improving reliability of performance. A microprocessor including a nonvolatile program memory into which a control program is written is serially connected to an auxiliary microprocessor including an auxiliary nonvolatile program memory. The microprocessor and the auxiliary microprocessor function in cooperation to control on-vehicle electric load groups in response to input signals from on-vehicle sensor groups and on-vehicle analog sensor group. The nonvolatile program memory and the microprocessor are subjected to runaway monitoring performed by a watchdog timer and to an external checksum diagnosis performed periodically by the auxiliary microprocessor. If an anomaly occurs in the runaway monitoring, the external checksum diagnosis, and a checksum interval, parts of electric loads are cut off of power supply by load power relay.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: July 31, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyuki Mitsueda, Katsuya Nakamoto, Kohji Hashimoto
  • Patent number: 7246267
    Abstract: A logic analyzer according to the subject invention includes a disassembler for disassembling object code. The disassembler automates the process of locating op-code addresses by utilizing information derived from an object file corresponding to the code whose execution is being disassembled. The object file includes addresses for the starting location of op-codes corresponding to individual source code lines. When the disassembler cannot determine the correct starting location for an op-code, it uses information from the object file to obtain the address of an op-code within a specified range of interest.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 17, 2007
    Assignee: Tektronix, Inc.
    Inventors: David L. Bennett, Robert J. Heath, Mark L. Millard
  • Patent number: 7219264
    Abstract: Methods and systems for preserving dynamic random access memory content in response to a hung processor condition are disclosed. In order to preserve dynamic random access memory content, a first watchdog timer is initiated and strobed at a predetermined time interval less than its timeout value. If a hung processor condition occurs and the strobing of the first watchdog timer fails, the first watchdog timer generates a non-maskable interrupt to the processor. The non-maskable interrupt triggers the processor to execute an interrupt service routine. If the processor is able to execute the interrupt service routine, the interrupt service routine controls the processor to perform a selective system reset and preserve dynamic random access memory contents. If the processor is not capable of executing the interrupt service routine, a board reset occurs and dynamic random access memory contents are cleared.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: May 15, 2007
    Assignee: Tekelec
    Inventors: Michael R. Pail, Robert Wallace, Jeremy T. Baus
  • Patent number: 7219268
    Abstract: Disclosed are systems and methods for determining time-outs with respect to a plurality of transactions comprising utilizing a first time-out clock for simultaneously determining time-out states with respect to a first set of transactions of the plurality of transactions, and determining when transactions of the first set of transactions have reached a timed-out state of the time-out states.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: May 15, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard W. Adkisson, Huai-Ter V. Chong
  • Patent number: 7216265
    Abstract: An improved method and system for determining the state of an operating system includes an operating system, a USB host controller that is driven by the operating system to send a polling signal to a USB device, and a management module that monitors the polling signal. If the polling signal has stopped, then the management module takes corrective action to restore the operating system. No specialized software or specialized hardware is required to determine the state of the operating system. The state of the operating system can be determined quickly and efficiently without adding to the costs of the system.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: May 8, 2007
    Assignee: International Business Machines Corporation
    Inventors: James E. Hughes, Eric R. Kern, Thomas D. Pahel, Jr.
  • Patent number: 7200781
    Abstract: Techniques and apparatus are disclosed for detecting and responding to the malfunction of a host coupled to a communications bus through a bus transceiver.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: April 3, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paul John Mantey, David R. Maciorowski, Michael D. Young
  • Patent number: 7194665
    Abstract: An integrated circuit, a client computer system, and a method for operating the integrated circuit in the client computer system. The integrated circuit includes a first bus interface logic for coupling to a first external bus, a microcontroller configured as an Alert Standard Format management engine, and a watchdog timer coupled to the microcontroller. The microcontroller is further configured to receive Alert Standard Format sensor data over the first external bus. The watchdog timer is coupled to receive a reset input upon a predetermined change in a system state. The watchdog timer is further configured to provide an indication to the microcontroller in response to an expiration of the watchdog timer.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: March 20, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Dale E. Gulick
  • Patent number: 7174483
    Abstract: A method for monitoring a system controlled by a processor utilizes an integrated monitoring unit independent of the processor but integrated together with the processor in an integrated circuit, as well as a watchdog unit for preventing measures that influence the system. The watchdog unit is cyclically reset by the integrated monitoring unit.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: February 6, 2007
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Alwin Becher, Peter Bertelshofer, Roger Pohlmann
  • Patent number: 7162666
    Abstract: Each processor in a multi-processor system is periodically interrupted for preempting the current thread for servicing of a watchdog thread during normal operation. Upon failing to service the watchdog thread over a grace period, a system watchdog initiates an orderly shutdown and reboot of the system. In order to prevent spinlocks from causing fake panics, if the current thread is holding one or more spinlocks when the interrupt occurs, then preemption is deferred until the thread releases the spinlocks. For diagnostic purposes, a count is kept of the number of times that preemption is deferred for each processor during each watchdog grace period.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: January 9, 2007
    Assignee: EMC Corporation
    Inventor: Jean-Pierre Bono
  • Patent number: 7152191
    Abstract: A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: December 19, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Richard E. Kessler, Peter J. Bannon, Kourosh Gharachorloo, Thukalan V. Verghese
  • Patent number: 7117062
    Abstract: A method and an apparatus for characterizing an uncertainty factor relating to processing workpieces. A first processing step is performed upon a workpiece. A first uncertainty factor associated with the first processing step is calculated. A final uncertainty factor associated with an end-of-line parameter relating to the workpiece is calculated based upon the first uncertainty factor. A process control function based upon the final uncertainty factor is performed.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: October 3, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas J. Sonderman, Robert J. Chong, Brian K. Cusson, Alexander J. Pasadyn
  • Patent number: 7107488
    Abstract: A microprocessor 20a controls an electrical load group 12 responsive to content of a non-volatile program memory 25a and operation state of an input sensor group 11. A monitoring control circuit section 30a sequentially transmits a large number of question items with an inquiry packet, and compares response content from the microprocessor 20a with correct answer information to carry out an error determination. The microprocessor 20a diagnoses an interval of receiving an inquiry packet to monitor in reverse the monitoring operation of the monitoring control circuit section 30a. Thus, in an electronic control unit having a microprocessor built-in, a monitoring control circuit is obtained that alternatively executes at regular intervals a part of control programs to carry out operation inspection during operation.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: September 12, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kohji Hashimoto, Katsuya Nakamoto
  • Patent number: 7103738
    Abstract: A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: September 5, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Yoneda, Tsutomu Kamiyoshi, Hiroshi Benno, Shirou Yoshioka, Tsuneo Uenishi
  • Patent number: 7089450
    Abstract: A recovery process for embedded processors monitors other processes in the system. Each process may specify a recovery policy residing in nonvolatile electronic memory that preferably includes a recovery count, a recovery time, and a recovery action. If a process terminates unexpectedly, the recovery process determines whether the process had a corresponding recovery policy. If not, the recovery process does not recover the process. If the process has a corresponding recovery policy, the recovery process determines whether it can recover the process by examining the recovery count and recovery time specified in the recovery policy. If the process can be recovered, the recovery process performs the recovery action specified in the corresponding recovery policy. If the process cannot be recovered, the recovery process resets the system.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gary D. Anderson, Andreas Arnez, Joshua W. Boyer, Gerald G. Kreissig, Paul Edward Movall, Ward R. Nelson
  • Patent number: 7073097
    Abstract: A two-MCU system includes a main-MCU and a sub-MCU. When any one of operating keys is operated, an operation signal is applied to the sub-MCU. Thereupon, the sub-MCU detects the operation of the operating key, and makes a timer start to count a time period. The sub-MCU, when no specified command is received from the main-MCU irrespective of a lapse of a predetermined time period, determines that the main-MCU is being in a hang-up state. Then, the sub-MCU applies a reset signal to a reset circuit thereby to reset the main-MCU, and the two-MCU system returns from the hang-up.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: July 4, 2006
    Assignee: Funai Electric Co., Ltd.
    Inventor: Yasunori Kuwayama
  • Patent number: 7069478
    Abstract: A safety device for a stored-program control includes a controller which exchanges data with a stored-program control and, via a bus controller and a bus system, with the peripheral to be controlled. A memory is provided, in which safety-relevant data of the stored-program control is stored, which is accessible to the controller.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: June 27, 2006
    Assignee: Robert Bosch GmbH
    Inventors: Reiner Wamsser, Hans-Peter Lerch, Jürgen Haeufgloeckner, Joachim Zeller, Gerhard Wolff