Abstract: A semiconductor recording device includes: flash memories including a plurality of physical blocks each including a plurality of pages; an external interface unit which receives data to be recorded on the flash memories; a first ECC generation unit which generates a first ECC code by adding parity data to the data; a data writing unit which records the data based on the first ECC code into the pages in the flash memories; and a page shuffling unit which controls assignment of a symbol of the first ECC code to the pages, and the page shuffling unit controls the assignment of the symbol of the first ECC code such that the symbol of the first ECC code is assigned to pages having at least two page numbers in the physical blocks included in a group.

Abstract: A non-volatile memory device comprises an application code sector of sufficient size to store a first copy of an application code and a second copy of the application code; and a boot sector having a boot loader code embodied therein. The boot loader code is configured to cause a processor to check the integrity of both the first and second copies of the application code; if the first copy is corrupted, overwrite the first copy of the application code with the second copy; and if the second copy is corrupted, overwrite the second copy of the application code with the first copy.

Abstract: A computer-implemented method for improving redundant storage fault tolerance may include 1) identifying a plurality of storage devices storing an encoded set of data, with the encoded set of data including a redundant form of an underlying set of data, 2) determining that a subset of the plurality of storage devices have failed, 3) reconstructing encoded data lost due to the failure of the subset of the plurality of storage devices, and then 4) redundantly storing the reconstructed encoded data on the plurality of storage devices. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A computer readable storage medium, embodying instructions executable by a computer to perform a method, the method including: validating a memory write of data segments using a first number of leaf hashes of a first hash tree, where each of the first number of leaf hashes is associated with one of the data segments of a first block size, generating interior node hashes based on the first number of leaf hashes, where each of the interior node hashes is associated with a second block size, generating a first root hash using the interior node hashes, where the first root hash is associated with a remote procedure call size, transmitting the first root rash and the data segments to a network file system, where the transmission is performed using the remote procedure call size, and validating the transmission of the data segments using the first root hash.

Abstract: An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed.

Abstract: The parallel RS-RAID data storage architecture can aggregate that data and checksums within each cluster into intermediate or partial sums that are transferred or distributed to other clusters. The use of intermediate data symbols, intermediate checksum symbols, cluster configuration information on the assignment of data storage devices to clusters and the operational status of data storage devices, and the like, can reduce the computational burden and latency for the error correction calculations while increasing the scalability and throughput of the parallel RS-RAID distributed data storage architecture.

Abstract: A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards.

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract: Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area.

Abstract: A method for processing a write instruction for writing data to a database stored on a logical device includes obtaining first and second addresses that specify the location of the data in respective first and second address spaces. A third address corresponding to an expected location of the data record in the first address space is then calculated. On the basis of a comparison between the first address and the third address, a determination is made as to whether to execute the write instruction.

Abstract: The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests. In accordance with an aspect of the invention, there is provided a method for verifying a priority of a winning service request node (SRN) established in an arbitration between a plurality of service request nodes (SRNs) performed by an interrupt controller, the method comprising: storing the priority of the winning SRN in the interrupt controller; encoding the priority of the winning SRN, wherein the encoding allows for error detection; transmitting the encoded priority from the winning SRN to the interrupt controller; and verifying the priority of the winning SRN by comparing the encoded priority transmitted by the winning SRN with the priority of the winning SRN established in the arbitration and stored in the interrupt controller.

Abstract: A method for transmitting data from a network to a user equipment in a wireless communication system is provided. The network adds an error detection code, generated using a first identifier allocated to the user equipment, to scheduling information for data to be transmitted to the user equipment and transmits the scheduling information to which the error detection code has been added to the user equipment. The network also adds an error detection code, generated using a second identifier allocated to the user equipment, to the data to be transmitted to the user equipment and transmits the data to which the error detection code has been added to the user equipment.

Abstract: An encoder structure for an error correcting code with arbitrary parity positions is presented. The invention is effective for all error correcting codes whose parity check matrix is of the Vandermonde type. In contrast to conventional encoder circuits, the parity symbols produced by this encoder are not restricted to form a block of consecutive parity symbols at the beginning or at the end of a codeword, but may be spread arbitrarily within the codeword. A general structure of the parity check matrix for such a code is found by exploiting the special Vandermonde structure of matrices. From this general parity check matrix, an expression for the evaluation of the parity symbols in terms of a polynomial with limited degree is derived. An efficient hardware implementation of the proposed encoder is suggested.

Abstract: A backup method for a computer system network avoids generating hashes from data that may be inaccurate due to network errors affords verification of source data written to backup media includes reading at a network client a portion of the source data from a source storage volume and generating a hash of the source data at the client. The source data and hash are transmitted to a backup server and written to the backup media. The hash is written to the backup media is associated with the backup data corresponding to the source data from which the hash was generated. Verification of the backup data is performed by reading the backup data from the backup media, generating a hash from the backup data read, and comparing that hash with the hash originally stored on the backup media.

Abstract: A data reading method suitable for a flash memory storage system having a flash memory is provided, wherein the flash memory is substantially divided into a plurality of blocks and these blocks are grouped into at least a data area and a spare area. The data reading method includes: respectively determining whether the blocks in the data area are frequently read blocks; allocating a buffer storage area corresponding to the frequently read block and copying data stored in the frequently read block to the buffer storage area; and reading the data from the buffer storage area corresponding to the frequently read block when the data stored in the frequently read block is to be read. As described above, data loss caused by read disturb can be effectively prevented.

Abstract: A method performed by an I/O unit connected to another I/O unit in a network device. The method includes receiving a packet; segmenting the packet into a group of data blocks; storing the group of data blocks in a data memory; generating data protection information for a data block of the group of data blocks; creating a control block for the data block; storing, in a control memory, a group of data items for the control block, the group of data items including information associated with a location, of the data block, within the data memory and the data protection information for the data block; performing a data integrity check on the data block, using the data protection information, to determine whether the data block contains a data error; and outputting the data block when the data integrity check indicates that the data block does not contain a data error.

Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

Abstract: The method begins with a processing unit receiving an encoded slice for storage. The method continues with the processing unit determining whether to store the encoded slice in one of a first set of memory devices or in one of a second set of memory devices based on metadata associated with the encoded slice, wherein the first set of memory devices are continually active and the second set of memory devices are selectively active. The method continues with the processing unit stores the encoded slice in the one of the second set of memory devices when the encoded slice is to be stored in the one of the second set of memory devices. The method continues with the processing unit de-activating the one of the second set of memory devices, in accordance with a deactivation protocol, after storing the encoded slice.

Abstract: To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc.

Abstract: Systems and methods are provided for selecting transmission parameters used in the transmission of a communication signal in a wireless communications device. In one embodiment, a computer-implemented method for determining a convolutional code constraint length and/or a modulation type is provided. The method includes obtaining a channel condition for a channel associated with transmission of the communication signal. Based at least in part on the channel condition, the method includes selecting a convolutional code constraint length and/or a modulation type for transmitting the communications signal. In some embodiments, the method also includes selecting a data rate for transmitting the communications signal.

Abstract: A solid state disk device comprises a plurality of nonvolatile memories and a controller. The plurality of nonvolatile memories are electrically connected to a plurality of channels, respectively. The controller controls storing, erasing and reading operations of the nonvolatile memories. The controller divides input data into a number of units corresponding to a number of the plurality of channels and stores the divided input data in the nonvolatile memories through the plurality of channels.

Abstract: The present invention is directed to a memory device with protection capability and a method of accessing data therein. A spreader encrypts input user data according to an entered password, and the encrypted data is then stored in a storage area. A despreader performs reverse process of the spreader on the stored data according to the entered password.

Abstract: The parallel RS-RAID data storage architecture can aggregate that data and checksums within each cluster into intermediate or partial sums that are transferred or distributed to other clusters. The use of intermediate data symbols, intermediate checksum symbols, cluster configuration information on the assignment of data storage devices to clusters and the operational status of data storage devices, and the like, can reduce the computational burden and latency for the error correction calculations while increasing the scalability and throughput of the parallel RS-RAID distributed data storage architecture.

Abstract: A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.

Abstract: A communication device for transmitting data to a communication partner device includes a transmitter for transmitting transmit data to the communication partner device, a determiner for determining a check value from the transmit data in accordance with a determination specification, a receiver for receiving a verification value from the communication partner device, and a checker configured to compare the check value with the verification value and to provide a fault indication signal as a function of the comparison.

Abstract: A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.

Abstract: A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.

Abstract: An integrated circuit includes a memory array and an error correction code (ECC) circuit configured to provide a first signal indicating whether data read from the memory array has been corrected by the ECC circuit. The integrated circuit includes a mimic circuit configured to provide a second signal indicating whether the first signal is valid and a counter configured to increment in response to the second signal indicating the first signal is valid and the first signal indicating an error.

Abstract: A data recovery circuit for recovering data from a parity error without entirely rewriting the data. A write circuit is connected to memory regions including an actual data region and a copy region. A first parity generation circuit writes actual data with even parity to the actual data region. A second parity generation circuit writes backup data of the actual data with odd parity to the copy region. A read circuit reads data from the actual data region and the copy region. An even parity checker detects a parity error in the actual data based on the data read from the actual data region. An odd parity checker checks whether the data read from the copy region is backup data.

Abstract: Apparatus and associated method that stores first metadata only at the same addressable storage location of a computer readable medium as that where associated first user data is stored, and afterward satisfies a read request for the first user data by retrieving the first user data from the addressable location of the computer readable medium where the first metadata is stored if the first metadata has a first value, and by reconstructing the first user data from other metadata stored at another addressable location of the computer readable medium than where the first metadata is stored if the first metadata has a second value.

Abstract: A method to receive a signal transmitted over a transmission link comprising coded channels, the method comprising: —equalization operations (110-116) to compensate for signal distortion introduced by the transmission link in a signal burst, and—block decoding operations (120-126) to perform channel decoding operation from the equalized signal bursts. If one of the block decoding operations has not been executed before a predetermined time limit, the method comprises at least one step (146) of discarding one of the next burst equalization operations.

Abstract: A method, transceiver, and computer program storage product transfer data over fiber between a first transceiver and a second transceiver. The second transceiver is determined to support a high integrity cyclic redundancy check associated with substantially an entire data set in a Fiber Channel Protocol exchange between the first transceiver and the second transceiver. A last data frame in a plurality of data frames is formatted for communication to the second transceiver during the Fiber Channel Protocol exchange. The last data frame includes a plurality of data and at least one cyclic redundancy check field associated with the plurality data and at least one additional cyclic redundancy check field associated with the plurality of data frames.

Abstract: A method and a system for template-based code generation. The method easily renders executable code using reusable customizable templates. The method further checks the templates for syntax errors prior to use. The system provides a memory and a processor for implementing template-based code generation.

Abstract: A hard disk drive with a disk that has a plurality of data bits. The drive includes a circuit that reads each data bit n times and selects a value for the bit based on a reliability factor. The circuit may select a bit based at least in part on the most frequent occurrence of one of a plurality of values. For example, if more 0s occurred than 1s the bit would be set to 0. The reliability factor may be a ratio of the occurrence of 0s to the occurrence of 1s. A bit can be not selected or deselected if the reliability factor exceeds a threshold value.

Abstract: The invention is directed to monitoring execution of software threads, particularly by detecting a lockup or stall in execution of a software thread and initiating a remedial action in response. Advantageously, some embodiments of the invention automatically detect a lockup or stall in execution of a software thread by periodically sampling information corresponding to the thread, and, in accordance with a determination made using the information, initiate an attempt to recover from such a condition in execution without the need for manual intervention.

Abstract: Embodiments of the present invention help improve the process for updating parities accompanied by the writing process. According to one embodiment, a host controller transmits a write command and new data to a hard disk drive (HDD). The HDD reads old data at a region where the new data are to be written. The HDD then XORs the new data and the old data to generate a pseudo-parity. The HDD sets the pseudo-parity in a data frame addressed to both of a horizontal parity disk drive HDD and a diagonal parity disk drive HDD and transmits it. The horizontal parity disk drive HDD and the diagonal parity disk drive HDD update the parities using the pseudo-parity.

Abstract: A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the memory device to a first location of a memory of the memory device is stopped. First data that remains in the register after the program failure is detected is transferred to a second location of the memory. At the second location of the memory, the first data is combined with second data from the first location of the memory that remains in the first location of the memory after the program failure is detected to reconstruct third data that was originally intended to be programmed in the first location before the program failure was detected.

Abstract: This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.

Abstract: An information processing device, for executing content reproduction processing from an information recording medium, includes a security information processing unit for determining output messages based on security check information in a content reproduction sequence, and outputting a message output command accompanied by selection information of the output message to a user interface processing unit, and a user information processing unit for obtaining message information based on the selection information input from said security information processing unit and outputting to a display unit.

Abstract: Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an error recovery device at an end of the chain. In one configuration shown, the serial chain of memory devices includes a chain of devices where each device is a stacked die memory device. Methods are described that show using the error recovery device in write operations and data recovery operations.

Abstract: Code, data, and/or other information types, may be isolated from one another and stored in distinct regions within the memory array of a nonvolatile memory. The distinct regions in memory may have corresponding read/write interfaces that are optimized for each information type.

Abstract: A backup method for a computer system network avoids generating hashes from data that may be inaccurate due to network errors affords verification of source data written to backup media includes reading at a network client a portion of the source data from a source storage volume and generating a hash of the source data at the client. The source data and hash are transmitted to a backup server and written to the backup media. The hash is written to the backup media is associated with the backup data corresponding to the source data from which the hash was generated. Verification of the backup data is performed by reading the backup data from the backup media, generating a hash from the backup data read, and comparing that hash with the hash originally stored on the backup media.

Abstract: A method of facilitating reliably accessing flash memory is provided. During the write-in process, the present invention utilizes the steps of coding write-in data to generate extra data, and then generating the first error correction code by performing an error-correcting operation on the write-in data and the extra data. Finally, store the N write-in data and the generated K extra data into the data area and the first ECC into the spare area. During read process, the present invention utilizes the steps of reading data from the data area of the target flash-memory page to generate the second ECC, counting with the counter a number of bit differences between the first ECC and the second ECC, and selecting M data from the N write-in data and the K extra data as decoding factors to retrieve the N write-in data. The higher the counter values, the lower the likelihood the corresponding bit is selected to be retrieved.

Abstract: A system and method for logging and storing failure analysis information on disk drive so that the information is readily and reliably available to vendor customer service and other interested parties is provided. The information, in an illustrative embodiment, is stored on a nonvolatile (flash) random access memory (RAM), found generally in most types of disk drives for storage of updateable disk drive firmware. A known location of limited size is defined in the flash RAM, to form a scratchpad. This scratchpad is a blank area of known addresses, formed during the original firmware download onto the memory, and which is itself free of firmware code. This scratchpad is sufficient in size to write a series of failure codes in a non-erasable list as failures/errors (and user/administrator attempts to unfail the disk) are logged.

Abstract: A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.

Abstract: An apparatus and method are provided for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system. The apparatus includes (a) a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache, (b) a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines, and (c) in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline.

Abstract: A method of verifying programming of an integrated circuit card includes transferring program data to a page buffer of a non-volatile memory, copying the program data to a buffer memory, calculating a first checksum value with respect to program data in the buffer memory, updating the program data in the buffer memory by copying the program data of the page buffer to the buffer memory, calculating a second checksum value with respect to updated program data in the buffer memory, comparing the first checksum value and the second checksum value, and determining, based on the comparison result, whether the program data of the page buffer is tampered.

Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.

Abstract: An information processing device is provided. The information processing device includes a frame acquiring unit for acquiring a frame using a signal transmitted via a network, a computing unit for computing a check sequence on the basis of data included in the frame, a checking unit for checking whether the frame is corrupted by checking whether the check sequence coincides with a check sequence added to the frame in advance, a storing unit for storing a table that is a list of check sequences computed in advance on the basis of a plurality of pieces of data representing addresses of frames to be received by the information processing device, and a determining unit for determining whether the frame should be received by determining whether a check sequence computed by the computing unit on the basis of data representing a destination address of the frame coincides with any one of the check sequences included in the table.

Abstract: Provided are a method, system and article of manufacture for verifying a record as part of an operation to modify the record. A search request is received to determine whether a record matches a value. A first component executes the search request to determine if the record matches the value. The first component sends a verify request to a second component that did not execute the search request to execute the search request to determine whether the record matches the value. A result of the first and second components executing the search request is logged.