Abstract: The present disclosure includes systems, apparatuses, and methods related to memory channel controller operation. For example, a data type associated with an access request may be determined. The access request may be executed by utilizing, responsive to determining the access request is associated with a first data type, a first memory channel controller coupled to a first memory device to access a first memory address range, associated with the first data type, allocated to the first memory device. The access request may be executed by utilizing, responsive to determining the access request is associated with a second data type, the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range, associated with the second data type, allocated among the first memory device and the second memory device.

Abstract: A method includes memory fencing in memory components of a memory sub-system and receiving a first number of commands and a second number of command for execution on a memory sub-system, receiving a memory fencing command associated with the first number of commands and the second number of commands, and executing at least one of the first number of commands before executing at least one of the second number of commands in response to receiving the memory fencing command. The method further includes executing the at least one of the first number of commands by moving data from a first location in the memory subsystem to a second location in the memory sub-system and executing the at least one of the second number of commands by reading data from the second location in the memory sub-system and sending the data to a host system.

Abstract: A read/write method includes: applying a read command to a memory device, the read command pointing to address information, reading to-be-read data from a storage cell corresponding to the address information to which the read command points, and if an error occurs in the to-be-read data, storing the address information to which the read command points in a preset storage space. The read/write operation is not performed on the address information stored in the preset storage space when the user executes the read or write operation on the memory device, which avoids a data error or data loss and greatly improves the reliability and prolongs the service life of the memory device.

Abstract: Methods and apparatus for using characterized devices such as memories. In one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. The characterized memories can be used in conjunction with a solution density function to optimize memory searching. In one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (POW). The results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. In one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. Various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).

Abstract: A method for error correction of logical pages of an erase block of a solid state drive (SSD) memory, the method may include determining an erase block score of the erase block, wherein the calculating is based on a program erase (PE) cycle of the erase block and one or more erase block error correction parameter; determining, based on (a) the erase block score, and (b) a mapping between the erase block score and one or more page error correction parameters for each page type out of multiple pages types, the one or more page error correction parameter for each page type; and allocating, within each page of the erase block, an overprovisioning space and an error correction space, based on at least one page error correction parameter related to a page type of the page.

Abstract: A system that implements a data storage service may store data on behalf of storage service clients. The system may maintain data in multiple replicas of various partitions that are stored on respective computing nodes in the system. The system may employ a single master failover protocol, usable when a replica attempts to become the master replica for a replica group of which it is a member. Attempting to become the master replica may include acquiring a lock associated with the replica group, and gathering state information from the other replicas in the group. The state information may indicate whether another replica supports the attempt (in which case it is included in a failover quorum) or stores more recent data or metadata than the replica attempting to become the master (in which case synchronization may be required). If the failover quorum includes enough replicas, the replica may become the master.

Abstract: A playback device includes a port configured to receive content from an external memory device, a device memory residing in the device, and a controller programmed to execute instructions that cause the controller to read a read data pattern from the defined region in the external memory device and determine if the read data pattern correlates to an expected data pattern to a predetermined level, wherein the expected data pattern is derived at least in part from a defect map of the defined region.

Abstract: A memory-control logic, disposed in a memory circuit, is provided. The memory circuit includes a memory-cell array that is divided into a plurality of regions that include a damaged region. The memory-control logic includes a one-time-programmable (OTP) memory array, an array-control circuit, and an address-redirecting circuit. The array-control circuit programs a memory-size type of the memory-cell array, a region-failure flag corresponding to each region, and a redirecting mapping table corresponding to each region in the OTP memory array. The array-control circuit programs the redirecting mapping table corresponding to each region according to the memory-size type to direct the redirecting mapping table corresponding to each damaged region to non-repetitive good regions.

Abstract: This disclosure describes techniques for providing a distributed scalable architecture for Network Address Translation (NAT) systems with high availability and mitigations for flow breakage during failover events. The NAT servers may include functionality to serve as fast-path servers and/or slow-path servers. A fast-path server may include a NAT worker that includes a cache of NAT mappings to perform stateful network address translation and to forward packets with minimal latency. A slow-path server may include a mapping server that creates new NAT mappings, depreciates old ones, and answers NAT worker state requests. The NAT system may use virtual mapping servers (VMSs) running on primary physical servers with state duplicated VMSs on different physical failover servers.

Abstract: A system and apparatus for secure NVM format by pre-erase is disclosed. According to certain embodiments when an NVM does into idle mode, one or more free blocks are serially popped from a free block heap. The free block is then physically erased in an SLC mode, and then pushed to a pre-erase heap. The process is performed in both SLC and TLC partitions, in the TLC partition the block becomes hybrid SLC (HSLC). This process increases a program erase count (PEC) value of the block, maintaining device longevity. When there is a need to use a new block, it is popped from the pre-erase heap. In some cases where there is a need to use a TLC block instead of an HSLC block, an erase operation is used that converts the block from HSLC to TLC, and does not increase a PEC value for the block.

Abstract: A data processing method includes in response to determining that data corresponding to received data to be written exists, determining a first data identifier of the data corresponding to the data to be written, where the first data identifier is used to obtain a first storage area corresponding to the data, generating a second data identifier of the data to be written, writing the data to be written into the second storage area, in response to receiving a data rollback instruction, obtaining a target data identifier corresponding to the data rollback instruction, and determining a target storage area based on the target data identifier to obtain rollback data from the target storage area. The second data identifier is different from the first data identifier, and the second data identifier corresponds to a second storage area different from the first storage area.

Abstract: Systems, methods, and software are disclosed herein that enhance the management of storage sub-systems with solid-state media. In various implementations, a method comprises collecting time series data indicative of an accumulation of bad blocks within dies on one or more solid-state drives. For one or more of the dies, the method includes identifying one or more behaviors of a die based at least on a portion of the time series data associated with the die and determining to retire the die based at least on one or more identified behaviors of the die. One or more of the dies on the one or more solid-state drives may then be retired accordingly.

Abstract: A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.

Abstract: Failure information associated with a plurality of blocks of a solid-state storage device of a plurality of solid-state storage devices is received. One or more blocks of the plurality of blocks storing uncorrectable data are identified based on the received failure information. A partial deallocation of the one or more blocks of the plurality of blocks is issued, the partial deallocation indicating that the one or more blocks store uncorrectable data. A remedial action associated with the one or more blocks of the plurality of blocks is performed.

Abstract: Aspects of a storage device including at least one die and a controller are provided that allow superblock formation using surplus block pairs when bad blocks occur. After the controller forms a superblock including a first block in a first plane of the die and a second block in a second plane of the die, the controller identifies the first block as a bad block and switches the second block into a surplus state (or vice-versa). The controller then forms a new superblock from blocks in a spare pool. When the number of blocks is equal to a superblock threshold, the controller attempts to pair the surplus block with another surplus block from the opposite plane according to a die sequence. If the attempt to pair is successful, the controller adds the pair to the spare pool; otherwise, the surplus block is not added to the spare pool.

Abstract: Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.

Abstract: An improved solid state drive (SSD). The SSD comprising a plurality of non-volatile memory dies, each configured to store at least one block of data associated with one of a plurality of superblocks each containing a plurality of blocks; a volatile memory; and a memory controller. The memory controller configured to store a bit map associated with a first superblock of the plurality of superblocks in the volatile memory, wherein the bit map is configured to indicate whether each of the plurality of blocks is a replacement block, store a block address list in the volatile memory, the block address list is configured to store an address of one or more replacement blocks, and store a replacement block index in the volatile memory associated with the first superblock of the plurality of superblocks, the replacement block index corresponding to the location of an address of a first replacement block of the first superblock in the block address list.

Abstract: An information processing apparatus includes a storage unit configured to store at least a first boot program and a second boot program corresponding to the first boot program, a controller configured to read and execute a program, detect, in accordance with occurrence of a read error at reading of the first boot program, an address of a storage area storing a program in which the read error has occurred in the first boot program, and specify, from an address of a storage area storing the second boot program, an address corresponding to the detected address. The controller reads and executes the second boot program stored in the specified address.

Abstract: In some embodiments, the present disclosure provides an access controlling network architecture may include: a processor in communication with a non-transitory computer readable medium storing application program instructions that when executed, cause the processor to: generate an expected access control digital key for authenticating a computing device that is operationally linked to access-restricted digital resource for accessing; record the expected access control digital key in a computer memory associated with the access controlling platform; cause to display the expected access control digital key at the computing device; receive a mobile originating communication, having: a particular access control digital key and an identity linked to the computing device; perform a confirmation of the particular access control digital key with the expected access control digital key; transmit, when the confirmation is successful, an access authentication indicator; configured to cause to unlock the at least one acc

Abstract: A method, computer program product, and computing system for dividing a plurality of volumes replicated across a pair of storage systems into one or more consistency groups. A polarization state may be defined for each consistency group. An input-output (IO) failure associated with at least one consistency group may be detected. At least a portion of the at least one consistency group may be polarized based upon, at least in part, the polarization state defined for the at least one consistency group.

Abstract: Embodiments of the present disclosure provide a memory system and an operating method thereof. A memory system includes a memory device and a memory controller. The memory controller is configured to create a bad memory area replacement table including state information of a bad memory area among a plurality of memory areas, add the state information of one or more runtime bad memory areas to the bad memory area replacement table when one or more runtime bad memory areas occur, and remap, based on the bad memory area replacement table, a bad sub-area included in a target memory area to a normal sub-area included in one of remaining bad memory areas other than the target bad memory area among the bad memory areas added to the bad memory area replacement table.

Abstract: For migrating data to a remote data repository based on the security protocol capabilities of the remote data repository, a storage module identifies a security profile of a file residing in an on-premise data repository, where the security profile comprises security protocol requirements, matches the identified security profile with an entry in a list of one or more remote data repository providers, each entry comprising a security protocol capability of a corresponding remote data repository provider, and migrates, in response to finding a match of the identified security profile and the identified security protocol capability, the file to the matched remote data repository provider.

Abstract: Embodiments herein describe error interceptors disposed along a bus that communicatively couples first and second circuits for redirecting in-band errors. That is, the error interceptors can block (or mask) in-band errors so they are not forwarded along the bus. Further, the error interceptors can redirect those errors such that they are converted into out-of-band errors. Moreover, the user can select which error interceptors to activate (e.g., block and redirect the errors) and which to deactivate (e.g., permit the in-band errors to pass). In this manner, the user can control which circuits receive in-band errors and which do not based on whether those circuits can handle the in-band errors.

Abstract: The disclosed systems and methods enable an application to start operating and servicing users soon after and during the course of its backup data being restored, no matter how long the restore may take. This is referred to as “instant application recovery” in view of the fact that the application may be put back in service soon after the restore operation begins. Any primary data generated by the application during “instant application recovery” is not only retained, but is efficiently updated into restored data. An enhanced data agent and an associated pseudo-storage-device driver, which execute on the same client computing device as the application, enable the application to operate substantially concurrently with a full restore of backed up data.

Abstract: A method includes storing, on immutable memory, a first separately compiled portion of an OS, the first separately compiled portion having a first OS section including a patch hook having a patch lookup table address and associated with a first index value, and a second OS section including the patch hook associated with a second index value, storing, on mutable memory, a second separately compiled portion of the operating system, the second separately compiled portion including a patch lookup table at the patch lookup table address. The first and the second separately compiled portion are linked to form the OS. A determination is made that a change is required in the first OS section of the first separately compiled portion, resulting in updating the second separately compiled portion to include a first patch for the first OS section at a first patch address, and updating the patch lookup table.

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

Abstract: Techniques are disclosed relating to a method that includes executing, by a processor of a computer system, one or more processes. The processor may use a peripheral device coupled to the computer system, wherein the peripheral device utilizes a particular version of a driver. A sideband processor included in the computer system may receive, via a network, instructions for an updated version of the driver to replace the particular version of the driver. The sideband processor may cause the processor to pause use of the peripheral device. While the processor executes the one or more processes, the sideband processor may send a series of commands to install the instructions for the updated version of the driver. The sideband processor may also notify the processor that the peripheral device is available for use.

Abstract: A storage device includes an integrity checking module checking integrity of data stored in a first host memory buffer (HMB) address of an HMB in a host coupled to the storage device, and an HMB mapping module mapping, if the integrity checking module determines the data as corrupted, the first HMB address to a second address.

Abstract: A memory system includes a status information register configured for checking threshold voltages of select transistors included in memory blocks, storing status information on a check result, and outputting a code based on the status information, a status monitor configured to receive the code from the status information register, determine a number of select transistors that have shifted according to the code, and output status signal based on the number of the select transistors that have shifted, and a central processing unit configured for outputting a setup command set for setting parameters of the memory blocks, outputting a re-program command set for re-programming the select transistors, or outputting a bad block address for processing the memory blocks as bad blocks in response to the status signals.

Abstract: A method includes reserving memory capacity in a first memory device as patch memory region for backing faulted memory, receiving a memory error indication indicating an uncorrectable error in a faulted segment in a second memory device and, in response to the memory error indication, associating in a remapping table the faulted segment with a patch segment in the patch memory region. The faulted segment is smaller than a memory page size of the second memory device. The method also includes, in response to receiving a memory access request directed to the faulted memory segment, servicing the memory access request from the patch segment by querying the remapping table to determine a patch segment address corresponding to a requested memory address, where the patch segment address identifies the location of the patch segment, and based on the patch segment address, performing the requested memory access at the patch segment.

Abstract: Systems and methods for managing content in a flash memory. Systems and methods for implementing hash tables in a flash memory are disclosed. A hash table may include a flat array or an array of buckets that are each associated with a linked list. Adding or removing entries from the hash table or from the linked list are achieved by performing an overwrite operation where possible to pointers affected by the table operation.

Abstract: A storage system comprises a plurality of storage devices, and is configured to establish a redundant array of independent disks (RAID) arrangement comprising a plurality of stripes, with each of the plurality of stripes comprising a plurality of blocks, the blocks being distributed across multiple ones of the storage devices. In conjunction with establishment of the RAID arrangement, the storage system is further configured, for each of the plurality of stripes, to designate a particular one of the storage devices as a spare storage device for that stripe, and for each of the storage devices, to determine numbers of the stripes for which that storage device is designated as a spare device for respective ones of the other storage devices. A particular number of spare blocks is reserved for each of the storage devices based at least in part on its determined numbers of the stripes.

Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. The computing devices may push a point in time to a backend for a distributed storage system.

Abstract: Embodiments may include apparatus, systems, and methods associated with an Enhanced Serial Peripheral Interface (eSPI) channel interface to couple to a data bus to link an eSPI primary device to an eSPI secondary device. In embodiments, the eSPI primary device includes an eSPI device controller and is coupled to the channel interface and transmits a notification of a crash event, e.g., a catastrophic error (CATERR), via packet-based signaling, such as a virtual wire (VW) over the data bus to allow the eSPI primary device to transmit the notification of the crash event without allocation of a dedicated wire signal for the notification between the eSPI primary device and the eSPI secondary device. Other embodiments may be described and/or claimed.

Abstract: Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

Abstract: According to one embodiment, a memory system includes a first memory, an interface circuit, and a processor. The interface circuit is configured to receive a first request from an external device. The processor is configured to select a mode among a plurality of modes in response to the first request, and perform, on data read from the first memory, error correction of the selected mode.

Abstract: Resource provisioning to a process in a distributed computing system, such as a cloud computing system. An instruction to provision a resource is received. Portions of the resource are provisioned to the process as they become available, and prior to all portions becoming available, based on determining that the provisioning speed is greater than or equal to the use speed for the resource. If the use speed is faster, it may be actively slowed down.

Abstract: According to one embodiment, a magnetic disk device includes a plurality of disks including a first area to which data is randomly written in normal recording and to which an LBA is added, and a second area to which data is written in shingled recording to write a plurality of tracks overlaid in a radial direction and to which an LBA is added, a plurality of heads, and a controller which writes data to the first area in the normal recording, writes data to the second area in the shingled recording, and changes the first area in accordance with a first recording capacity of a first recording surface in each of the disks, which corresponds to a first head of the heads, when the first head is inhibited from being used.

Abstract: The application is directed to techniques, devices, and systems for updating files. For example, a remote system may store first data representing a first version of a file and second data representing a second version of the file. The remote system may then determine that a first portion of the first data corresponds to a first portion of the second data. Based at least in part on the determination, the remote system may identify a second portion of the first data using the first portion of the first data and identify a second portion of the second data using the first portion of the second data. The remote system may then generate third data representing a difference between the second portion of the second data and the second portion of the first data. Additionally, the remote system may store the third data in association with the file.

Abstract: An apparatus may include a circuit configured to initialize a read operation to read one or more requested data segments of a respective data unit having a plurality of data segments. Based on a number of failed data segments of the requested data segments and an erasure capability of an outer code error correction scheme, the circuit may perform erasure recovery to recover the failed data segments. Based on the number of failed data segments, the erasure capability of the outer code error correction scheme, and a threshold value, the circuit may perform iterative outer code recovery to recover the failed data segments.

Abstract: A storage system is configured to establish a redundant array of independent disks (RAID) arrangement comprising a plurality of stripes each having multiple portions distributed across multiple storage devices. The storage system is also configured to detect a failure of at least one of the storage devices, and responsive to the detected failure, to determine for each of two or more remaining ones of the storage devices a number of stripe portions, stored on that storage device, that are part of stripes impacted by the detected failure. The storage system is further configured to prioritize a particular one of the remaining storage devices for rebuilding of its stripe portions that are part of the impacted stripes, based at least in part on the determined numbers of stripe portions. The storage system illustratively balances the rebuilding of the stripe portions of the impacted stripes across the remaining storage devices.

Abstract: A method for injecting specific errors of both correctable and non-correctable types into a PCIE device for testing purposes during fabrication stage constructs an error injecting platform based on received target information. The platform includes a control system and at least one testing system. Disabling a security boot in the connected testing system and obtaining information of the specified driver. The obtained information comprises objects to be tested according to selection, each object having a bus address and a PCIE port value. The object under test is controlled to inject a specified error, the injection and result of injection being reported by the processor and analyzed.

Abstract: A computer-implemented method according to one embodiment includes determining a location within a file system that is potentially vulnerable to hardware failures, and injecting one or more simulated hardware failures into the determined location within the file system. The method further includes determining whether the file system was damaged as a result of injecting the simulated hardware failure(s). In response to determining that the injection of the simulated hardware failure(s) resulted in damage to the file system, it is determined whether the damage is repairable. Based on whether the file system was damaged as a result of injecting the simulated hardware failure(s) and/or based on whether or not the damage is determined to be repairable, a tolerance-to-storage-failure score is assigned to the file system.

Abstract: A machine learning module receives inputs comprising attributes of a storage controller, where the attributes affect failures that occur in the storage controller. In response to a failure occurring in the storage controller, a plurality of output values corresponding to a plurality of recovery mechanisms to recover from the failure in the storage controller are generated via forward propagation through a plurality of layers of the machine learning module. A margin of error is calculated based on comparing the generated output values to expected output values corresponding to the plurality of recovery mechanisms, where the expected output values are generated from an indication of a correct recovery mechanism for the failure. An adjustment is made of weights of links that interconnect nodes of the plurality of layers via back propagation to reduce the margin of error, to improve a determination of a recovery mechanism for the failure.

Abstract: A data storage device includes a memory array for storing data; a host interface for providing an interface with a host computer running an application; a central control unit configured to receive a command in a submission queue from the application and initiate a search process in response to a search query command; a preprocessor configured to reformat data contained in the search query command and generate a reformatted data; and one or more data processing units configured to extract one or more features from the reformatted data and perform a data operation on the data stored in the memory array in response to the search query command and return matching data from the data stored in the memory array to the application via the host interface.

Abstract: A memory system includes: a nonvolatile memory device including a plurality of memory blocks and spare blocks; and a memory controller configured to control the nonvolatile memory device. The nonvolatile memory device may store spare information to any one block of the memory blocks or the spare blocks. When a bad block is detected from the memory blocks, the nonvolatile memory device replaces the bad block with any one of the spare blocks according to the spare information.

Abstract: Non-volatile memory block management. A method according to one embodiment includes calculating an error count margin threshold for each of the at least some non-volatile memory blocks of a plurality of non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded.

Abstract: Devices and methods for using nonvolatile memory and volatile memory are described. As volatile memory cells may not retain information absent power, nonvolatile memory cells (e.g., antifuses, phase-change memory cells, ferroelectric memory cells) may store various information related to operating conditions of the volatile memory cells. For example, an operating condition (e.g., voltage, temperature, a timing parameter for command, or refresh rate) of volatile memory cells may exceed an operating limit causing the volatile memory cells to fail. An indication of the operating condition of the volatile memory cells may be stored in nonvolatile memory cells to be retrieved later. The indication stored in the nonvolatile memory cells may facilitate analytical processes to identify root-causes that may have caused the volatile memory cells to fail. Nonvolatile memory cells may be configured to indicate whether such an operating condition exists and provide specific information about the operating condition.

Abstract: Methods, systems, and devices for memory read masking are described. In some cases, a portion of a memory device, such as a portion of a memory array, may be disabled. During a testing operation, a command for accessing one or more memory cells of the disabled portion may be received, and the associated memory cells may be attempted to be accessed. Based on attempting to access the disabled memory cells, a logic state of the disabled cells may be masked. Outputting the masked value may indicate (e.g., to a testing device) that the disabled cells pass the test (e.g., that the memory cells are valid), which may allow for the enabled memory cells and the disabled memory cells of the memory device to be tested using a single test mode.