Abstract: The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.

Abstract: Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily.

Abstract: In one embodiment, a method includes selecting a subset of rays from a set of all rays to use in an error calculation for a constrained conjugate gradient minimization problem, calculating an approximate error using the subset of rays, and calculating a minimum in a conjugate gradient direction based on the approximate error. In another embodiment, a system includes a processor for executing logic, logic for selecting a subset of rays from a set of all rays to use in an error calculation for a constrained conjugate gradient minimization problem, logic for calculating an approximate error using the subset of rays, and logic for calculating a minimum in a conjugate gradient direction based on the approximate error. In other embodiments, computer program products, methods, and systems are described capable of using approximate error in constrained conjugate gradient minimization problems.

Abstract: This disclosure relates to method, device and system for detecting errors in a communication system. A signal is received from a transmitter at a receiver wherein the signal includes a data portion and a result of a hash function. The hash function is computed in part from a transmitter identification code. The receiver determines if the result of the hash function matches both the data portion and the transmitter identification code. The receiver discards the signal if the result of the hash function does not match both the data portion and the transmitter identification code of the transmitter.

Abstract: Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses this dynamic characterization of the channel fidelity to adapt the receiver processing and to affect an improvement in the performance of the receiver. For example, in this embodiment, the method increases the accuracy of the estimation of the transmitted information, or similarly, increases the probability of making the correct estimates of the transmitted information, even in the presence of temporary severe levels of impairment. The channel fidelity history may also be stored and catalogued for use in, for example, future optimization of the transmit waveform.

Abstract: Methods for detecting and correcting data errors in an RF data link include identifying valid data frames and corrupted data frames by measuring a data corruption level for each transmitted data frame, comparing the measured data corruption level for each corrupted data frame to a data corruption threshold, reconstructing the corrupted data frames having a data corruption level below the data corruption threshold, reconstructing the data block using data from valid and reconstructed data frames, and/or verifying the data in the reconstructed data block.

Abstract: System and method for error handling in a graphical program. An error handling structure is displayed in a graphical program. The error handling structure includes a first frame configured to contain graphical program code for which error handling is to be provided. At least a portion of the graphical program is included in the first frame in response to user input specifying the at least a portion of the graphical program. During execution of the graphical program, the error handling structure aborts execution of the at least a portion of the graphical program in the first frame in response to detection of an unhandled error in the at least a portion of the graphical program in the first frame and continues execution of the graphical program.

Abstract: In measuring a certain time lag between generations of two pulse signals, a time lag measuring device prevents errors in measurement results even with an error in two reference signals for measuring the time lag. The device measures a time lag between a start signal M1 and a stop signal M2 and includes a reference signal generating section 41 generating two reference signals S1, S2 having a phase difference ?/2, and an amplitude detecting section 42 detects amplitudes A11, A12 and A21, A22 of the reference signals S1, S2 at generation timings for the start signal M1 and the stop signal M2, a phase difference detecting section 43 calculating a phase _ of the reference signals S according to each set of the amplitudes (A11, A12) and (A21, A22), and a correcting section 46 correcting the calculated phase using correction data for error correction in the reference signals S1, S2.

Abstract: A distributed storage network receives data that is to be transmitted. The data is processed via one or more error-coding dispersed storage functions and sliced into data slices. A certain number of the data slices are selected for wireless communication via a plurality of wireless modules wherein a first wireless module sends a first portion of the data slices, and a second wireless module sends a second portion of the data slices, and so on until the data slices are fully communicated. The wireless modules may be of different hardware, software, protocols, throughputs, bandwidth, speeds, encoding schemes, algorithms, etc. The transmission over several different wireless modules that potentially have different (and potentially changing over time) characteristics may increase both performance and security.

Abstract: Provided is a test apparatus that tests a device under test, comprising a test unit that sends and receives signals to and from the device under test; and a control apparatus that controls the test unit. The control apparatus includes a first buffer and a second buffer that buffer access requests to the test unit; a data output section that buffers, in the first buffer, access requests to be sent from the control apparatus to the test unit and, when an error occurs, buffers the access requests in the second buffer instead of the first buffer; and a transmitting section that sequentially transmits the access requests in the first buffer to the test unit and, when an error occurs, sequentially transmits the access requests in the second buffer to the test unit.

Abstract: Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.

Abstract: An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.

Abstract: A method for designing a video processor with a variable and programmable bitwidth parameter. The method comprises selecting logical operations having propagation delay that scales linearly with the bitwidth; determining a desired tradeoff curve; and grouping instances of a logic operation having same properties; for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation.

Abstract: An efficient method and system for detecting frame slip in an inband signalling block in pulse code modulation. The effect of frame slip on the inband signalling block is that the bits following the frame slip are transferred from the signalling block into an adjacent block. The octet slip is detected by searching an error bit in a signalling block by comparing it to a sample block. If an error bit is found, an error count for the adjacent block starting from the error bit is calculated. If the error count is more than one, a second error bit of the signalling block is searched (26) and bits of the adjacent block after second error bit are verified (27). If bits of the adjacent block after the second error bit are not correct, the octet slip cannot be assumed (29). Otherwise the octet slip can be assumed by analyzing error count and error bits.

Abstract: The embodiments disclosed herein extend to methods, systems, and computer program products for error resolution in a computing system that includes a health module. The health module monitors components of the system for runtime errors and provides error resolution templates. The error resolution templates include metadata that specifies actions that may resolve the error and error handlers corresponding to the actions that may correct the error. The system may be extended by the addition and/or modification of the error resolution templates. The error resolution templates may also be used to facilitate the correction of runtime errors in the system.

Abstract: In measuring a certain time lag between generations of two pulse signals, a time lag measuring device prevents errors in measurement results even with an error in two reference signals for measuring the time lag. The device measures a time lag between a start signal M1 and a stop signal M2 and includes a reference signal generating section 41 generating two reference signals S1, S2 having a phase difference ?/2, and an amplitude detecting section 42 detects amplitudes A11, A12 and A21, A22 of the reference signals S1, S2 at generation timings for the start signal M1 and the stop signal M2, a phase difference detecting section 43 calculating a phase _ of the reference signals S according to each set of the amplitudes (A11, A12) and (A21, A22), and a correcting section 46 correcting the calculated phase using correction data for error correction in the reference signals S1, S2.

Abstract: According to the present invention, in a content delivery managing section 16, transmission channels and transmission timing are allocated to contents layered according to content properties or respective contents constituting a program. In a content transmission section 10, on the basis of the transmission channels and transmission timing allocated in the content delivery managing section 16, coded bit sequences 101a to 101n of respective contents are multiplexed with timing information 102 such as decoding timing information, combination timing information, presentation timing information and reproduction start timing information for the contents generated in a timing information generating section 14 to generate transmission bit sequences 105a to 105n, and they are transmitted.

Abstract: A data management apparatus connected to a data storage apparatus via a network manages the data storage apparatus by transmitting a command of structured document format such as the extensible markup language format and receiving the information related to the executed command as response data of the structured document format. Since the information included in the command is expressed using the structured document format, the data storage apparatus can flexibly interpret the command by ignoring missing and excess information included in the command, and vice versa.

Abstract: A method for updating computing device firmware may comprise: (a) receiving a transmission of firmware update data; (b) writing the firmware update data to a firmware update data partition; and (c) writing the firmware update data to an active firmware partition. A system for updating computing device firmware comprising: (a) means for receiving a transmission of firmware update data; (b) means for writing the firmware update data to a firmware update data partition; and (c) means for writing the firmware update data to an active firmware partition.

Abstract: A series of marks on an optical disc are sampled to yield a series of data pulses. The marks are at least substantially angularly equidistant to one another on the optical disc. A function is performed on the series of data pulses to yield an error-corrected series of data pulses. The function is one of: frequency domain filtering, signal averaging, and signal integration.

Abstract: A method of receiving data packets. In the method of receiving data packets, a determination is made as to whether a received data packet is received out of an expected order. If the determining step determines a received packet is out of the expected order, a time period is calculated to wait for one or more missing data packets based at least in part on an expected time of receiving the one or more missing data packets.

Abstract: In data transmission apparatus, a transmission device transmits data to a destination when a user instructs data transmission. A storage device stores user information to relate destinations to users. The apparatus can communicate with a server having destination information. When the user logs in, automatic retrieval is requested to the server to retrieve a destination related to the user in the user information in the storage device. A result of retrieval executed by the server is received and stored in the storage device.

Abstract: Provided in a reception device (10) for receiving a transmission signal (US) in which, adhering to a communications protocol, reception data (ED) can be transmitted to the reception device (10) from a transmission device (2, 3) are reception means (12) for receiving the transmission signal (US), and evaluation means (16) for evaluating the received transmission signal (US) and for emitting a bit sequence (BFT) received in the transmission signal (US), which bit sequence (BFT) may contain bits of reception data (ED) transmitted from the transmission device (2, 3) but also bits (SB) occasioned by an interference to the transmission signal (US), and checking means (18) for checking whether the received bit sequence (BFT) infringes a rule of the communications protocol, wherein the reception device (10) is designed to continue with the reception of the transmission signal (US) and the checking of the received bit sequence (BFT) following the occurrence of an infringement of the communications protocol.

Abstract: An electronic transmitter device has a puncturing device with two data outputs and/or an interleaver with two data inputs. An electronic receiver device has a de-interleaver with two data outputs and/or a depuncturing device with two data inputs.

Abstract: An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.

Abstract: Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple edges, the edges of the output signals may be aligned independently, e.g., using edge specific delay elements.

Abstract: A method of handling a stuck bit in a directory of a cache memory which detects an error in a stored tag having an address field, a state field and an error-correction field, determines that the error is associated with a stuck bit of the directory member, marks the directory member as defective, and casts out corrected address information. The error is detected during processing of a cache directory access request, and is determined to be associated with a stuck bit of the directory member by attempting to correct a first error and then detecting a second error after the first correction attempt. The address information is cast out by routing a surrogate tag contained in a surrogate member of the cache directory through error-correction pipeline circuitry while transmitting the address information from the surrogate member to a cast-out machine.

Abstract: An event data transmission scheme is provided for reducing positron emission tomography event losses. The event data transmission scheme employs a more effective use of available data bandwidth. Each of a plurality of detector data slots is connected directly to a data aggregation control interface, and the control interface is connected to a coincidence processor.

Abstract: The present disclosure relates to attempting to initialize and configure a device utilizing a remote server and, more specifically, to attempting to initialize a device with low level device configuration information that is stored on a remote server or servers.

Abstract: Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.

Abstract: A printer apparatus generates a fixed-length packet by appending a termination identifier for representing a termination point of sub-data. The printer apparatus transmits the packet to a unit. Upon receiving the packet, the unit detects burst error based upon the termination identifier.

Abstract: The subject matter disclosed herein provides methods and systems for converting fixed-point soft bit values, provided by a demapper, into floating-point soft bits values. In one aspect, there is provided a method. The method may include receiving, from a demapper, soft bits formatted as a fixed-point value. Moreover, the soft bits may be converted from the fixed-point value to a floating-point value. The floating-point value is punctured to remove a bit. The converted soft bits are provided to a buffer to enable decoding of the buffered soft bits. Related systems, apparatus, methods, and/or articles are also described.

Abstract: In a method of handling errors in a digital system that includes a root complex in data communication with at least one endpoint, the endpoint including at least one advanced error reporting register, an error is detected by the endpoint. Error data indicative of the error is stored in an advanced error reporting register. An indication of which transaction caused the error is stored in a secondary location. An error message packet that includes the error data and the indication of which transaction caused the error is generated. The error message packet is transmitted to the root complex. The root complex is caused to take a preselected action in response to the error message packet.

Abstract: This disclosure provides a method of routing communications over a network through an intermediate destination, and it also provides a “universal proxy” that may be used for this purpose. A host wishing to deliver information to a client sends packets as part of a first exchange or “session” to the intermediate destination, which performs error detection and recovery for received packets. The intermediate destination then (if desired) masks the source and transmits the information to the client in a second session, with the intermediate destination controlling transmission (e.g., specifying transmission protocol) and performing loss recovery as appropriate. This methodology enables a number of applications, including masquerading of source identity through the intermediate destination, and TCP acceleration (e.g., by subscribing to a service where the intermediate destination is used to accelerate communications or offer special types of processing or services).

Abstract: A data converter includes: an input module to which a first data series is input, the first data series having a first data sequence and a first error detection code corresponding to a remainder of division of the first data sequence by a predetermined polynomial; a conversion module converting the first data sequence into a second data sequence by processing including one of insertion, exchange, and inversion of a bit or a bit sequence, and exclusive-OR with a predetermined bit or bit sequence; a processing bit sequence generation module generating a processing bit sequence corresponding to the processing; and a code generation module generating a second error detection code corresponding to the second data sequence based on an exclusive-OR of the generated processing bit sequence and the first error detection code.

Abstract: A method for calculating equal error protection (EEP) profiles is disclosed. The method uses a profile function related to a sub-channel size to calculate EEP profiles and then uses the EEP profiles to decode data. When a receiver receives a protection level and a size value of the sub-channel size, a corresponding sub-channel size can be rapidly obtained through a reference table of the protection level and the sub-channel size so as to calculate the required EEP profiles. The method in the present invention requires only a few adders/subtractors and shifters or an easily realizable multiplier to calculate the profiles so that the objective of effectively saving cost and rapidly obtaining the profiles is achieved.

Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.

Abstract: Provided is a control device including: a storage portion for storing binary data transmitted from outside and received successively; and a control portion for carrying out processing including: production processing of producing a frame where of the stored binary data, pieces of data expressing events occurring in a predetermined period are placed into a group among which pieces of data expressing events each having a small degree of variation are arranged so as to be close to each other; difference computing processing of arranging the frames produced at intervals of the predetermined time in a predetermined order and of computing a difference between two adjacent frames; compression processing of compressing a result of the computation by a run length method; and recording processing of recording, to a recording portion, a first frame in the difference computing processing, a number of difference computations, and the compressed data.

Abstract: Disclosed is a frequency error detector and combiner at a receiving end of a mobile communication system. The frequency error detector and combiner using a diversity operation at a reception end of a mobile communication system includes: a plurality of fingers respectively having a diversity combiner for diversity-combining reference symbols used for a frequency error detection, and a frequency error detector for combining output signals of the diversity combiner to generate a frequency offset value; and a frequency error combiner for performing a multipath diversity combination on output signals of the frequency error detector.

Abstract: The subject invention relates to systems and methods that perform consistency checks of user defined type (UDT) fragments utilizing a stream of data without wholesale copying of the data. Streaming consistency checks facilitate discovering invalid fragments as soon as possible such that the entire UDT fragment does not have to be read, stored, analyzed, etc. Additionally, a UDT fragment can be evaluated without being completely materialized; thus, systems and/or methods employing the subject invention can yield improved performance as compared to conventional techniques by reducing required resources and enabling faster detection of invalid structures.

Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.

Abstract: A method, system, and computer program product are disclosed in a data processing system for determining defect detection efficiency. Code development steps are tracked using a repository while code is being developed. The tracked development steps are used to determine an earliest first time when a defect could have been discovered. An actual second time when the defect was discovered is determined. The efficiency of defect detection is determined by comparing the time elapsed between the first and second times.

Abstract: A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g.

Abstract: The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Decoding is performed in a pipelined manner using a layered belief propagation technique and scalable resources, which are configurable to accommodate at least two codeword lengths and at least two code rates. A computer program product, apparatus and device are also described.

Abstract: A circuit and method for using hardware to calculate a first derivative of the number of performance events that occur in a microprocessor during a predetermined period of time. This first derivative indicates a frequency of such performance events, which can be used as either a predictor of future problems or needs, or may be used to invoke a corrective action.

Abstract: A circuit and a method are provided to produce a noise-free multi-input I/O pad for an integrated circuit chip. The circuit includes a normal mode internal node, which connects to normal mode circuitry and a test mode internal node, which connects to test mode circuitry. There are separate transfer devices which connect the I/O pad to the normal mode circuitry and to the test mode circuitry. In addition, a third transfer device, a load device, and a new intermediate internal node are added to prevent negative input voltage swings which occur on the I/O pad during the normal mode from causing the transfer gate to the test mode circuitry from turning ON causing chip failure.

Abstract: A descrambling circuit includes three or more scramble value generators, each configured to generate a new scramble value by a formula at a state of shifting number of times different from each other by every eight bits based on a predetermined generator polynomial, a scramble value generated by the generator polynomial, and a descramble unit configured to descramble partially discontinuous scrambled input data by using the scramble values generated by the three or more scramble value generators.

Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.

Abstract: An embodiment of the invention includes a method of operating a remote testing access system. The method comprises receiving a test request from a test device over an incoming time division multiplexed (TDM) connection and in a TDM format wherein the test request indicates a one of a plurality of types of tests to perform on a soft switch, processing the test request to select a one of a plurality of service applications of the soft switch corresponding to the one type of test, and transmitting communications for the one type of test to the one service application in a packet format.

Abstract: A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled to the upstream data bus and a transmitter coupled to the downstream data bus. Similarly, each of the memory modules includes a receiver coupled to the downstream data bus and a transmitter coupled to the upstream data bus. Each receiver includes a receive clock generator that is synchronized by coupling a known pattern of data to the receiver. The receiver determines which phase of the receive clock best captures the known pattern and uses that receive clock phase during normal operation.