Abstract: Provided are a base station apparatus, a terminal apparatus and a communication method, capable of an efficient retransmission control of uplink data of which a resource for transmission is not discerned in grant-free multiple access. A terminal apparatus configured to communicate with a base station apparatus includes a transmitter configured to transmit an identifying signal indicating that the terminal apparatus itself transmits an uplink data channel and the uplink data channel. The uplink data channel includes an uplink data bit, a bit representing an identifier of the terminal apparatus, a first error detection bit generated from the uplink data bit, and a second error detection bit generated from the identifier of the terminal apparatus. The first error detection bit is scrambled using the identifier of the terminal apparatus, and the second error detection bit is scrambled using the identifying signal.

Abstract: A super-frame for transmission in an optical communications system comprises two or more data frames and a parity frame. All frames in the super-frame have been encoded in accordance with a first Forward Error Correction (FEC) scheme. The parity frame is computed over the two or more data frames (prior to or concurrently with or after encoding via the first FEC scheme) according to a second FEC scheme. At a receiver, the super-frame is decoded in accordance with the first FEC scheme to generate a set of FEC decoded frames in which residual errors are clustered, that is, are non-Poisson. The second FEC scheme, which is particularly suited or designed to correct the clustered non-Poisson residual errors, is used to correct the residual errors.

Abstract: A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit.

Abstract: A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a permutation network of a permutation circuit according to the default dimension value and a saving parameter, wherein the permutation network comprises a plurality of permutation layers arranged sequentially, and each of the permutation layers has the same amount of nodes, wherein the amount of the permutation layers and the amount of the nodes of each of the permutation layers are set according to the default dimension value and a saving parameter; and disposing a plurality of selectors on the nodes of the permutation network of the permutation circuit.

Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. When the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, when the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.

Abstract: Some embodiments described herein relate managing communications between an origin and a destination using end-user and/or administrator configurable virtual private network(s) (VPN(s)). A first VPN that defines a first data path between an origin and a destination can be defined at a first time. A second VPN that defines a second, different data path between the origin and the destination can defined at a second time. Each packet sent across the first VPN and each packet sent across the second VPN can follow the same data path for that VPN, such each packet can be sent across the first VPN or the second VPN in the order it was received, and the transition between the first VPN and the second VPN can be “seamless,” and communications between the origin and the destination are not disrupted between the first time period and the second time period.

Abstract: In one embodiment, linked-list interlineation of data in accordance with the present description includes inserting a subsequent set of data in a linked-list data structure within an initial data structure. The linked-list data structure includes a sequence of linked-list entries interspersed with the initial data of the initial data structure. To insert the subsequent data, a pattern of data within the initial data structure is replaced with data of the subsequent set of data in a sequence of linked-list entries of the linked-list data structure. Other aspects are described herein.

Abstract: In one embodiment, a method includes writing data to a storage medium, via a write channel, by applying a partial reverse concatenated modulation code to the data prior to storing encoded data to the storage medium. The applying the partial reverse concatenated modulation code to the data includes application of a C2 encoding scheme to the data to produce C2-encoded data prior to application of one or more modulation encoding schemes to the C2-encoded data to produce modulated data, followed by application of a C1 encoding scheme to the modulated data subsequent to the application of the one or more modulation encoding schemes to produce the encoded data.

Abstract: A data processing apparatus and method with efficient decoding of an LDPC code under bit interleave processing is disclosed. In one example, a data processing apparatus includes a parallel demapping portion configured to obtain a second data stream by executing in parallel demapping processing corresponding to mapping on a transmission side for a first data stream as an object of processing. The apparatus also includes a bit interleave reverse processing portion configured to obtain a third data stream by executing in parallel bit interleave reverse processing corresponding to bit interleave on the transmission side for the second data stream, and an LDPC decoding portion configured to decode the third data stream which is inputted in parallel with a bit group as a unit. The present disclosure, for example, can be applied to a receiving apparatus for a digital broadcasting.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for performing physical layer operations in a point-to-point network is disclosed. The method involves receiving, from a link in the communications network, information in an operations, administration, and management (OAM) word, setting an interleaving level, L, in response to the information received in the OAM word, inserting an OAM word into a forward error correction (FEC) frame, the OAM word including the set interleaving level (L), and transmitting, onto the link in the communications network, the FEC frame, which includes the OAM word.

Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

Abstract: An apparatus is provided. The apparatus comprises a processing system comprising: an ARINC 429 converter system; an Internet protocol (IP) suite; and an Ethernet driver; wherein the processing system is configured to be coupled to a communications management system and at least one IP radio; wherein the processing system converts data, from the communications management system, from an ARINC 429 protocol into a transport layer protocol, an IP and a Ethernet protocol; and wherein the processing system converts data, from the IP radio, from the Ethernet protocol, IP, and transport layer protocol to the ARINC 429 protocol.

Abstract: A communication system that uses keyed modulation to encode fixed frequency communications on a variable frequency power transmission signal in which a single communication bit is represented by a plurality of modulations. To provide a fixed communication rate, the number of modulations associated with each bit is dynamic varying as a function of the ratio of the communication frequency to the carrier signal frequency. In one embodiment, the present invention provides dynamic phase-shift-keyed modulation in which communications are generated by toggling a load at a rate that is a fraction of the power transfer frequency. In another embodiment, the present invention provides communication by toggling a load in the communication transmitter at a rate that is phase locked and at a harmonic of the power transfer frequency. In yet another embodiment, the present invention provides frequency-shift-keyed modulation, including, for example, modulation at one of two different frequencies.

Abstract: Various embodiments disclosed herein provide for a transmitter that can adjust the size of an information block or segment the information block based on a forward error correction (FEC) code optimum efficiency. Certain FEC codes are more efficient at encoding and decoding longer information blocks and if an information block is shorter than a predetermined length, the transmitter can pad the information block with a group of null bits to lengthen the information block to increase the performance of encoding and decoding the information block. In some embodiments, the transmitter can segment the information block into a set of segments, and if the last segment is below the predetermined length, the transmitter can pad the last segment.

Abstract: Embodiments are directed to a semiconductor wafer having on-wafer circuitry. The on-wafer circuitry includes functional circuitry and first drive circuitry communicatively coupled to the functional circuitry. The on-wafer circuitry further includes test-only circuitry communicatively coupled to the functional circuitry, along with second drive circuitry communicatively coupled to the test-only circuitry. The control circuitry is communicatively coupled to the second drive circuitry and the test-only circuitry, wherein the first drive circuitry is configured to drive the functional circuitry in a first manner, and wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner.

Abstract: A node configured to support multi-service with Flexible Ethernet (FlexE) includes circuitry configured to receive a client signal, wherein the client signal is different from a FlexE client; and circuitry configured to map the client signal into a FlexE shim. A method, implemented in a node, for supporting multi-service with Flexible Ethernet (FlexE) includes receiving a client signal, wherein the client signal is different from a FlexE client; and mapping the client signal into a FlexE shim.

Abstract: A super-frame for transmission in an optical communications system comprises two or more data frames and a parity frame. All frames in the super-frame have been encoded in accordance with a first Forward Error Correction (FEC) scheme. The parity frame is computed over the two or more data frames (prior to or concurrently with or after encoding via the first FEC scheme) according to a second FEC scheme. At a receiver, the super-frame is decoded in accordance with the first FEC scheme to generate a set of FEC decoded frames in which residual errors are clustered, that is, are non-Poisson. The second FEC scheme, which is particularly suited or designed to correct the clustered non-Poisson residual errors, is used to correct the residual errors.

Abstract: An apparatus having a microcontroller includes a processing unit, an internal communication bus assembly, a volatile memory, a non-volatile memory, a logic error management circuit, and two interface circuits. A first interface circuit couples the processing unit to the volatile memory via the internal communication bus assembly. A second interface circuit couples the processing unit to the non-volatile memory via the internal communication bus assembly. When the microcontroller is operating, the interface circuits are arranged to retrieve and evaluate requested data from their respective memory without intervention from the processing unit. In the event a failure is detected, the logic error management circuit is arranged to assert a stop signal. In some cases, detecting a failure includes comparing a check value stored in memory with a check value calculated from the data retrieved from memory.

Abstract: A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.

Abstract: Techniques are disclosed relating to circuitry configured to interleave data, e.g., for use to process error correcting codes for wireless data transmission. In some embodiments an apparatus includes one or more circuit elements configured to receive input data samples, a plurality of polynomial coefficients, a start index, and information indicating a window size for non-sequential traversal of interleaver indices. The polynomial coefficients may include coefficients for at least a third-order polynomial. In some embodiments, the one or more circuit elements are further configured to generate interleaved bank and address information for writing the input data samples to the plurality of memory blocks, based on an order of the polynomial, a code block length, the start index, and the information indicating the window size. In some embodiments, the apparatus also includes output circuitry configured to provide interleaved data samples from the memory blocks.

Abstract: A memory device includes one or more memory arrays and a quad bit error correction circuit. The quad bit error correction circuit may include a first layer error correction circuit and a second layer error correction circuit. The first layer error correction circuit may be configured to generate a Hamming correction bit vector, and the second layer error correction circuit may be configured to generate a Golay correction bit vector. The Hamming correction bit vector and the Golay correction bit vector may be used to identify up to four correctable bit errors in data to be stored in the one more memory arrays.

Abstract: In a transmission device, a determining unit determines, for use in transmission, an LDPC encoding method corresponding to occurrence conditions of external noise from a plurality of LDPC encoding methods each having the same code length and the same code rate and being defined by a different parity check matrix, and an encoding unit generates a codeword bit sequence by encoding transmission data using the LDPC encoding method determined by the determining unit.

Abstract: A communication device includes a barrel shifter shifting an information sequence according to a code word number; an error correction coding circuit encoding the shifted information sequence to generate a code word; and a transmitter transmitting a frame with N rows and M columns in the order of the row numbers. One code word is disposed in a row of the frame. The row number of the frame corresponds to the code word number. When a code word number is N, the error correction coding circuit encodes an information sequence of a second size smaller than the first size and fixed data of a third size, which is the difference between the first size and the second size, and disposes them in a row of the frame such that the error correction parity follows the information sequence of the second size and the fixed data follows the error correction parity.

Abstract: The application provides a network device, which includes: a main control board and a service board, where the main control board includes a processor and a switching chip, and the service board includes a physical layer component. The switching chip is connected to the physical layer component by using a system bus. The system bus consists of a SerDes link, and is configured to transmit service data and control information of a port of the physical layer component. The processor controls the port of the physical layer component by using the control information of the port of the physical layer component. The network device transmits the service data and the control information by using the system bus, so that the service board does not need to set a CPU processing the control information, thereby expanding an interface flexibly, and reducing device complexity and hardware costs.

Abstract: A method and an image processing apparatus for image-based object feature description are provided. In the method, an object of interest in an input image is detected and a centroid and a direction angle of the object of interest are calculated. Next, a contour of the object of interest is recognized and a distance and a relative angle of each pixel on the contour to the centroid are calculated, in which the relative angle of each pixel is calibrated by using the direction angle. Then, a 360-degree range centered on the centroid is equally divided into multiple angle intervals and the pixels on the contour are separated into multiple groups according to a range covered by each angle interval. Afterwards, a maximum among the distances of the pixels in each group is obtained and used as a feature value of the group. Finally, the feature values of the groups are normalized and collected to form a feature vector that serves as a feature descriptor of the object of interest.

Abstract: A method and a radio base station for interleaving control channel data to be transmitted in a telecommunications system are described. The method comprises grouping the control channel elements CCE1-CCEn into a first order of control channel symbol groups, adding symbol groups comprising dummy values or zeros to the first order of control channel symbol groups based on a number of available symbol group positions for the shared control channel, interleaving the first order of the control channel symbol groups resulting in an a second order, and mapping the second order of control channel symbol groups to the available control channel transmission resources.

Abstract: A data processing system is disclosed that includes machines having an in-line accelerator and a general purpose instruction-based general purpose instruction-based processor. In one example, a machine comprises storage to store data and an Input/output (I/O) processing unit coupled to the storage. The I/O processing unit includes an in-line accelerator that is configured for in-line stream processing of distributed multi stage dataflow based computations. For a first stage of operations, the in-line accelerator is configured to read data from the storage, to perform computations on the data, and to shuffle a result of the computations to generate a first set of shuffled data. The in-line accelerator performs the first stage of operations with buffer less computations.

Abstract: Storage devices and components, including memory components (e.g., non-volatile memory) can be trained by executable code that facilitates and/or performs reads and/or write requests to one or more storage sub-modules of a storage component (e.g., memory configured on a memory channel) made up of multiple storage components (e.g., DIMMs). The executable code can also train multiple storage components at the same time and/or in parallel.

Abstract: A system for monitoring graphics processing units, including an image merge element; a database memory, operatively connected to the image merge element; and, a comparator element. The image merge element is configured to: i) receive visible image data from a graphics processing unit (GPU); ii) extract a symbol identifier; iii) receive a mask; and, iv) calculate a cyclic redundancy check (CRC) of a masked portion of the visible image data corresponding to the mask. The database memory is operatively connected to the image merge element. The database memory includes: a mask database including lookup tables of masks for defined areas of the visible image data indexed by the extracted symbol identifier; and, a CRC signature database including a table of valid CRCs for the image data indexed by the extracted symbol identifier.

Abstract: A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.

Abstract: There are various drawbacks by using existing OTN (Optical Transport Network) frames for communication between OTN cards. Such drawbacks might for example include high latency, low robustness, and/or high coding rate. According to embodiments of the present disclosure, systems and methods are provided for modifying an OTN frame (or creating a new frame with data from the OTN frame) prior to transmission by an OTL (Optical channel Transport Lane) in order to address some or all of the foregoing drawbacks. Note that this embodiment can make use of existing hardware (e.g. hardware used for generating the OTN frame, and the OTL used for transmission).

Abstract: A data processing system is disclosed that includes machines having an in-line accelerator and a general purpose instruction-based general purpose instruction-based processor. In one example, a machine comprises storage to store data and an Input/output (I/O) processing unit coupled to the storage. The I/O processing unit includes an in-line accelerator that is configured for in-line stream processing of distributed multi stage dataflow based computations. For a first stage of operations, the in-line accelerator is configured to read data from the storage, to perform computations on the data, and to shuffle a result of the computations to generate a first set of shuffled data. The in-line accelerator performs the first stage of operations with buffer less computations.

Abstract: A concatenated error correction device may be provided that includes: a first encoder which encodes a plurality of blocks arranged in a column direction and a row direction into a block-wise product code consisting of column codes and row codes by applying a first error correction code to the blocks in each of the column direction and the row direction; and a second encoder which receives K number of source symbols and applies a second error correction code to the source symbols, and then encodes into N number of symbols including N-K number of parity symbols. The N number of symbols form the plurality of blocks. K and N are natural numbers.

Abstract: Methods and apparatus to perform serial communications are disclosed. An example serial data transmitter includes: a clock signal generator to generate a digital clock signal; a clock signal controller to enable the clock signal generator; a line break signal generator to, in response to an expiration of a time period, trigger the transmission of a transmission line check frame; a data integrity check generator to generate error detection data corresponding to first data to be transmitted via the transmission port; a signal framer to: generate a first data frame having a preamble, second data, third data, the first data, the error detection data, and fourth data; and generate the transmission line check frame.

Abstract: A method begins by a set of distributed storage and task (DST) execution units receiving a set of partial tasks and data, where a partial task of the set of partial tasks includes a common task and a unique partial sub-task. The method continues with the set of DST execution units executing the common task on the data to produce a set of preliminary partial results. The method continues with a first DST execution unit of the set of DST execution units generating first interim data based on the at least some of the set of preliminary partial results. The method continues with the first DST execution unit executing a first unique partial sub-task on at least one of a first portion of the data and the first interim data to produce a first partial result.

Abstract: Row decoding is performed on row codewords in an array in order to produce a row decoded array that includes row decoded column codewords. Column decoding is performed on the row decoded column codewords in order to produce a row and column decoded array that includes row and column decoded row codewords and row and column decoded column codewords. The number of row and column decoded row codewords that are not in a row codebook is determined and the number of row and column decoded column codewords that are not in a column codebook are determined. If the number not in the row codebook equals 0 and the number not in the column codebook equals 1, at least a data portion of the row and column decoded array is output.

Abstract: A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.

Abstract: Data fields within a trace data set are interpreted using data field declarations of the data fields that each specify a data type definition of a respective data field. A data value of an interpreted data field is compared with the data type definition specified within a respective data field declaration for the interpreted data field within the trace date set. Based upon the comparison, a determination is made that the respective interpreted data field contains a data value that violates the data type definition specified within the respective data field declaration.

Abstract: A LDPC decoder utilizes a new schedule that breaks a dependency between data of different layers of a parity check matrix, so that the forward scan in the next layer can begin to perform after a predetermined time has elapsed (i.e. a delay) since the backwards scan of the previous layer has begun, and before the backwards scan of the previous layer is completed. Accordingly, the computation at the next layer can begin as soon as possible.

Abstract: A method and a radio base station for interleaving control channel data to be transmitted in a telecommunications system are described. The method comprises grouping the control channel elements CCE1-CCEn into a first order of control channel symbol groups, adding symbol groups comprising dummy values or zeros to the first order of control channel symbol groups based on a number of available symbol group positions for the shared control channel, interleaving the first order of the control channel symbol groups resulting in an a second order, and mapping the second order of control channel symbol groups to the available control channel transmission resources.

Abstract: A system and method are illustrated as including receiving a request for a current time and transmitting the current time to a password device. The current time is used to synchronize a clock in the password device to reflect the current time of an authentication server. The synchronized clock is used to generate a first token value at the password device. A request for the first token value is received from a server of the site by the authentication server. The server of the site is provided with the first token value. The server of the site sends a list of token values including the first token value to a computing device associated with the password device. The list of token values, presented at the same time on the computing device, are compared to the first token value generated by the password device to determine a matching first token value.

Abstract: Memory depth optimization in communications systems with ensemble PHY layer requirements. Memory depth, for one or more modules in a communication device, is managed based on a limited amount of provisioned hardware. For example, each of a number of various modules within a communication device is configurable to operate at various memory depths. Considered together, various sets or profiles of operational parameters (e.g., associated with particular settings for each of the various modules within the communication device), may be employed to configure the communication device to operate in accordance with one of a variety of operational modes. For example, in a first operational mode, latency may be minimized (e.g., using shorted codewords, shorter interleaver depth, etc.), whereas in a second operational mode, a higher latency may be tolerated but with an expectation of much lower error rates (e.g., achieved using more powerful ECC, longer interleaver depth, etc.).

Abstract: A method performed by a medical device for transmitting data packets includes: removing select data fields from a data packet defined in accordance with IEEE standard 11073 to form a modified data packet; determining a length of the modified data packet; determining whether the length of the modified data packet is greater than a predetermined maximum length of data packets under the Bluetooth low energy protocol, as defined in Bluetooth Core Specification version 4.0 or higher; when the length of the modified data packet is greater than the predetermined maximum length of data packets defined under the Bluetooth low energy protocol, partitioning the modified data packet into a plurality of individual data packets, wherein each of the individual data packets includes a portion of the modified data packet; and transmitting the individual data packets via an antenna in accordance with the Bluetooth low energy protocol.

Abstract: A method and apparatus is disclosed herein for performing wireless communication.

Abstract: A method begins by a dispersed storage (DS) processing module detecting, in accordance with a rebuilding process, a storage error of an encoded data slice stored in a storage node of a dispersed storage network (DSN) and identifying the encoded data slice for rebuilding. The method continues with the DS processing module identifying one or more storage traits associated with the encoded data slice and identifying encoded data slices having at least one storage trait in common with the one or more storage traits of the encoded data slice to produce identified encoded data slices. The method continues with the DS processing module prioritizing storage error detection analysis of the identified encoded data slices over other encoded data slices stored in the DSN and when a storage error is detected for one of the identified encoded data slices, identifying the one of the identified encoded data slices for rebuilding.

Abstract: The present invention discloses a method and apparatus of performing outer loop link adaptation (OLLA) operation. This method may comprise: accelerating in an initial probing phase, increase of an OLLA scaling factor until obtaining a negative result regarding codeword selection; and fine modifying, in a fine modification phase, the scaling factor using an upturn factor and a downturn factor in response to the result regarding codeword selection so that a channel quality indication, which is modified using the scaling factor, is matched with its actual value. Compared with the prior art, the technical solution as provided in the present invention can quickly modify a CQI to match its actual value, thus this solution may effectively mitigate the CQI mismatch, improve the CQI feedback accuracy, and further enhance the cell throughput performance and frequency utilization.

Abstract: The present disclosure provides a method for monitoring a control channel in a wireless access system, including setting the number of maximum blind decoding times for each user equipment (UE)-specific search space and a common search space to which the control channel is transmitted; monitoring a plurality of candidate control channels in each of the search spaces, based on the number of maximum blind decoding times, set in the respective search spaces; and receiving downlink control information through a control channel which has succeeded in the blinding decoding among the plurality of candidate control channels, wherein the common search space is allocated to at least one carrier group that includes at least one component carrier.

Abstract: The present application relates to a method in which a relay node receives control signals from a base station in a wireless communication system. More particularly, the method comprises: a step of receiving, from the base station, a relay-node-dedicated physical downlink control channel (R-PDCCH) via a specific subframe; and a step of performing a blind decoding process on the physical downlink control channel to detect control information for the relay node, wherein said specific subframe includes a first slot and a second slot, and the size of a relay-node-dedicated control channel element (R-CCE) for performing the blind decoding process is individually defined depending on the number of reference signals contained in the first slot and in the second slot.

Abstract: A PLL status detection circuit and its associated method are disclosed herein. The circuit and the method are used to detect a PLL clock generated by a PLL of a chip to determine a status of the PLL. The PLL status detection circuit includes a counter, a status analyzing circuit and a status storing circuit. The counter is configured to generate a count value by counting cycles of the PLL clock according to a control signal. The status analyzing circuit, which is coupled to the counter, is configured to analyze the count value according to the control signal to generate an analyzed result. The status storing circuit, which is coupled to the status analyzing circuit, is configured to store the analyzed result. The status storing circuit is coupled to a scan chain of the chip so that the analyzed result is transmitted via the scan chain.