Abstract: A method, system and computer program product for efficiently developing software and supporting creation of source code so as to develop software that meets the requirements. A plurality of test cases defining a plurality of respective tests to be executed to check the conformity of the software to the requirements are used. In a test execution step, one or more specific test cases selected from the plurality of test cases are executed or the specific test cases are caused to be executed. Furthermore, a test result of a test case executed or caused to be executed in the test case execution step is added to the source code.

Abstract: A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result.

Abstract: A semiconductor memory may be provided with a built-in test mode that is accessible through a password protection scheme. This enables access to a built-in test mode after manufacturing, if desired. At the same time, the password protection prevents use of the built-in test mode to bypass security features of the memory.

Abstract: A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.

Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.

Abstract: A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple binary searches on segments. Segments are defined based on codeword, trapping set and biasing noise components of the channel. To improve calculation speed the most significant subclasses of codewords, trapping sets and noise signals are used.

Abstract: A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly.

Abstract: Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.

Abstract: A data processing apparatus is provided having error code generation circuitry configured to generate an error code associated with a received data value, such that a bit change in the received data value can be known about by reference to the error code. Stored data values are stored in a data store and associated error codes are stored in an error code store. Error checking circuitry performs a verification operation on a stored data value and an associated error code to determine if an error has occurred in at least one of the stored data value and the associated error code during storage. The received data value comprises at least one additional bit with respect to the stored data value and the error checking circuitry is configured to reconstruct the at least one additional bit by reference to the stored data value and the associated error code.

Abstract: The present invention provides a system for detecting timing characteristics of internal signals in a communications device, the system comprising: a system clock running at a known frequency; a test counter having a test input at which an internal signal to be tested is received; a gating counter having an input arranged to receive the system clock signal; and a system controller for controlling the counters; wherein the system controller controls the gating counter to count a predetermined number of system clock cycles to define a test period, and during the test period the test counter counts the cycles of the internal signal under test, whereby timing characteristics of the internal signal may be found with reference to a time base defined by the system clock. An associated method of operation is also described.

Abstract: Method and apparatus for writing data to be stored to a predetermined memory area, the method comprising: reading stored data from the predetermined memory area, the stored data comprising a stored data block and an associated stored error detection value, manipulating, after reading the stored data, at least one of the stored data block and the associated stored error detection value in the predetermined memory area, and writing, after manipulating, the data to be stored to the predetermined memory area.

Abstract: A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.

Abstract: In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

Abstract: A remotely-accessible electronic circuit is provided, which, in wireless communication with a maritime pilot's Personal Pilot Unit (PPU), or other remote computer, is able to identify a common mis-wiring of an Automatic Identification System (AIS) Pilot Port in a maritime vessel. The circuit then is remotely controlled to electronically manipulate the connections that provide raw transmit and receive signals from the AIS Pilot Port. The electronic manipulation corrects the common mis-wiring without actual physical intervention of the pilot with the AIS Pilot Port, or other mechanical interface between that port and the pilot's PPU.

Abstract: Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.

Abstract: An error injection module for injecting errors into an ECC memory selects a target address associated with the ECC memory, selects an error injection pattern, and sets a redirect address of the scrubber to the target address. During an injection mode of the scrubber, the error injection module injects the error injection pattern into the target address of the ECC memory with the scrubber.

Abstract: A browser-based simulator may be used to create and send test messages to one or more transaction processing facilities (TPFs) to determine the response of the TPF system. It allows a user or plurality of users to create ISO 8583 messages, send the messages to the TPF systems, receive a response, and display the results to the users. Messages created by the simulator are stored within an ANSI queryable SQL database to make test selection simple. The TPF test messages and results are thus available worldwide. Further, the simulator is server-based, so desktop licenses are not required. The simulator allows a user to either select a preformatted message or derive a new message by selecting the data of interest.

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract: In order to detect a faulty error correcting unit (2) in an embedded system, wherein the error correcting unit (2) receives output data from a data source (20) and determines, whether the received data are incorrect, and wherein if the received data are incorrect, the error correcting unit (2) is expected to correct at least one error within the received data, output the corrected data and manipulate an error vector (4), a method and a system (Ia) are suggested that enable to compare the output data of the error correcting unit (2) with at least one reference data, wherein the at least one reference data originate at least indirectly from the data source (20). Both, the error vector (4) and the result of the comparison are input to a plausibility test in order to decide, whether the error correcting unit (2) is faulty. According to the result of the plausibility test, a failure vector (7) is manipulated in order to indicate whether a failure in the error correcting unit (2) is detected.

Abstract: Systems, methods, and computer-readable media provide for updating a firmware image during a debugging sequence using a firmware debugger application without re-flashing each updated firmware image on a non-volatile memory device. Embodiments include a debugger application operating on a host computer system and a debugger driver located within a firmware image undergoing the debugging sequence on a target computer system. The debugger application and debugger driver may communicate and transfer data between one another. Upon detecting an error in a firmware image, the debugger driver notifies the debugger application. The debugger application sends an updated firmware image to the debugger driver on the target computer system. The debugger driver loads the updated firmware image and passes control to an entry point of the updated firmware image for continued debugging from the new entry point.

Abstract: Embodiments of the invention include methods of transmitting a hidden message within a secured primary data transmission. In one embodiment, a method involves transmitting a primary data transmission over a computer network from a source host to a receiving host. Intentionally-corrupted packets are introduced within the primary data transmission in a manner providing a hidden message. For example, a pattern of intentionally-corrupted packets may be used to encode the hidden message. Alternatively, the hidden message may be embedded within the data area of the intentionally-corrupted packets. The intentionally-corrupted packets are received and interpreted at the receiving host to determine the hidden message.

Abstract: A method for enhancing verification efficiency regarding error handling mechanism of a controller of a Flash memory includes: providing an error generation module, for generating errors; and triggering the error generation module to actively generate errors of at least one specific type in order to increase an error rate corresponding to the specific type. An associated memory device and the controller thereof are provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control access to the Flash memory and manage a plurality of blocks, and further enhance the verification efficiency regarding error handling mechanism of the controller; and an error generation module arranged to generate errors. The controller that executes the program code by utilizing the microprocessor triggers the error generation module to actively generate errors of at least one specific type to increase an error rate.

Abstract: A relocatable interrupt handler for use in test generation and execution. A method for executing test code includes executing a test code block that includes a plurality of test instructions. The executing includes, for one or more of the test instructions: executing the test instruction; determining that the executing the test instruction caused an exception condition to occur; executing first exception handling logic associated with the exception condition based on determining that the executing the test instruction caused the exception condition to occur, the first exception handling logic located at an entry address consisting of a first memory address value, the executing the first exception handling logic including: clearing the exception condition; and changing the entry address to a second memory address value that is an address of a second exception handling logic. A return code that indicates a result of executing the test code block is then generated.

Abstract: A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the receiver then conditions the data and compares them with the transmitted check data in order to recognize transmission errors, wherein the transmitter bases the production of the check data and the receiver bases the conditioning of the data on the same check data formation method, wherein the check data formation/conditioning is performed using error recognition hardware, wherein the region of the receiver contains not only the error recognition hardware but also error recognition software which are used to additionally check the received data, and wherein also an error in the transmitted data and/or check data is caused by a transmitter-end error stimulation. A transmission and reception circuit for carrying out the above method and also the use thereof is also disclosed.

Abstract: Embodiments of the invention include methods of transmitting a hidden message within a secured primary data transmission. In one embodiment, a method involves transmitting a primary data transmission over a computer network from a source host to a receiving host. Intentionally-corrupted packets are introduced within the primary data transmission in a manner providing a hidden message. For example, a pattern of intentionally-corrupted packets may be used to encode the hidden message. Alternatively, the hidden message may be embedded within the data area of the intentionally-corrupted packets. The intentionally-corrupted packets are received and interpreted at the receiving host to determine the hidden message.

Abstract: An automated software testing system allows automated test script generation with fully parameterized scripts, execution, and result correlation. A software Application Under Test (AUT) includes a process having Graphical User Interface (GUI) windows, objects and data elements. A test thread tree is generated corresponding to these windows, objects and data elements. A data structure is generated to enumerate test cases indicative of the windows, objects and data elements. Also generated is a parameterized script implementing the test cases and having string values instead of hard-coded data. A global change manager automates modifying in the data structure, data object attributes across multiple scripts. A Scenario view or data generation member generates Test Descriptions, automatically documenting the test cases. The script is executed to apply each of the test cases to the AUT and receive responses.

Abstract: A data access method for accessing data in a flash memory is provided, wherein the data has a plurality of sub-data. The data access method includes generating an error correction code (ECC) for the data and writing the data and the ECC into the flash memory. The data access method also includes generating a corresponding bit checking code for each of the sub-data and writing the bit checking codes into the flash memory. When the sub-data subsequently is read from the flash memory, whether the sub-data contains any error is determined only according to the bit checking code corresponding to the sub-data. Thereby, the data access efficiency is improved.

Abstract: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. A signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector.

Abstract: When a communication error detection apparatus according to the present invention is initially installed, it performs a detection processing of the errors based on a sampling method in which a sampling interval of packet signals at the start of detection processing is a comparatively short. If the amount of the packet signals, which are sampled and accumulated, reaches a predetermined value, the communication error detection apparatus performs a detection processing of the errors based on another sampling method. In addition, if the detection processing of the errors is temporally released, the sampling method in which a sampling interval of packet signals is a comparatively short is used.

Abstract: The present invention provides a test apparatus for a 64B/66B encoding process capable of precisely performing a test with a high reproducibility on a certain pattern of a 64B/66B encoder or decoder. A frame generator generates frame data in a layer higher than a physical coding sublayer of Ethernet (registered trademark) and inputs the frame data to a 64B/66B encoder such that the 64B/66B encoder performs a 64B/66B encoding process of the physical coding sublayer with respect to the frame data. A sequence pattern generator generates a certain 66B sequence pattern written in advance, and a controller writes a desired sequence pattern in the sequence pattern generator and, at the same time, controls a data selector to select one of data encoded by the 64B/66B encoder and a sequence pattern output from the sequence pattern generator and to provide the selected one to a test subject.

Abstract: A controller for use at a node of a clustered computer apparatus includes an exception detection component for detecting an exception raised by a service component at the node; a quiesce component responsive to the exception detection component for quiescing lease-governed activity by the service component prior to termination of a lease; a lease control component responsive to the quiesce component for pre-expiry relinquishing of the lease; and a communication component responsive to the lease control component for communicating the pre-expiry relinquishing of the lease to one or more further nodes of the clustered computer apparatus. The controller may further include a second communication component for receiving a communication indicating the pre-expiry relinquishing of a lease; a second lease control component responsive to the communication to control failure processing; and a second service component to perform a service in place of the service component at the node.

Abstract: A device and method for outputting BIOS POST code, applied to a computer system. The device includes a basic input output system (BIOS), a transfer module and a video graphics array (VGA) connector. The BIOS generates a power-on self-test (POST) code using a low pin count (LPC) interface format. The transfer module receives the POST code and transfers the format of the POST code to a system management bus (SMBus) format. The VGA connector receives and outputs the POST code transmitted from the transfer module.

Abstract: A fault code memory management apparatus stores a permanent fault code in different places of a non-volatile memory, and restore the fault code when an error is detected in the fault code stored in the different places in a manner that, in case that discrepancy between the fault codes in different places is found, the fault code matching with data in a code table stored in a read-only memory is determined to be correct. If two fault codes have matching data in the code table, the fault code is compared with data in a standby random access memory that stores an original fault code data. Further, the data in the random access memory and the data in the code table are compared if the comparison between the code and the data in the random access memory is not sufficient.

Abstract: Systems, methods, and computer-readable media provide for updating a firmware image during a debugging sequence using a firmware debugger application without re-flashing each updated firmware image on a non-volatile memory device. Embodiments include a debugger application operating on a host computer system and a debugger driver located within a firmware image undergoing the debugging sequence on a target computer system. The debugger application and debugger driver may communicate and transfer data between one another. Upon detecting an error in a firmware image, the debugger driver notifies the debugger application. The debugger application sends an updated firmware image to the debugger driver on the target computer system. The debugger driver loads the updated firmware image and passes control to an entry point of the updated firmware image for continued debugging from the new entry point.

Abstract: In one embodiment, a controller can perform a secure clear of a poisoned indicator associated with an uncorrectable error (after recovery from the error). To this end, the controller may access a register storing an address of a memory location associated with indicator, determine whether the address corresponds to an entry in a table storing a list of such errors, and perform the clear based at least in part on the determination. Other embodiments are described and claimed.

Abstract: Disclosed are a method, system and computer program product for determining hardware diagnostics during initial program loading (IPL). A space is allocated for a diagnostics hardware table storing hardware identifications corresponding to hardware to be tested. A hardware monitor function detects new and/or defective hardware. Hardware can be manually selected. A runtime diagnostics detects defective hardware. The hardware identifications corresponding to the new, failing, and/or selected hardware are added to the diagnostics hardware table. The hardware identification to be tested is acquired during the building of a system Hardware Objects Model (HOM). A diagnostics flag is set within HOM according to the diagnostics hardware table. Diagnostics are performed per HOM diagnostics flag indication. The diagnostics table is cleared, and the operating system is run. At system runtime, diagnostics code monitors for runtime error.

Abstract: The present invention relates to a method, device, and system for managing verification of configurable hardware and software. The solution according to the present invention solves this by applying a matrix-like method of handling test and verification parameter combinations and interacting with a user using a browser like interface for simple and fast selection of coverage.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: Embodiments of the present disclosure relate to a system and method for testing an embedded circuit in a semiconductor arrangement as part of an overall circuit that is located on a semiconductor wafer, the system and method comprising an arrangement comprising an overall circuit with at least one input and output. The overall circuit may be provided with an embedded circuit that is not directly connected to the inputs and outputs or may be connected thereto by being specially switched. Switching elements and test islands that are connected thereto may be provided such that the input or the output of the embedded circuit may be connected to the test islands via the switching elements in case of a test. The switching elements may be switched to said test mode in case of a test by applying a voltage to the test island, or the switching elements may be switched in this manner.

Abstract: A diagnosis technique to improve scan cell internal defect diagnostic resolution using scan cell internal fault models.

Abstract: The invention relates to communications, particularly but not exclusively broadband communications. One facet of the present invention relates to provisioning of services in a communications network and finds particular, but not exclusive, application in a broadband network environment or other environment where services are provisioned. The provisioning of services will now be discussed in more detail.

Abstract: In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.

Abstract: There is disclosed a method and system of testing server side objects in a client-server environment. A proxy is created of a first object on a server side on a client side. The proxy invokes a method of the first object on the server side to conduct a test by a test case deployed on the client side. A proxy is created of a second object on the client side by the proxy of the first object by the process of invoking the method of the first object on the server side. The creation of the proxies and objects are performed recursively.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: A method for testing a storage apparatus, which includes: (a) writing a specific pattern to a storage unit of a storage apparatus; (b) reading the specific pattern written to the storage apparatus; (c) determining an error bit number of the specific pattern read in the step (b); and (d) determining that the storage unit has defect when the error bit number is larger than a error bit threshold value, wherein the error bit threshold value is smaller than a correctable bit number for a error correction code corresponding to the specific pattern.

Abstract: An electronic circuit includes configurable cells each having a test input and an output. The configurable cells are connected to one another in a chain in a predefined order via their test input and their output to form a test register based on receiving a chaining command signal. The electronic circuit also includes a detection circuit activated by the chaining command signal to produce a state signal representing a state of initialization of a first set of configurable cells A multiplexing circuit selectively connects the test input of each configurable cell to a second set of the configurable cells either to the output of a preceding configurable cell or to an output of a decoy data generator based on the state signal.

Abstract: In order to detect a faulty error correcting unit (2) in an embedded system, wherein the error correcting unit (2) receives output data from a data source (20) and determines, whether the received data are incorrect, and wherein if the received data are incorrect, the error correcting unit (2) is expected to correct at least one error within the received data, output the corrected data and manipulate an error vector (4), a method and a system (Ia) are suggested that enable to compare the output data of the error correcting unit (2) with at least one reference data, wherein the at least one reference data originate at least indirectly from the data source (20). Both, the error vector (4) and the result of the comparison are input to a plausibility test in order to decide, whether the error correcting unit (2) is faulty. According to the result of the plausibility test, a failure vector (7) is manipulated in order to indicate whether a failure in the error correcting unit (2) is detected.

Abstract: A BISR mode and associated method for testing memory. All redundant elements of the memory including the ones which are not used are tested, and interaction between redundant elements of the memory and adjacent functional memory are checked. Repair information is used to repair the memory. In addition, redundant elements which are not needed to be used for repairing the memory are forced to be used, such as by faking defects to remap good elements with redundant elements.

Abstract: Embodiments of the present invention are directed to validating a rules-based diagnostic system for a network. Emulated data for use by the rules-based diagnostic system can be generated that includes a trouble ticket to emulate a problem associated at least one of Layer 1 and Layer 2 network services and includes network information associated with the problem. Responses from the rules-based diagnostic system can be received in response to the emulated data being processed by the rules-based diagnostic system. A log generated by the rules-based diagnostic system can be analyzed to determine rules implemented by the rules-based diagnostic system in response to the emulated data, thereby validating operation of the rules-based diagnostic system.

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.