Abstract: A display device which can suppress erroneous display of a display panel is provided. A source driver receives a serial data signal in which a preamble and video data of the display panel are alternately continuous via an interface from a display controller. The source driver controls timing of supply of a gate signal from a gate driver based on the video data included in the serial data signal, and supplies a gradation voltage signal which corresponds to the video data to a plurality of data lines of the display panel. The source driver has a detection portion which detects that the interface is in an unstable state, and a gate reset signal output portion which outputs a gate reset signal for stopping an operation of the gate driver when the unstable state of the interface is detected at the time of the supply of the video data.

Abstract: The present subject matter relates to the field of communications technologies, and in particular, to a method and an apparatus for indicating a fault in flexible Ethernet. The method for indicating a fault includes: detecting whether a fault occurs in at least one physical layer entity included in a flexible Ethernet group; and when a fault occurs in the at least one physical layer entity, periodically sending a fault indication code block to a flexible Ethernet client corresponding to the at least one physical layer entity in which the fault occurs. Not all bandwidth of a downstream transmission path in the flexible Ethernet is occupied, and data transmission on a non-faulty channel in a same flexible Ethernet group is not affected, thereby reducing a quantity of affected flexible Ethernet clients.

Abstract: An iterative decoding circuit is provided. The iterative decoding circuit includes a first concatenated decoding circuit, a second concatenated decoding circuit, and a comparator. The first concatenated decoding circuit includes a first convolutional decoder, a first deinterleaver, and a first block decoder. The second concatenated decoding circuit is coupled to the first concatenated decoding circuit, and the second concatenated decoding circuit includes a second convolutional decoder, a second deinterleaver, and a second block decoder. The comparator receives a first convolutional decoding result corresponding to a first convolutional decoding operation and a second convolutional decoding result of a second convolutional decoding operation, and is configured to compare the first convolutional decoding result with the second convolutional decoding result to generate a comparing result. The second block decoder obtains an erasure address information according to the comparing result.

Abstract: Disclosed are a display device, and a source driver and a packet recognition method thereof. In the display device, when check information of a control data packet of transmitted transmission data is normal, a control data packet of to be restored is updated with a control data packet of a current cycle, and when the check information is abnormal, the control data packet to be restored is maintained, so that it is possible to normally drive a source signal even through there is an error or a change in the control data packet.

Abstract: A method and apparatus are provided for identifying and locating fault conditions in a network. Network performance data are derived from a network termination device perspective which enables fault detection in any part or parts of a link between the device and broadband remote access server (BRAS) including copper lines. For example, during a training phase, parameter data generated by a device is retrieved for a plurality of network termination devices in a predetermined portion of the network. The parameter data comprising values for a predetermined set of parameters indicative of data communications performance over that portion of the network. The data is analyzed and one or more models are generated. In a monitoring phase, the same parameters are retrieved from a network termination device of a selected user served by the same portion of the network to expose any significantly divergent behavior, potentially indicative of a fault condition.

Abstract: Illustrative communications link performance analyzer methods and modules that accommodate FEC. In at least some embodiments, a method for characterizing communications link performance includes: (A) transmitting a predetermined bit stream across a physical communications link to produce a receive signal; (B) deriving a received bit stream from the receive signal with a receiver, the receiver including an embedded debug module having: (1) a bit counter dividing the received bit stream into symbols and frames; (2) an error counter determining a symbol error count for each frame; and (3) an aggregator obtaining at least one performance-related statistic from the symbol error counts; (C) generating a performance measure based on the at least one performance-related statistic; and (D) displaying a visual representation of the performance measure.

Abstract: The invention relates to a method and device for testing a data link. A single-lane or multi-lane bit error tester that transmits one or more PRBS signals through the data link is augmented with a raw bit error buffer for storing bit error information for each detected error event and an error pattern analyzer. Most frequently occurring intra-lane bit error patterns, inter-lane word error patterns, and bit slip patterns are identified and their characteristics are analyzed so as to provide information indicative of root causes of the detected bit errors and bit slips.

Abstract: Soft decision sections provisionally decide each modulated signal separated using an inverse matrix calculation of a channel fluctuation matrix at separation section. Signal point reduction sections reduce candidate signal points of a multiplexed modulated signal using the provisional decision results. Soft decision sections make a correct decision using the reduced candidate signal points and obtain received data of each modulated signal. This allows received data RA, RB with a good error rate characteristic to be obtained with a relatively small number of calculations without reducing data transmission efficiency.

Abstract: An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.

Abstract: A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition sets. The design aiding program causes the computer to execute a process of mapping the worst-case corner candidates that are within an allowable range. The design aiding program causes a computer to execute a process of determining the worst-case corner candidates that minimize the number of the worst-case corner candidates mapped to the condition sets by handling the worst-case corner candidates thus mapped as a single worst-case corner candidate to be worst-case corners.

Abstract: Apparatus, and an associated method, for estimating a bit error rate of data communicated to a receiving station of a digital communications system, such as a GSM/EDGE cellular communication system. Soft decision values, indicative of confidence levels that decided values have been correctly decided are compared with threshold values by a comparator. A count is accumulated by a counter whose counted value is representative of decided data values having low levels of confidence that the decided values are correct. The count value is used in the formulation of the BER estimation.

Abstract: Methods and apparatus are disclosed for using error detection techniques, such as Forward Error Correction techniques, to predict the degradation below a certain threshold of an ability to accurately convey information on a communication channel, for example, to predict a failure of the communication channel. In response, transmission and/or reception of information on the channel may be adapted, for example, to prevent the degradation below the threshold, e.g., prevent channel failure. Predicting the degradation may be based, at least in part, on data transmission error information corresponding to one or more blocks of information received on the channel and may include determining an error rate pattern over time. Based on these determinations, the degradation below the threshold may be predicted and the transmission and/or reception adapted. Adapting may include initiating use of a different error encoding scheme and/or using an additional communication channel to convey information.

Abstract: A receiving apparatus is disclosed which includes: an amplification section configured to amplify a received signal including a digital broadcast signal; a mixing section configured to mix the received signal amplified by the amplification section with a selective frequency signal so as to acquire an intermediate frequency signal; a demodulation section configured to demodulate the intermediate frequency signal acquired by the mixing section so as to acquire a demodulated signal of the digital broadcast signal; and a control section configured to control the amplification factor of the amplification section in a manner bringing to a target level the signal level of the intermediate frequency signal acquired by the mixing section, the control section being further configured to set variably the target level in accordance with bit error status of the demodulated signal acquired by the demodulation section from the digital broadcast signal.

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: Disclosed is a method and apparatus for transmitting data between a timing controller and a source driver, and more particularly, a data transmission method and apparatus between a timing controller and a source driver, which has a bit error rate test (BERT) function for sensing an error rate in real time when data is transmitted and received between the timing controller and the source driver.

Abstract: Apparatus, and an associated method, for estimating a bit error rate of data communicated to a receiving station of a digital communications system, such as a GSM/EDGE cellular communication system. Soft decision values, indicative of confidence levels that decided values have been correctly decided are compared with threshold values by a comparator. A count is accumulated by a counter to whose counted value is representative of decided data values having associated therewith low levels of confidence that the decided values are correct. The count value is used in the formulation of the BER estimation.

Abstract: System and method for determining and/or merging differences between configuration diagrams. First information is received regarding a first configuration diagram comprising a first plurality of nodes and graphically representing a first system, and second information is received regarding a second configuration diagram comprising a first plurality of nodes and graphically representing a second system. At least a portion of the nodes may correspond to hardware devices, programs, and/or configuration data of the respective systems, and may be interconnected. The first and second information is analyzed to determine and/or merge differences between the first configuration diagram and the second configuration diagram, e.g., differences between hardware, software, configuration, and/or connectivity, e.g., by traversing the configuration diagrams or data structures representing the diagrams. An indication of the differences and/or a merged configuration diagram may be displayed on a display device, e.g.

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, which corresponds to a baseline jitter amount. In turn, the receive test accelerator tests the device, at the adjusted test time, using a data stream that is modulated by the adjusted jitter amount.

Abstract: In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.

Abstract: A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, increment the pass counter responsive to determining that all errors have been checked, and clear the error counter responsive to determining that the pass counter is greater than or equal to a pass count threshold value.

Abstract: An error controlling system includes a plurality of error generation target circuits, a plurality of pseudo error generating devices each having a pseudo error content holding register that holds directed pseudo error content, each plurality of pseudo error generating device generates a pseudo error corresponding to a pseudo error content held in a respective pseudo error content holding register in at least one of data to be written to one of the plurality of error generation target circuits and data to be read from one of the plurality of error generation target circuits upon being directed to generate the pseudo error, and a pseudo error controlling device that directs the plurality of pseudo error generating devices to generate a pseudo error corresponding to a respective pseudo error content held in each of the pseudo error content holding register provided in each of the plurality of pseudo error generating devices.

Abstract: A method for testing a storage apparatus, which includes: (a) writing a specific pattern to a storage unit of a storage apparatus; (b) reading the specific pattern written to the storage apparatus; (c) determining an error bit number of the specific pattern read in the step (b); and (d) determining that the storage unit has defect when the error bit number is larger than a error bit threshold value, wherein the error bit threshold value is smaller than a correctable bit number for a error correction code corresponding to the specific pattern.

Abstract: Methods and systems are provided for dynamic adjustment of the forward-link frame error rate (FFER) target. In accordance with an exemplary embodiment, a base station provides service to at least one mobile station on a carrier in a wireless coverage area using a first FFER target. The base station calculates an Ec/Ior value for the carrier in the wireless coverage area. The base station then selects a second FFER target based at least in part on the calculated Ec/Ior value. Thereafter, the base station provides service to at least one mobile station on the carrier in the wireless coverage area using the second FFER target.

Abstract: Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal.

Abstract: In a digital broadcast receiver, when a bit error rate (BER) is larger than a threshold in a BER determining part, power is supplied to a first tuner and a second tuner for diversity reception. When the BER is smaller than the threshold, power supply to one of the first tuner and the second tuner is stopped for single reception. This structure allows power supply to one of the tuners to be stopped in excellent reception environments, thus reducing power consumption.

Abstract: In a preferred embodiment, the invention provides a circuit for reducing bit error rates. A data recovery circuit recovers data from a first HSS link to differential bit pair inputs. Data from the differential bit pair outputs of the data recovery circuit drive differential bit pair inputs to a plurality of FIFOs. The data is then driven from a parallel output of the plurality of FIFOs to the parallel input of a synchronizer. The data is then driven from the parallel output of the synchronizer to the parallel input of a serializer. The serializer, through different bit pair outputs, drives a second serial HSS link.

Abstract: A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (BIST) circuitry. The built-in, at-speed BERT provides a low-cost solution for production testing of high-speed serial links, facilitating jitter analysis and evaluation of pre-emphasis and equalization performance. This further allows adaptation of pre-emphasis and equalization.

Abstract: The invention proposes a method for controlling a variable of transmission between a mobile network element and a fixed network element, wherein the transmission is effected by repeatedly sending of data units, and a control of the variable of the transmission based on a target data unit error rate is performed, the method comprising the steps of detecting (S2), whether a received data unit includes an error, analyzing (S3), in case an error is detected, the transmission number of the data unit, detecting (S4), whether the analyzed diversity of the data unit is equal to a target transmission number, and forwarding (S5) the data unit to a network control element in case the transmission number of the data unit is equal to the target transmission number, or in case no error is detected. The invention also proposes a corresponding fixed network element and a corresponding network control element.

Abstract: An approach is provided for bit error rate characterization. A test signal representing one or more Ethernet frames exhibiting a particular bit error rate is generated. The test signal is output to a device under test. Traffic is received from the device under test. A determination is made as to whether a link failure condition exists at a port on an Ethernet switch.

Abstract: The distortion component of an optical signal received from an optical transmission system, such as an all-optical system, subject to noise and amplitude distortion components, can be evaluated by a method that utilises information derived from analysing the bit error ratio (BER) of the signal as a function of a movable threshold. The analysis is performed in high and low bit error ratio areas of the eye diagram used for data one/zero decision making. The intersections with the threshold axis (where BER=0.25) of extrapolations of the high and low bit error ratio values provide variables V1 and V2 which are divided (V1/V2) to obtain an estimate/prediction of the amplitude closure of the eye diagram resulting from amplitude distortion. The analysis is preferably carried out after Q conversion of the BER values. The method can also be extended to provide indications of Q, bit error ratio and optical signal-to-noise ratio within the signal.

Abstract: A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the testing signals to an input of the under-test circuit for predetermined measurements. A testing circuit and testing method achieve the same jitter injection as conventional high-speed testing instruments, but save testing cost.

Abstract: Embodiments of the invention relate to diagnosing error-correcting retries of an upper system by using a disk drive under control of the upper system. In one embodiment, a microprocessor can operate in any of at least two operation modes. One is normal operation mode while the other is pseudo failure operation mode. Mode switching is made by a switch. Strictly, the pseudo failure operation mode includes three different operation modes: 1) pseudo logical error report mode in which a pseudo logical error is reported to the upper system without performing disk control; 2) pseudo component circuit failure mode in which a control circuit is forced to cause a failure by setting invalid control values to the control circuits; and 3) pseudo interface failure mode in which a pseudo interface failure in the system comprising multiple disk drives is reported by setting an invalid control value to the interface control circuit.

Abstract: A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a particular decoder processing speed. The system and method may also be used to indicate proper adjustment direction by displaying real-time error measurements during encoder alignment. The system measures a logic state width error and calculates alignment parameters, processing speed and a safety factor. The method allows a measured logic state width error to be used to calculate a minimum required processing speed and safety factor.

Abstract: Self-synchronizing techniques for checking the accuracy of a pseudorandom bit sequence (PRBS) are provided. The PRBS being checked may be generated by a device (e.g., a device under test) in response to a PRBS received by the device (e.g., from a PRBS generator). In an aspect of the invention, a PRBS checking technique includes the following steps/operations. For a given clock cycle, the presence of an error bit in the PRBS generated by the device is detected. The error bit represents a mismatch between the PRBS input to the device and the PRBS output from the device. Then, propagation of the error bit is prohibited for subsequent clock cycles. The prohibition step/operation may serve to avoid multiple errors being counted for a single error occurrence and/or masking errors in the PRBS output by the device.

Abstract: A non-volatile memory system comprises a non-volatile memory and a memory controller controlling the non-volatile memory. The non-volatile memory has a pseudo pass function of returning a pass as a status even if a bit error reaching allowable number of bits occurs after at least one of a write or erase sequence is completed. The memory controller has an allowable bit change function of changing the upper limit value of the allowable number of bits.

Abstract: Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.

Abstract: An apparatus and method for decision threshold control in an optical signal receiver. A forward error correction (FEC) decoder provides a feedback signal representative of corrected errors. The decision threshold is adjusted to balance a number of corrected ones and zeros.

Abstract: A weighted defect estimating apparatus and a related method for determining a defect estimation value are disclosed. The weighted defect detecting apparatus includes: a defect detecting unit for generating a defect value when a defect in a predetermined region of an optical disc is detected; a weighting circuit, electrically connected to the defect detecting unit, to generate a weighted defect value according to the defect value and a weighting factor corresponding to a location of the defect on the optical disc; and a computing module, electrically connected to the weighting circuit, for computing the defect estimation value according to a plurality of weighted defect values corresponding to the predetermined region.

Abstract: A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.

Abstract: A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detector.

Abstract: The present invention is directed to a data recording method of notifying degree of deterioration of recording medium thus to perform stable recording operation. Even in the case where uncorrectable address read error does not exist, deterioration information is displayed in accordance with generated and stored deterioration information. Whether or not address read error of ATIP is detected over successive two frames or more, or whether or not four errors or more are detected on the average at 75 frames is discriminated. In the case where error detecting state is adapted to affirmative discrimination condition, warning is displayed. In the case where 200 errors or more detected from deterioration information generated in processing with respect to random missing with respect to written data exist on the average with respect to successive 750 frames, or in the case where one error or more detected in processing with respect to random missing exist, disc deterioration warning display is similarly performed.

Abstract: A reception error rate controller in which the settling time can be shortened at the time of feedback control by controlling the quality of a received signal when the error rate is low. The reception error rate controller identifies the received signal by comparing it with a reference value, detects the error rate of the identified signal, controls the reference value based on the error rate and further controls the quality of the received signal based on the error rate.

Abstract: An apparatus for monitoring asynchronous transfer mode cells in the communication system is proper for recognizing state information of asynchronous transfer mode cells transceiving between a base transceiver station and a base station controller. Accordingly, the apparatus enables to monitor the contents of the cell by comparing VPI/VCI of the ATM cells inputted to the multiplexing/demultiplexing part to the other VPI/VCI latched hardware, have the cell bus RX I/F count the number of the error-occurring ATM cells by carrying out header error checks of the ATM cells inputted to the cell bus RX I/F itself, and find out how long the cell transferring time takes for transceiving loop is found out by transceiving the test ATM cells between the multiplexing/demultiplexing part being the ATM low rate subscriber multiplexing/demultiplexing board assembly (ALMA) and the base transceiver station.

Abstract: A system and method for efficiently correcting block errors in packet-based digital communications are provided whereby the ratio of redundant symbols/message symbols over the length of a data packet decreases in order to more efficiently use available bandwidth. The reduction of this ratio, and subsequently the change in a corresponding framing schedule, may be determined through negotiations between the transmitting device and the receiving devices. Each receiving device calculates a redundancy requirement based on signal-to-noise ratio samples. This requirement is returned to the transmitting device in the form of a schedule request. The transmitting device determines if a new framing schedule is needed based on the schedule request, and communicates this new framing schedule to the receiving device. Once the receiving device acknowledges receipt of the new schedule, the transmitting device switches to the new framing schedule for future data packet transmissions.

Abstract: A system and method for measuring and utilizing a pseudo pixel error rate in digital data transmission is disclosed. As an alternative to measuring actual pixel error rate measurement, the present invention uses a pseudo pixel error rate detection scheme where the errors occurred in the special character patterns used in data encoding are measured. A particular embodiment uses a de-glitch filter for filtering the glitches from an unfiltered data enable (DE), a delay for delaying the unfiltered DE to match the delay of the de-glitch filter, and a comparator for comparing the unfiltered DE and the filtered DE to determine the occurrence of an error. It further includes a counter to count the errors occurred.

Abstract: An apparatus and method for measuring the bit error ratio of a transmission system is provided, which can accurately report the degradation of the service quality of a line to an operator by accurate BER calculation under an exceptional situation where an excessive error is instantaneously generated. This is preferably accomplished by storing the number of bit errors in buffers at an interval of time T, scoping these buffers by a sliding window of a preset size, and judging whether or not an E-BER alarm is generated using the average number of bit errors of the scoped sliding window buffers. In addition, it is also possible to intermittently report an error repair situation under which an error is generated by scoping buffers by a sliding window of a set size and judging whether or not an E-BER alarm is cleared using the average number of errors of the scoped sliding window buffers, for thereby accurately and rapidly operating the system.

Abstract: A cable line quality evaluating method for evaluating a quality of a cable line for transmitting a digital modulation signal in a bidirectional manner comprises the steps of extracting a noise signal of an upstream line from one of a cable line connection point for evaluating a head end of the cable line evaluated in the quantity and the cable line evaluated in the quantity and a connection point between a tap-off and the cable line evaluated in the quality, generating a pseudo random signal, modulating a carrier signal of its predetermined frequency by means of the pseudo random signal, and then outputting the modulated signal as a test carrier, outputting an output signal obtained by adding the noise signal of the upstream line and the test carrier, selectively receiving the signal of its predetermined frequency from the output signal, and modulating the selectively received signal, and comparing the modulated signal with the pseudo random signal in bits, and then measuring a bit error rate.

Abstract: A method of measuring a Q-value according to a mean value and standard deviation of a signal level distribution of input data comprises: a first step for calculating a difference between bit error rates of input data sampled by a plurality of threshold values which are a little different from each other; a second step for calculating a difference between the difference data obtained in the first step; and a third step (steps 118 and 120) for calculating a mean value and standard deviation of the signal level of input data when data obtained in the first and the second step (steps 100 to 116) are utilized.

Abstract: A method of simple network synchronization in a bus extension system with expanded capabilities wherein a plurality of independently-operable multimedia multiplexing devices are connected to the same network in parallel. The method of network synchronization for multiplexing devices connected by parallel through an extension bus is provided wherein one of two or more multiplexing devices is used as a clock master and other remaining multiplexing devices as slave devices and wherein the multiplexing device acting as the clock master is operated in synchronization with a clock received from a network while the multiplexing devices acting as the slave devices receive a clock from a clock transmission line of the extension bus which is outputted after the clock master has established synchronization with the network clock and regenerate a clock leading the received clock in phase.