Abstract: Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.

Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

Abstract: A memory apparatus is disclosed, comprising a memory device under test, a reduced-pin-count device and a built-in self test device. The reduced-pin-count device is used to find a faulty cell address in the memory device under test during a pre-fuse stage. The built-in self test device is used to detect whether the memory device under test has any error during a post-fuse stage. The memory apparatus is capable of promptly finding the address of a defect cell in the memory device under test such that repairs can be performed during a fuse stage. Furthermore, the invention reduces the pin count required during testing the memory device under test. Thus, the cost of testing equipment is reduced and the performance of memory testing is enhanced.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one of a plurality of signals transmitted from each of the corresponding ones of the plurality of processors so as to generate a plurality of loop back signals. A plurality of signal transmission paths are configured to carry a corresponding one of the plurality of signals from one of the plurality of processors to another of the plurality of processors, and a plurality of comparators compare the plurality of loop back signals to the plurality of transmission signals so as to enable the validity of each of the plurality of signals to be assessed.

Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Abstract: A loopback connector for a system can include a connector arrangement connectable to connector of a system component and/or a cable. The loopback connector can include loopback logic for simulating cable and/or system component functionality. In an example implementation the loopback connector can also operate to protect a system component and/or cable connector during shipping.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: A system and method for loopback self testing. A system includes a host device and an endpoint device. The host device transmits unencoded test symbols. The endpoint device loops back the unencoded test symbols to the host device. The host device drives at least some bits of each unencoded test symbol onto host device data signals and drives at least some bits of each unencoded test symbol onto host device control signals.

Abstract: A test circuit can use a simple test pattern data without customization for each substrate and considerably reduce a test preparation process. A connection test circuit is generated by receiving the input of the data of the connection relation indicating the devices mutually line-connected among a plurality of devices, the number of connection lines corresponding to the respective connection relations, and the device outputting a test result, sequentially searching for a connection destination device from the output terminal of an output device, and embedding a test circuit module in a test route.

Abstract: A switch apparatus providing with a loop detection function sets a port identification to a port which activates the loop detection function, only receives the loop detection frame by a high-order port in the switch apparatus connected with a backbone network or a high-order switch apparatus on the basis of the port identification set previously, and controls an inactivation of a sending source low-order port that sent the loop detection frame, when the loop detection frame is received by the high-order port.

Abstract: In a system and method for testing a serial attached small computer systems (SAS) interface of a SAS controller, the SAS controller connects to a loopback dongle via the SAS interface. The SAS interface sends a first data packet to the loopback dongle, and receives a second data packet from the loopback dongle. If information in the second data packet is the same as information in the first data packet, the system and method transmits a first notification indicating that the SAS interface is functioning normally. Otherwise, the system and method transmits a second notification indicating that the SAS interface is not functioning normally.

Abstract: The present application describes a method and system for testing the compliance of a PCIE expansion system to verify that data signals transmitted through multiple data lanes in the expansion system comply with the PCIE requirements. The method for testing a PCIE expansion system comprises delivering the data signals from the data lanes to a compliance board that is configured to loop back at least a first portion of the data signals and transmit a complementary second portion of the data signals to a testing device, and testing a compliance of the second portion of the data signals with the PCIE requirements. The first portion of the data signals is then tested through a second compliance board that is configured to loop back the second portion of the data signals and transmit the first portion of the data signals to the testing device.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Abstract: The present invention implements a method and apparatus for using components within a Serializer/DeSerializer (SerDes) to emulate the effects of a backplane in order to facilitate automated test equipment (ATE) testing of the SerDes. The SerDes includes a transmitter pre-emphasis circuit (TPXE) that pre-emphasizes a transmitted signal and a receiver equalization circuit (RXEQ) that equalizes a received signal. The TPXE includes coefficients that are dynamically programmable.

Abstract: A burn-in test circuit according to the present invention includes a scan chain formed by a plurality of scan flip-flips connected in series, a circuit under test input with an output from one of the plurality of scan flip-flops as an activation signal, and a scan chain loop circuit being configured to an output signal of the scan chain determined according to an output of the circuit under test back to the scan chain.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: The ‘IP Diagnostics’ software is a new and innovative method of aiding the deployment and troubleshooting of IP enabled POS terminals. Its purpose is to identify where a failure in the IP connection is occurring. The IP Diagnostics application does this by testing major failure points within the IP chain from the POS terminal to the host.

Abstract: A system and method for monitoring network traffic utilizing a small form pluggable (SFP). The SFP is activated in a customer premise equipment (CPE) device in response to a user inserting the SFP in the CPE device. A determination is made whether a service provider is authorized to access the SFP. Monitoring is implemented for the service provider in response to the determining.

Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Abstract: Embodiments of the present invention provide a protocol tester for performing a protocol test, said protocol tester exhibiting an input for the feeding in of data, a protocol decoding device for the decoding of data, and an output for providing the decoded data, the protocol tester also comprising a device for measuring the bit error rate. A corresponding method for performing a protocol test is also provided.

Abstract: A method of and a system for autonomously identifying which node in a two-node system has failed are described. The system includes two nodes and a fault-tolerant communication fabric. The fabric defines a plurality of communication paths connecting the two nodes, and fault-tolerant loop-back communication in which each node can send a message to itself utilizing at least one switch structure of the fabric. In addition, each of the two nodes includes logic for performing the service; logic for testing the functionality of the respective node; logic for sending test result messages to both nodes; fault-isolation logic for analyzing test result messages from both nodes; and logic for disabling the other node from performing the service only if the fault-isolation logic determines that the respective node is capable of successfully performing the service and also determines that the other node is incapable of successfully performing the service.

Abstract: A system and method for self-test of an integrated circuit are disclosed. As one example, an integrated circuit is disclosed. The integrated circuit includes a digital signal processing chain, a random sequence generator coupled to an input of the digital signal processing chain, and a checksum calculator coupled to an output of the digital signal processing chain.

Abstract: A system for operating a data storage device having a plurality of sectors and at least one port, each port having a transmitter and a receiver, is disclosed. In one embodiment the system includes coupling at least one of the transmitters to at least one of the receivers, providing power to the data storage device, detecting that the transmitter is coupled to the receiver, and executing code for exercising the data storage device.

Abstract: There is provided a method of testing a first device using a tester. The method includes receiving test data having a pattern by the first device from the tester; detecting the pattern of the test data by the first device; generating first data, by the first device, according to the pattern detected by the detecting; comparing the test data with the pattern detected by the detecting; determining errors in the test data, by the first device, based on the comparing; inserting the errors into the first data to generate error-inserted first data; and transmitting the error-inserted first data by the first device to the tester. The method may further include generating a first clock at the first device; wherein the transmitting uses the first clock for transmitting the error-inserted first data.

Abstract: A data storage device includes a plurality of sectors and a port, the port having a transmitter and a receiver. In one embodiment a method includes coupling the transmitter to receiver, providing power to the data storage device, detecting that the transmitter is coupled to the receiver, and executing code for exercising the data storage device.

Abstract: A testing circuit includes a signal generator operative to provide a control signal in response to a reference clock signal. The control signal may include both alignment and timing information operative to synchronize the timing and output of the signal generator with a device under test. A clock recovery instrument is electrically coupled to the signal generator. The clock recovery instrument generates the reference clock signal in response to a clock signal from the device under test. The reference clock signal is synchronized with the clock signal from the device under test such that signal generator operation is synchronized with the device under test independent of the behavior of the device under test.

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract: A semiconductor integrated circuit includes: an input/output cell that is included in a path captured during propagation delay testing and that has an output-stage buffer on an output bus; and a terminal connected to the output bus and an input bus of the input/output cell. An external load or a testing device is connectable to the terminal. The input/output cell has a switching part that is capable of switching between a first path that loops back at an output side of the output-stage buffer and a second path that loops back at an input side of the output-stage buffer. The first path is selected during normal operation and the second path is selected during the propagation delay testing.

Abstract: Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example the acknowledgment is performed by initiating loopback communications from a first agent to a second agent, sending a packet including a redundant acknowledgment sequence from the first agent to the second agent, receiving the packet including the redundant acknowledgement sequence looped back from the second agent at the first agent, sending a test sequence from the first agent to the second agent, and receiving the test sequence looped back from the first agent.

Abstract: A device and a method for testing SAS channels which are applied to a plurality of pairs of SAS interfaces. The testing device includes a control terminal, a PCI-E microprocessor, a PCI-E-to-SAS adaptor, and a signal feedback module. The control terminal is used for selecting SAS channels and sending a control command; the PCI-E microprocessor is used for receiving the control command and sending a test signal to a PCI-E channel according to the control command; the PCI-E-to-SAS adaptor is used for converting a transmission signal between the PCI-E channel and the SAS channels; and the signal feedback module is used for connecting a first SAS interface to a second SAS interface in the SAS back plate. The PCI-E microprocessor compares whether the test signal sent to the first SAS channel is consistent with the test signal received from the second SAS interface.

Abstract: A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detecting module is integrated with the semiconductor device, samples values of the output signal, and outputs the sampled values to the test module.

Abstract: A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be inoperable during a first operational mode of the interface and operable during a second operational mode of the interface. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.

Abstract: In a communication system based on OSI (Open Systems Interconnection) Reference Model, a pattern body generation circuit of a transmitting device generates and outputs a jitter test pattern body for jitter test. A selector selects an output (frame data) of a transmitting-end upper circuit during normal communication and selects an output (pattern body) of the pattern body generation circuit during jitter test. A transmitting-end MAC circuit performs transmitting-end processing of a MAC layer on the data selected by the selector to thereby obtain a MAC frame. A receiving-end MAC circuit performs receiving-end processing of a MAC layer on a received frame in MAC frame format to thereby obtain a payload. A pattern body verification circuit verifies a pattern body that is a payload obtained by the receiving-end MAC circuit during jitter test against a corresponding pattern body before transmission.

Abstract: An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner apparatus. An LSI has a plurality of interfaces (IFs) for transmission/reception of data with an external device, and the LSI includes an emulation control unit for allowing one of the two of the plurality of IFs to perform an operation of emulating an IF of a connection partner device having operation specifications different from those of the LSI, when two IFs are connected to each other via a transmission line.

Abstract: A method according to one embodiment may include communicating, by a far end device with a near end device, using a Serial ATA (SATA) communications protocol; receiving, by the far end device, a SATA signal sequence having two bits, the state of which define at least one loopback mode; defining, by the far end device, a reserved and/or error state if both of the bits are set; and processing, by the far end device, the two bits together to determine if the two bits are in a state that defines at least one loopback mode or if the two bits are set. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: An integrated circuit 2 having a data receiver circuit 14 for a serial data signal also includes a test data generating circuit 24 for self-test purposes. The test generating circuit includes a filter circuit 230, 32, 34, 36 which processes an input test serial data signal to generate an output test serial data signal having enhanced inter-symbol interference for loopback to the data receiver circuit so as to test that data receiver circuit.

Abstract: A loopback module is disclosed in which N differential High Speed Serial (HSS) digital data input channels are received and sent to a serial to parallel converter, whose output is M-bit wide parallel data. By doing so, the effective data rate is divided down by M to 1/M “fabric” speeds. If the channels contain an embedded clock, the clock is extracted. The parallel data is then sent to a non-blocking crossbar switch, which is able to route any of the N M-bit parallel data inputs to any of Q parallel data outputs by effectively utilizing one multiplexer for each parallel output. Each parallel data output of the crossbar is sent to a parallel to serial converter, whose output is a high speed serial output. Each high speed serial output is fed into a jitter generator circuit, and then to an output driver.

Abstract: Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel.

Abstract: Methods and apparatus for aligning the transmitters of two or more bidirectional ports of an integrated circuit (IC), particularly an application-specific IC (ASIC) or field-programmable gate array (FPGA). Misalignment of two or more transmitters is determined by the IC itself without the use of external test equipment. Receivers of the bidirectional ports whose transmitters are to be aligned are used by the IC to detect misalignment. Any misalignment of the receivers is also determined and either eliminated or taken into account when aligning the associated transmitters. Variants for ICs with and without internal loop-back capability and for ICs with and without differential outputs are described.

Abstract: The present application describes a method and system for testing the compliance of a PCIE expansion system to verify that data signals transmitted through multiple data lanes in the expansion system comply with the PCIE requirements. The method for testing a PCIE expansion system comprises delivering the data signals from the data lanes to a compliance board that is configured to loop back at least a first portion of the data signals and transmit a complementary second portion of the data signals to a testing device, and testing a compliance of the second portion of the data signals with the PCIE requirements. The first portion of the data signals is then tested through a second compliance board that is configured to loop back the second portion of the data signals and transmit the first portion of the data signals to the testing device.

Abstract: In a mobile device having a primary baseband circuit and a secondary baseband circuit and an interface between the primary baseband circuit and a secondary baseband circuit, a method for testing the interface and primary and secondary baseband circuits comprising the steps of: setting the secondary baseband circuit into a loopback mode; sending a test signal from the primary baseband circuit to the secondary baseband circuit; receiving at the primary baseband circuit a second signal, the second signal being the first signal looped back from the secondary baseband circuit; and comparing the second signal with an expected result.

Abstract: A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator; and determining parametric information pertaining to the I/O circuit of the device under test from the phase signal.

Abstract: Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check operations. Such apparatus and methods facilitate subsequent checks for data gain of erased memory cells using abbreviated procedures compared to normal erase operations.

Abstract: An apparatus for determining the amount of skew injected into a high-speed data communications system, including a plurality of lanes having a data bus per lane, relative to a reference lane, for system skew compensation. By knowing the relative amount of skew that each lane requires for alignment, an appropriate amount of skew is then injected on each lane to provide alignment and thus compliancy with the SFI-5 and SxI-5 standards, in terms of data skew specifications. The relative skew amounts for each transmitting lane are determined using dual loopback methods.

Abstract: A method for testing a processor subassembly includes providing a computer system comprising subassemblies. Each subassembly includes processors having internal communication paths and ports that provide external communication paths to other subassemblies via a midplane circuit board. For each subassembly, a first port is connected to a second port via the midplane circuit board, thereby re-routing external communication paths back to the subassembly instead of to other subassemblies and allowing communication between the processors through external paths. Each subassembly can be tested one at a time.

Abstract: There is provided a method of testing a first device using a tester. The method comprises receiving test data having a pattern by the first device from the tester; detecting the pattern of the test data by the first device; generating first data, by the first device, according to the pattern detected by the detecting; comparing the test data with the pattern detected by the detecting; determining errors in the test data, by the first device, based on the comparing; inserting the errors into the first data to generate error-inserted first data; and transmitting the error-inserted first data by the first device to the tester. The method may further comprise generating a first clock at the first device; wherein the transmitting uses the first clock for transmitting the error-inserted first data.