Abstract: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the applied data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the first group. A second group of the applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals to determine whether the group, although shifted in time, was nonetheless correctly captured. Expect data signals are generated in this manner and may be utilized in a variety of integrated circuits, such as an SLDRAM.

Abstract: A semiconductor device having multiple memory circuits of varying sizes includes scan test circuitry that enables the memories to be simultaneous loaded with pattern data and tested. A first memory circuit has a first memory, a first address scan chain that receives serial scan-in address data and generates a first address signal, and a first data scan chain that receives serial scan-in data and generates a first data input signal. A second memory circuit has a second memory, a second address scan chain that receives the serial scan-in address data and generates a second address signal, and a second data scan chain that receives the serial scan-in data and generates a second data input signal.

Abstract: A memory testing method tests a memory by writing test data to and reading test data from the memory. Data is successively read from the memory is synchronism with a clock and the data is compared. The memory testing method then judges a defect in the memory based on a result of the comparison.

Abstract: A method is presented for self-test and self-repair of a semiconductor memory device. Prior to the self-repair stage, both redundant and regular memory portions are comprehensively tested, preferably using a checkerboard bit pattern. Faulty rows identified in each memory portion during testing are recorded. Known-bad rows in regular memory are then replaced by known-good redundant rows in the self-repair stage, and the resulting repaired memory is retested for verification. Compared to existing methods, the new method is believed to provide improved test coverage, making it both more effective in identifying non-repairable memory devices and less prone to fail repairable ones.

Abstract: A system for recreating a data background to test memory designs for macros includes a macro, a first multiplexer, and a second multiplexer. The macro includes a plurality of flip-flops. The first multiplexer has a first input coupled to the macro output and a second input coupled to an inverted version of the macro output. The first multiplexer receives a control signal that selects between the macro output and the inverted version of such output to produce a first multiplexer output. A second multiplexer, coupled to the first multiplexer output and a normal scan input signal, receives a select signal that selects between the first multiplexer output and the normal scan input signal to generate a second multiplexer output, which is coupled to the macro input. A method for recreating a data background to test memory designs for a macro size defined by a plurality of flip-flops also is described.

Abstract: A method is provided to perform spatial locality testing on a memory array having a logical address map distinct from its physical address map. The built-in self-test generator performs memory spatial locality tests on the memory array by generating adjacent physical memory row addresses that are then converted to corresponding logical memory row addresses. Once the physical memory row address is converted to its corresponding memory row address the test vector is written to the logical memory row address to perform spatial locality tests on adjacent physical memory row addresses of the memory array.

Abstract: An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling inside the memory circuit is required.

Abstract: A wafer burn-in test mode circuit is described. In a wafer burn-in test mode, an output at respective stages may be decoded using a single address signal in a shift register to minimize the number of an address necessary to decode a test item. Therefore, the limit of a burn-in apparatus having a small number of a channel may be overcome. Various test items may be supported with only a single address signal.

Abstract: A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.

Abstract: A semiconductor integrated circuit device with fault analysis function performs test operation for a memory circuit (such as a RAM) in which a comparison control circuit (6) generates a comparison control signal CCMP in order to select one or more memory cells in each memory cell group (34, 35, 36 and 37) corresponding to a single bit, a specified row, a specified bit, or a specified pattern, and then outputs the comparison control signal CCMP to scan flip flops (2, 3, 4 and 5) each including a comparator (292). The comparator (292) performs the comparison operation between data and expected values EXP and then outputs a comparison result only when address signals are input and data are red from memory cells, as the object of test, addressed by these address signals.

Abstract: A method of testing RAM without destroying the stored data consists of looping through the locations to be tested (21, 28, 29), and at each location, inverting the data stored in the location (22), loading the inverted data from the location to a register (23), inverting the data in the register (24), writing the twice-inverted data back to the location (25) and comparing the actual content of the location with the content of the register (26). The test fails (27) if any of the comparisons fails, whereupon the test can be terminated. The test succeeds (30) if the all of the locations have been tested without any of the comparisons having failed. Further tests may be carried out at a selected location only, to test for short circuits between data bus leads. The method contains fewer memory access operations that the conventional method, so it will be faster. The method will also detect bits that can be changed but not changed back again, as well as stuck bits.

Abstract: The present invention relates to a method and an article of manufacture for differentiating between an in-circuit programming read-only memory (“ROM”) and a ROM emulator for purposes of in-circuit programming. In one aspect, the invention relates to a method to determine whether a software program is executing in a non-volatile memory device or an emulator. The method includes reading a binary representation of a first value stored at a predetermined test location and changing the binary representation of the first value to create a binary representation of a second value. The method further includes writing the binary representation of the second value to the test location and reading a resulting value stored at the test location. The method further includes determining whether the resulting value corresponds to the first value or the second value.

Abstract: It is one object of the present invention to eliminate redundant testing steps from an operation for testing the search function of a content addressable memory having a priority encoder. Before testing is conducted, background data that differ from test data are written (step 21). Then, the background data are read (step 22) and are tested (step 23). The address having the lowest priority is designated (step 26). And the test data are written thereto (step 27). Following this, the search operation is performed (step 28) to determine whether test addresses match search addresses (step 29). Then, the address having the second lowest priority is designated (step 26), and the above processing is repeated for all the addresses (step 32).

Abstract: A built-in self-test (BIST) circuit in a DRAM has a test mode controller including a mode counter for selecting based on the count thereof one of a plurality of test modes, and a plurality of test signal generators for generating test control signals based on the selected test mode. A RAM interface executes test of the DRAM based on the test control signals and based on the addresses supplied from an address counter, which counts up or down based on the selected test mode. A plurality of test modes constitutes a test pattern such as column bars, checker board and marching.

Abstract: A pattern generator for generating a test pattern that has a repetition rate higher than the basic repetition rate thereof to test a synchronous memory. The test pattern to be provided to a memory under test can be accurately modified by inverting the pattern data as a function of address data.

Abstract: Disclosed is a method of testing memory, comprising providing one or more semiconductor wafers having one or more semiconductor chips thereon, each said chip comprising one or more memory cells, providing a programmable testing apparatus comprising at least one test pattern generators and a test bed adapted to receive said one or more wafers in communicative contact so as to address individual memory cells, chips, and wafers and transmit information thereto and receive information therefrom, receiving one or more test commands, constructing a test sequence of one or more commanded tests from said test commands, constructing at least one header comprising location information for each said wafer, chip and memory cell, testing said memory cells with a test pattern generated by said test pattern generator, collecting the results of said testing and passing them to a display device, passing said location information to said display device, constructing and displaying a graphical representation of said test result

Abstract: The cell array of a semiconductor memory, in particular of a DRAM, has word lines and bit lines, whose intersections define the cells of the cell array. A test data pattern is written to all the cells of a word line at the same time.

Abstract: A memory device testing apparatus has a pattern generator, which generates all of the signals used for a packet signal in one cycle, a pin data selector, which generates the packet signal by selecting some of the signals generated by the pattern generator and outputting the selected signals a plurality of times, a memory device socket, which can write test data into the memory device and read test data from the memory device, and a comparator, which compares expectation value data with test data.

Abstract: A test pattern generator for generating a plurality of test patterns to test a memory comprising: a control memory for storing plural kinds of control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for alternately storing vector instructions read out from vector memory and bank memories; an address expander for generating an address of each of control instructions in control memory in accordance with vector instructions stored in a plurality of bank memories; and a test pattern calculator for generating test patterns based on control instructions read out from an address generated by an address expander stored in the control memory.

Abstract: There are disclosed methods and apparatus for testing memory components for faults, defects or the like, by generating a testing sequence that produces various bit combinations as well as current changes, that when coupled, stresses or fatigues the memory component, and allows for the evaluation of single bits. The testing sequence is provided in cycles, formed of complement word pairs of N bit words. The first, or initial, cycle typically includes a first word of all binary zeros. Successive or subsequent cycles include a shifted bit in each subsequent first word. The testing pattern is written into the memory component(s) under test and corresponding words are read from the memory component(s). The written and read words are then compared, with this comparison analyzed for detection of faults, defects or the like in the memory component(s).

Abstract: A test circuit comprised of a microprogram controlled control unit for generating a test pattern (addresses and data) for each memory in accordance with a predetermined algorithm and reading written data, an arithmetic unit, and data determining means for determinating the read data and outputting the result of determination is provided over a semiconductor chip equipped with a memory.

Abstract: A method and system for testing a memory in operation. A storage unit is used to temporarily free one memory location in the memory, making it possible to check this memory location for bit errors. Data intended for the selected memory location is stored in the storage unit, and instead a test pattern is written into the memory location to be tested and read out again, all in coordination with the normal operation of the memory. If the pattern read from the test location does not match the written test pattern, an alarm is raised.

Abstract: A method for providing specific test programs from a production test program for testing semiconductor devices, in accordance with the present invention, includes providing a semiconductor device to be tested by a tester and initiating a production test program. The production test program includes a plurality of program files and test code sequences. The production test program is held at a test which is to be extracted, and register information and settings are extracted from the tester for the test to be extracted. The register information and settings are stored in a storage file, and the storage file is assembled and translated to provide an executable test program for an extracted test for testing the semiconductor device or other semiconductor devices.

Abstract: An associative memory of the TRIE type is organised in the form of registers of 2K cells having a portal register from which binary strings are analyzed in successive slices of K bits. Each non-empty cell contains either a pointer or a reference. This reference is issued after the analysis has followed a path formed by the cells designated by the successive slices of K bits in the registers designated by the pointers encountered in these cells in succession. The data is stored in the TRIE memory in response to commands to insert and delete binary patterns of variable length, each associated with a reference, so that when a bit string is analyzed, the reference issued is that associated with the longest of the binary patterns coinciding with the start of the string being analyzed.

Abstract: A method of generating a test bit pattern for a memory device is provided. The method includes, for example, the steps of loading a data register with an initial test bit pattern and storing the initial test bit pattern in the memory device. The method also includes the steps of generating a additional test bit patterns by shifting the initial test bit pattern by a predetermined number of bits and storing the additional test bit pattern in the memory device. The step of shifting the initial test bit pattern includes, for example, the step of pushing a one or two-bit pattern into the initial test bit pattern. Subsequent successive test bit patterns are similarly generated by pushing a one or two-bit pattern into the previously generated test bit patterns. Hence, the number of bits loaded into the data register is greatly reduced and the required test bit pattern still generated.

Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.

Abstract: A pattern generator for use in a memory tester to provide packet address and data signals to a packet-based memory-under-test is disclosed. The pattern generator includes an address source for generating an external packet memory address signal. The external packet memory address signal represents a plurality of addressable memory elements in the memory-under-test. A plurality of data generators are disposed in parallel relationship and coupled to the output of the address source to receive at least a portion of the packet memory address signal. Each of the data generators has logic operative to derive an internal address from the packet address. The internal address corresponds to an individual memory element within the memory under test. A sequencer is disposed at the outputs of the data generators to distribute the data generator outputs in a packet waveform for application to the memory-under-test.

Abstract: A memory test circuit having access control circuits (11 and 12, or 21 and 22, or 31 and 32) recognizes a first memory circuit (101) and a second memory circuit (102), as one continuous memory, incorporated in a semiconductor processing device based on addresses and control commands provided from an external device. The memory test circuit then executes a memory test operation for the first and second memory circuits (101 and 102) continuously.

Abstract: The present invention discloses a memory testing apparatus. The testing apparatus can be embedded on a chip with embedded memory block or a memory chip to reduce the testing time of memory blocks or memory devices. Through the selection of testing modes and the data processing of the processing device, the correctness of the output data of a memory block can be represent with the data state of a verifying data. The data output can be pre-processed and simplified as the verifying data to reduce the test time.

Abstract: A semiconductor apparatus is composed of a signal providing circuit and a data analyzer. The signal providing circuit provides an input signal set including at least one input signal. The data analyzer outputs a digital result signal in synchronization with a clock signal. The data analyzer inverts the digital result signal at a timing indicated by the clock signal while the input signal set is in a predetermined state, and does not invert the digital result signal while the input signal set is not in the predetermined state.

Abstract: A method for testing bus connections of electronic circuits, in particular memory components, selects address and data bit test patterns such that, in a first step of write and read steps, respectively, the bits in the address bit test pattern have a first binary value and, in the first step of write steps, the bits in the data bit test pattern have a second value and, for each following step, starting with the lowest-value or highest-value bit, the respective adjacent bit is assigned a binary value which is complementary to that in the preceding step until, in the final step, all the bits in the address or data bit test pattern have a complementary value.

Abstract: Image data of a test pattern is transmitted to an image processor and image processing is effected by the image processor based on the test pattern. The image outputted (the results of the image processing) from this test pattern image processing and the original image are compared to each other. If they are different, the image processing by the current image processor is judged to be abnormal. In this case, the image processor (hardware process) is switched promptly and automatically to be emulated by an auto set-up engine (software process). Further, in the image processor section, ordinarily, three frame memories are used to effect processes including reading of image data, image processing, and outputting of image data at the same time and in parallel. Image processing can be switched in such a manner that when any one of the frame memories is judged to be abnormal, the two remaining frame memories judged as normal are used to execute image processing.

Abstract: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of these applied data signals have been properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group of applied data signals. A second group of the applied data signals are then captured after the first group. The second group of applied data signals are determined to have been properly captured when the second captured group of applied data signals corresponds to the group of expect data signals. In this way, when capture of the applied series of data signals is shifted in time from an expected initial capture point, subsequent captured groups of applied data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured.

Abstract: A structure and method for testing multi-port SRAM cells includes a test controller connected to at least one multi-port SRAM cell (the test controller is adapted to store a pattern into the multi-port SRAM cell and generate a stability test restore clamp), a read/write controller connected to the multi-port SRAM cell (the read/write controller is adapted to simultaneously activate a plurality of wordline ports on the multi-port SRAM cell while the stability test restore clamp is enabled), and a timing control circuit connected to the read/write controller. The timing control circuit is adapted to vary an activation time of the wordline ports. The read/write controller reads from the multi-port SRAM after the stability test restore clamp is deactivated. The read/write controller activates the wordline ports for each multi-port SRAM cell in an array sequentially while all bitlines in the array are held on by the stability test restore clamp.

Abstract: DRAM memory unit is tested for a series of cell faults such as: the stuck-at fault (SAF), the stuck-open fault (SOF), the transition fault (TF), the multiple address fault (MAF) as well as storage capacitor leakage, subthreshold leakage or junction leakage. Predetermined data pattern is written throughout the DRAM memory, locations in one region of the memory are “frozen” while a disturbance is created in a second region during an interval sufficient for a defective cell in the first region to lose its charge, following which the locations of the first region are sequentially read to verify if any cell has lost its data.

Abstract: A semiconductor memory device according to the present invention includes: a test mode setting circuit capable of serially setting a plurality of test modes in accordance with an external signal; a voltage generating circuit; a column related control circuit; a row related control circuit; and a memory cell array. In a corresponding test mode, odd-numbered word lines/even-numbered word lines are brought into a selection/non-selection state. In the corresponding test mode, a voltage of the bit line is set higher (an internal power supply voltage) or lower (a ground voltage) than an equalization voltage in a normal operation mode. Thus, a checker pattern can efficiently be written.

Abstract: Disclosed herein is a semiconductor memory device that includes a memory cell array and a plurality of pads for providing data to and from the memory cell array. A plurality of input/output line pairs corresponds to the plurality of pads. A reading means reads out the data from the memory cell array through the plurality of input/output line pairs and pads. A switch control circuit generates sequential switch control signals during a test mode. A switch control means receives the data from the reading means during the test mode. The switching means sequentially transfers the data to a representative pad responsive to the switch control signals. The present invention allows testing for defective memory cells at a wafer level using a limited number of probe needles.

Abstract: A memory test circuit in which time required for a memory test is reduced is disclosed. A memory test circuit according to the present invention is provided with stripe data generating means for generating stripe data composed of plural bits based upon a block address signal, means for writing the above stripe data to a predetermined address of a memory, means for reading information written to the above predetermined address of the memory and compare means for judging whether the above read information is the same as the stripe data or not. The above stripe data generating means generates stripe data in a cycle 2 in response to a first state of the above block address signal and generates stripe data in a cycle 4 in response to a second state of the block address signal.

Abstract: This invention describes a method to test both auto-refresh and self refresh of an SDRAM. The method writes a logical zero in to a single cell on each word line using a write with auto-precharge and increments an internal counter with either auto-refresh or self refresh to select the row address. The test is performed using existing circuitry on the SDRAM, and when testing self refresh, the refresh cycle is exited shortly after a cell on a row has been written into so as to not run the entire refresh cycle and save test time. A test signature is formed by the logical zeros written into one cell along each word line. Comparing this signature with the signature that should exist provides an easy way to determine if there is a test error and where the error occurred.

Abstract: A path under test is selected from a semiconductor integrated circuit that has been designed by a scan method. A test pattern is generated for the selected path so that the path is sensitized and a signal, passing through the path, changes its level at a time before or after a capture clock pulse is input to the circuit. Next, the test pattern generated is transformed into a normal scan pattern. Also, an expected output value, which should result from the test pattern input, is obtained. Then, the test pattern is input to the path under test and the resultant output value is compared to the expected value. In this manner, the path can be tested in such a manner as to see whether or not any hold error will occur.

Abstract: A method and apparatus for built in self test, BIST, of content addressable memory, CAM, and associated random access memory, RAM, is described. The method and apparatus may most beneficially be used for difficult to test situations such as embedded CAM or other memory types. There are no external memory read operations to determine the contents of a memory location, so little additional circuitry or overhead, such as separate read ports, is required on the embedded memory for implementation of the BIST. Only a number generator, a shift register and an OR gate with inputs from each of the CAM word match lines are added to the circuit in which the memory is embedded. The test uses a set of unique data patterns, each one spaced from the others by two bit locations, a walking inversion test, and a complement and reverse pattern test to determine what type of error and the error location.

Abstract: A system for continuous monitoring and autonomous detection of patterns in the main memory subsystem of a computer system. The invention can be embodied as an extension to existing memory scrubbing hardware to permit stored code pattern analysis and identification during the autonomous transparent memory scrubbing process. A library of stored target signatures is provided to which code signatures are compared during analysis. Code signatures may be derived directly from the memory subsystem data pattern or may be indirectly and more efficiently derived from the error correction code (ECC) string associated with the stored data pattern. This invention is directly applicable to computer virus detection and neutralization systems.

Abstract: Built-in tests included in reset functions of single board computers can be rapidly performed to confirm adequate functionality without additional hardware support by disabling an error correcting code function in a memory controller, writing a pattern of predictable parity to a location in memory and reading and correcting the pattern with the error correcting code function of the memory controller re-enabled. Thus, resets caused by, for example, momentary soft errors or power interruptions can be executed within rigid time constraints and thus negligibly short interruptions of processor function.

Abstract: An improved method and structure for generating addresses of a memory array facilitates the testing of a memory cell by generating the address of any adjacent memory cell to the memory cell under test. The address generation provides for movement to any adjacent memory cell, in any direction, including north, south, east, west, northeast, northwest, southeast, and southwest. The address of any memory cell, even the address of a non-adjacent memory cell, may be selectively generated by exercising a programmable initialization feature.

Abstract: To provide a semiconductor memory device having an ECC circuit whereof checker-data inspection of memory cells in the user areas and the ECC areas can be performed at once, the ECC code generation circuit generates the ECC code of six bits whereof logic of each bit has XOR logic of each of six different combinations of 15 bits of the data set of 32 bits, and addresses in every user areas of the bit-columns are arranged in an order of 1, 4, 2, 5, 3, 6, . . . , b, f. When a checkerboard pattern is written, a first data set having 32 bits of logic ‘0’ and a second data set having 32 bits of logic ‘1’ are written alternately, in addresses 4n to 4n+3 and 4(n+1) to 4(n+1)+3 of the user areas on odd-numbered word-lines, and written alternately on even-numbered word-lines in an inverse order of the odd-numbered word-lines, when checker-data inspection of the memory-cell array is performed, n being an integer not less than 0.

Abstract: A test pattern which has an outputted image obtained by said image processing executing normal image processing is used to self-judge an image processor. Namely, image data of the above described test pattern is transmitted to the image processor and image processing is effected by the image processor. The image outputted (the results of the image processing) from this image processing and the original image are compared to each other. When they do not correspond to each other, the image processing by the current image processor is judged to be abnormal. In this case, the image processing using the image processor (hard ware process) is switched promptly and automatically to be emulated by an auto set-up engine (soft ware process). Further, in the image processor section, ordinarily, all of the three frame memories are used to effect processes including reading of image data, image processing, and outputting of image data at the same time and in parallel.

Abstract: Disclosed herein is a semiconductor device having a semiconductor memory circuit whose operation is tested in combination with an external test means to specify defective portions produced in a memory section of the semiconductor memory circuit and shorten the time necessary for its test.

Abstract: A multiple bank memory device is described which can be tested by accessing the multiple memory banks simultaneously. The memory includes a test mode trigger which initiates a test which writes and reads from memory cells located in different memory banks. Error detection circuitry evaluates data read from different memory banks and determines if a defect is present in the memory cells. Different test patterns and techniques are described for identifying defective memories.

Abstract: A test method for a cache memory of a multiprocessor system. The multiprocessor system has a shared memory structure accessed via a system bus, including a multiplicity of processor modules, each acting as a master of the bus and each having a cache module, and a shared memory module for storing data shared by the processor modules. The test method includes dividing the cache memory into a test region, to be tested, and a code region, to store a program, positioning a test program in the shared memory at a place corresponding to the code region of the cache memory, and reading the test program stored in the shared memory and writing the test program in the code region of the cache memory to perform the test program. Accordingly, the total cache region is divided into a test region and a code region, and then only the test region is tested, to thereby enhance the test performance.

Abstract: Testing time of interconnections is reducted by splitting up the collection of connection paths to be tested into two or more groups. A set of test vectors, which is applied to each of the groups concurrently, is arranged to insure that the two adjacent connections that are assigned to different groups are not tested concurrently. The user can select the number of groups, and the number of connection paths within each group (which need not be the same for all groups). The disclosed algorithm increases the number of connection paths that are tested with each concatenated test vector, and consequently the number of required test vectors is reduced.