Error Mapping Or Logging Patents (Class 714/723)
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Patent number: 9384124Abstract: According to one embodiment, a data storage device includes a first controller, a second controller, and a third controller. The first controller performs a control operation of writing data of a first data unit to a storage area in a flash memory and reading the data of the first data unit from the storage area. The second controller carries out migration processing of measuring a data amount of valid data stored in storage areas of a second data unit that is a data erase processing unit.Type: GrantFiled: December 19, 2012Date of Patent: July 5, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Taichiro Yamanaka, Yoko Masuo, Hironobu Miyamoto
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Patent number: 9336075Abstract: There is provided a monitoring apparatus (1) including: an acquisition unit (10) that acquires failure information indicating that a failure has occurred in any of a plurality of monitoring targets; a notification job determination unit (20) that determines whether or not a predetermined user has to be notified of the failure which is specified by the failure information; and a display unit (40) that displays failure notification information indicating occurrence of the failure when the acquisition unit (10) acquires the failure information, and displays notification job information indicating that there is a job to notify the failure to a predetermined user when the notification job determination unit (20) determines that notification has to be issued.Type: GrantFiled: May 30, 2012Date of Patent: May 10, 2016Assignee: NEC CorporationInventor: Teruya Ikegami
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Patent number: 9305663Abstract: Examples are disclosed for assessing pass/fail status of non-volatile memory. In some examples, information may be received to indicate a block having memory pages associated with non-volatile memory cells. The information may indicate at least some of the memory pages have bit errors in excess of an error correction code (ECC) ability to correct. For these examples, the block may be selected for read testing. Read testing may include programming the memory pages with a known pattern and waiting a period of time. Following the period of time each memory page may be read and if a resulting pattern read matches the known pattern programmed to each memory page, the memory page passes. The block may be taken offline if the number of passing memory pages is below a pass threshold number. Other examples are described and claimed.Type: GrantFiled: December 20, 2013Date of Patent: April 5, 2016Assignee: NetApp, Inc.Inventors: Joshua Silberman, George Totolos, Richard Strong
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Patent number: 9230687Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.Type: GrantFiled: April 22, 2013Date of Patent: January 5, 2016Assignee: International Business Machines CorporationInventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
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Patent number: 9170302Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first chip compresses first test data of the first chip and outputs the compressed first test data through the first data channel in a first test mode, and the second chip compresses second test data of the second chip and outputs the compressed second test data through the second data channel in the first test mode.Type: GrantFiled: June 17, 2011Date of Patent: October 27, 2015Assignee: SK Hynix Inc.Inventor: Ki Up Kim
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Patent number: 9165684Abstract: A fault bits scrambling memory and method thereof relate to a memory including at least one memory bank. The memory bank includes a memory module, a scrambling-logic unit, a self-testing unit and a scrambling code generating unit. The memory module includes a plurality of pages. Each page has a plurality of memory cells, and each memory cell has a physical address. The scrambling logic unit receives a scrambling code and the physical address to generate a mapping address by logical calculation, and outputs the mapping address to the memory module. The self-testing unit detects the faulty memory cells of each page. The scrambling code generating unit is applied to generate the scrambling code to maintain the number of the faulty memory cells corresponding to the mapping address of the same page is up to a maximum tolerance.Type: GrantFiled: March 31, 2014Date of Patent: October 20, 2015Assignee: National Taiwan University of Science and TechnologyInventors: Shyue-Kung Lu, Hao-Cheng Jheng
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Patent number: 9136843Abstract: TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate.Type: GrantFiled: July 30, 2014Date of Patent: September 15, 2015Assignee: Industrial Technology Research InstituteInventors: Pei-Ling Tseng, Keng-Li Su, Chih-Sheng Lin, Shyh-Shyuan Sheu
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Patent number: 9128143Abstract: A semiconductor device failure analysis system according to an embodiment of the present invention includes a memory configured to be capable of retaining an initial display information; and a control unit configured to generate a first image based on a configuration information of the semiconductor device and a plurality of fail bit information of the semiconductor device, the semiconductor device including a three-dimensional memory cell array, and to generate a second image from the first image based on the initial display information, the second image corresponding to part of the plurality of fail bit information. The semiconductor device failure analysis system according to the embodiment further includes a display configured to be capable of initially displaying the second image.Type: GrantFiled: March 14, 2013Date of Patent: September 8, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Mami Kodama, Yoshikazu Iizuka
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Patent number: 9063853Abstract: A storage device disclosed in the present application includes a device-error-codes table, first-information indicating a process-setting that can be changed by a device-state, and second-information indicating a process-setting that is a previously determined by a device-error-type, are associated with each other; a management-unit that adds information indicating a change in the second-information to the second-information stored in the table; a determining-unit that determines the device-error-type; an acquiring unit that acquires, from the table, the first-information; an information-converter that determines whether or not information indicating a change in the second-information, and changes the first-information by the acquiring unit; a transmitter that transmits the first-information by the acquiring unit or changed by the information-converter to a storage-device-controller; and an information-transmitter that receives, from the controller, a request to transmit the second-information and transmits,Type: GrantFiled: March 26, 2012Date of Patent: June 23, 2015Assignee: FUJITSU LIMITEDInventor: Hironori Kai
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Patent number: 9058256Abstract: A data writing method for a rewritable non-volatile memory module is provided. The method includes selecting at least one physical erasing unit as a global random area and building a global random area searching table for recording update information corresponding to updated logical pages that data stored in the global random area belongs to. The method also includes receiving updated data belonging to a logical page; and determining whether a data dispersedness degree corresponding to the global random area is smaller than a data dispersedness degree threshold. The method further includes, if the data dispersedness degree corresponding to the global random area is smaller than the data dispersedness degree threshold, writing the update data into the global random area and recording update information corresponding to the logical page in the global random area searching table.Type: GrantFiled: August 7, 2013Date of Patent: June 16, 2015Assignee: PHISON ELECTRONICS CORP.Inventor: Chih-Kang Yeh
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Patent number: 9049492Abstract: A portable terminal wherein the amount of processing and power consumption when performing repair is reduced and video data can be reliably repaired, and video data repair method and program of the same. The portable terminal is provided with a video data repairer that repairs video data in which video is poor by replacing it with a portion of video data acquired from an external source, said video data repairer saving, without deleting at the time of repairing, all of partial video data necessary to decode subsequent video data continuing after the video data to be repaired, and performing control so that only the portion of the video data that is repaired is re-encoded.Type: GrantFiled: December 28, 2009Date of Patent: June 2, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Masaki Takahashi, Toshio Oka, Ryo Yokoyama, Satoshi Senga
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Patent number: 9043663Abstract: An apparatus is equipped with a storage device including an error correction circuit. The apparatus performs a test of the storage device according to a predetermined testing procedure, and records a time-point at which error correction of the storage device has been performed by the error correction circuit during performance of the test. The apparatus determines, with predetermined accuracy, a first position within the storage device on which the error correction has been performed, based on a test speed at which the test is performed, a time-period from the time-point to current time, and a second position within the storage device on which the test is being performed at the current time. Then, the apparatus performs the test predetermined times on a range included in the storage device and including the first position, according to a testing procedure that has been used at the time-point.Type: GrantFiled: June 4, 2013Date of Patent: May 26, 2015Assignee: FUJITSU LIMITEDInventors: Katsuhiko Minotani, Takahiro Osada, Hirokazu Ohta
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Publication number: 20150143188Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a control unit, is disclosed to include at least the following steps. A transaction is appended to a bad-column table each time a bad column of a block within the storage unit is inspected. It is determined whether a total number of the transactions within the bad-column table is odd when the control unit determines that the last column of the block is a regular column. A transaction is appended to the bad-column table to indicate that the last column of the block is a bad column when the control unit determines that the total number of the transactions within the bad-column table is odd.Type: ApplicationFiled: July 9, 2014Publication date: May 21, 2015Inventor: Han-Cheng HUANG
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Publication number: 20150143187Abstract: A method and apparatus are provided for implementing enhanced performance with read before write to phase-change-memory. Each write to PCM is preceded by a read and a calculation to discover a location of any bad bits. The write data is converted to a format that can be corrected for a given number of previously undiscovered bit errors, and the writes are unverified.Type: ApplicationFiled: November 19, 2013Publication date: May 21, 2015Applicant: HGST Netherlands B.V.Inventors: Robert Eugeniu Mateescu, Dejan Vucinic, Cyril Guyot
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Patent number: 9037921Abstract: The relative health of data storage drives may be determined based, at least in some aspects, on data access information and/or other drive operation information. In some examples, upon receiving the operation information from a computing device, a health level of a drive may be determined. The health level determination may be based at least in part on operating information received from a client entity. Additionally, a storage space allocation instruction or operation may be determined for execution. The allocation instruction or operation determined to be performed may be based at least in part on the determined health level.Type: GrantFiled: March 29, 2012Date of Patent: May 19, 2015Assignee: Amazon Technologies, Inc.Inventors: Marc J. Brooker, Tobias L. Holgers, Madhuvanesh Parthasarathy, Danny Wei
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Patent number: 9037930Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.Type: GrantFiled: February 19, 2013Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
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Publication number: 20150135028Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.Type: ApplicationFiled: January 23, 2015Publication date: May 14, 2015Inventors: Benjamin Zorn, Ray Bittner, Darko Kirovski, Karthik Pattabiraman
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Publication number: 20150128000Abstract: In a method of operating a memory system including a memory device and a memory controller, the memory controller reads fail information from a fail info region included in the memory device. The memory controller maps a logical address related to a program to a physical address of a safe region based on the fail information to store the program in the safe region except the fail info region and a fail region included in the memory device. The memory controller loads the program into the safe region of the memory device according to the address mapping. The method of operating the memory system according to example embodiments increases the performance of the memory system.Type: ApplicationFiled: November 3, 2014Publication date: May 7, 2015Inventors: Ju-Yun JUNG, Min-Yeab CHOO, Do-Geun KIM, Mi-Kyoung PARK, Dong-Yang LEE, Sun-Young LIM, Bu-Il JUNG, Hyuk HAN
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Publication number: 20150121157Abstract: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.Type: ApplicationFiled: October 28, 2013Publication date: April 30, 2015Applicant: SanDisk Technologies Inc.Inventors: Deepak Raghu, Gautam A. Dusija, Chris Avila, Yingda Dong, Man Mui, Xiying Costa, Pao-Ling Koh
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Patent number: 9015463Abstract: A memory device includes a non-volatile memory configured to store a repair data and output the repair data in response to an initialization signal, a plurality of registers configured to store the repair data outputted from the non-volatile memory, a plurality of memory banks configured to replace normal cells with redundant cells by using the repair data stored in corresponding registers among the plurality of registers, a verification circuit configured to generate a completion signal for informing that transfer of the repair data from the non-volatile memory to the plurality of registers is completed, and an output circuit configured to output the completion signal to a device other than the memory device.Type: GrantFiled: August 31, 2012Date of Patent: April 21, 2015Assignee: SK Hynix Inc.Inventors: Jeongsu Jeong, Youncheul Kim, Gwangyoung Stanley Jeong, Bokmoon Kang
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Patent number: 9009550Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.Type: GrantFiled: December 10, 2012Date of Patent: April 14, 2015Assignee: Texas Instruments IncorporatedInventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady
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Patent number: 9003247Abstract: Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block.Type: GrantFiled: April 28, 2011Date of Patent: April 7, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Naveen Muralimanohar, Doe Hyun Yoon, Jichuan Chang, Parthasarathy Ranganathan, Norman Paul Jouppi
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Patent number: 8996936Abstract: A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position.Type: GrantFiled: January 23, 2012Date of Patent: March 31, 2015Assignee: Sandisk Technologies Inc.Inventor: Saravanakumar Sevugapandian
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Patent number: 8990646Abstract: An error test routine tests for a type of memory error by changing a content of a memory module. A memory handling procedure isolates the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure are to be performed at runtime transparent to an operating system. Information corresponding to isolating the memory error is stored.Type: GrantFiled: May 31, 2012Date of Patent: March 24, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Naveen Muralimanohar, Norman Paul Jouppi, Melvin K Benedict, Andrew C. Walton
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Patent number: 8990647Abstract: Memory devices and methods include a stack of memory dies and a logic die. Method and devices include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are included.Type: GrantFiled: March 4, 2013Date of Patent: March 24, 2015Assignee: Micron Technology, Inc.Inventor: Joe M. Jeddeloh
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Publication number: 20150082106Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.Type: ApplicationFiled: October 20, 2014Publication date: March 19, 2015Inventor: Michael A. Shore
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Publication number: 20150074476Abstract: A data storing system performs a test operation on a memory block on which a read operation is determined to be failed, and determines whether the memory block is or is not a bad block based on a result of the test operation. The data storing system may improve reliability and yield of a device.Type: ApplicationFiled: February 24, 2014Publication date: March 12, 2015Applicant: SK hynix Inc.Inventor: Eui Jin KIM
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Publication number: 20150067421Abstract: A dispersed storage processing unit selects a slice length for a data segment to be stored in a dispersed storage network (DSN). The data segment is encoded using a dispersed storage error coding function to produce a set of data slices in accordance with the slice length. A storage file is selected based on the slice length. A storage file identifier (ID) is generated that indicates the storage file. A set of DSN addresses are generated corresponding to the set of data slices, wherein the set of DSN addresses each include the storage file ID and a corresponding one of a plurality of offset identifiers (IDs). The set of data slices are written in accordance with the set of DSN addresses. A directory is updated to associate the set of DSN addresses with an identifier of the data segment.Type: ApplicationFiled: June 26, 2014Publication date: March 5, 2015Applicant: CLEVERSAFE, INC.Inventors: Andrew Baptist, Ilya Volvovski, Wesley Leggette, Greg Dhuse, Jason K. Resch
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Patent number: 8972822Abstract: A memory module includes a plurality of memory chips stacked on top of one another, each of the plurality of memory chips including a memory cell unit that is divided into a plurality of blocks, and an address scrambling circuit that processes an input address signal and that selects a block to be operated.Type: GrantFiled: November 13, 2012Date of Patent: March 3, 2015Assignee: Fujitsu LimitedInventors: Rikizo Nakano, Osamu Ishibashi, Sadao Miyazaki
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Patent number: 8972776Abstract: An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the non-volatile memory. The controller is configured to (i) write data using the R-blocks as a unit of allocation and (ii) perform recycling operations selectively on either an entire one of the R-blocks or a portion less than all of one of the R-blocks.Type: GrantFiled: March 7, 2013Date of Patent: March 3, 2015Assignee: Seagate Technology, LLCInventors: Leonid Baryudin, Alex G. Tang, Earl T. Cohen
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Patent number: 8966330Abstract: When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors.Type: GrantFiled: May 29, 2014Date of Patent: February 24, 2015Assignee: SanDisk Technologies Inc.Inventors: Deepak Raghu, Gautam Dusija, Chris Avila, Yingda Dong, Man Mui
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Patent number: 8943270Abstract: In tiered storage subsystems in which pages are automatically allocated to appropriate storage media based on the access frequency in page units, since the number of storage media is not simply proportional to the performance, it was difficult to design in advance a tier configuration satisfying the required performance. According to the present invention, a cumulative curve of I/O distribution is created based on a result of measurement of I/O accesses performed to the storage subsystem, and RAID groups (RG) are allocated sequentially in order from RGs belonging to tiers having higher performances to the cumulative curve of I/O distribution. When either a performance limitation value or a capacity of the RG exceeds the cumulative curve of I/O distribution, a subsequent RG is allocated, and the process is repeated so as to compute the optimum tier configuration.Type: GrantFiled: July 24, 2012Date of Patent: January 27, 2015Assignee: Hitachi, Ltd.Inventors: Hideki Nagasaki, Hirokazu Ogasawara, Taro Ishizaki
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Publication number: 20150019923Abstract: A method, computer readable medium, and system independently managing network applications within a network traffic management device communicating with networked clients and servers include monitoring with a network device a plurality of applications communicating over a plurality of direct memory access (DMA) channels established across a bus. The network device receives a request from a first application communicating over a first DMA channel in the plurality of DMA channels to restart the first DMA channel. In response to the request, the first DMA channel is disabled with the network device while allowing other executing applications in the plurality of applications to continue to communicate over other DMA channels in the plurality of DMA channels. A state of the first DMA channel is cleared independently from other DMA channels in the plurality of DMA channels, and communications for the first application over the first DMA channel are resumed with the network device.Type: ApplicationFiled: January 19, 2010Publication date: January 15, 2015Applicant: F5 NETWORKS, INC.Inventors: Timothy Michels, Clay Jones
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Publication number: 20150019926Abstract: An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.Type: ApplicationFiled: July 17, 2014Publication date: January 15, 2015Inventors: Yu Kou, Lingqi Zeng
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Patent number: 8935467Abstract: A memory system that includes a memory device and a memory controller. The memory device includes a plurality of memory cells, and a first storage unit configured to store information about a weak cell from among the plurality of memory cells. The memory controller is configured to transmit an operation command signal to the memory device, and control an operation of the memory device by using the information about the weak cell provided from the first storage unit. If the operation command signal is related to an operation to be performed using a first of the memory cells and the first memory cell is the weak cell, the memory device is configured to transmit the information about the weak cell to the memory controller.Type: GrantFiled: November 14, 2012Date of Patent: January 13, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hak Soo Yu, Joo Sun Choi, Hong Sun Hwang
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Patent number: 8930327Abstract: In production applications that process and transfer secure and sensitive customer data, the heap dump files of these applications, which may be useful for debugging production issues and bugs, may contain secure and sensitive information. Thus, to make the useful debugging information available in heap dumps from production applications without compromising secure client data to those assigned to debugging and fixing production issues, these heap dumps may be scrubbed of sensitive information without scrubbing information that is useful for debugging.Type: GrantFiled: April 28, 2011Date of Patent: January 6, 2015Assignee: salesforce.com, inc.Inventors: Fiaz Hossain, Zuye Zheng
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Publication number: 20150006985Abstract: A data storage device may be configured with at least one data sector sync mark. Various embodiments are generally directed to a data sector having a sync mark and stored on a data storage medium with the sync mark having either a first or second patterns and a sync circuit configured to distinguish between the two different patterns to identify a status of at least some other portion of the data sector.Type: ApplicationFiled: June 26, 2013Publication date: January 1, 2015Inventor: Bumseok Park
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Patent number: 8924832Abstract: A data storage system configured to efficiently search and update system data is disclosed. In one embodiment, the data storage system can attempt to correct errors in retrieved data configured to index system data. Metadata stored along with user data in a memory location can be configured to indicate a logical address associated in a logical-to-physical location mapping with a physical address at which user data and metadata are stored. The data storage system can generate modified versions of logical address indicated by the metadata and determine whether such modified versions match the physical address in the logical-to-physical mapping. Modified versions of the logical address can be generated by flipping one or more bits in the logical address indicated by the metadata. Efficiency can be increased and improved performance can be attained.Type: GrantFiled: June 26, 2012Date of Patent: December 30, 2014Assignee: Western Digital Technologies, Inc.Inventor: Johnny A. Lam
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Publication number: 20140372816Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.Type: ApplicationFiled: December 22, 2011Publication date: December 18, 2014Inventors: Kuljit S. Bains, Klaus J. Ruff, George Vergis, Suneeta Sah
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Patent number: 8910002Abstract: A test-ahead feature for non-volatile memory-based mass storage devices to anticipate device failure. The test-ahead feature includes a method performed with a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device. At least a first block is reserved on the at least one non-volatile memory device as a wear-indicator block and a plurality of second blocks are used for data storage. Information is stored corresponding to the number of write and erase cycles encountered by the second blocks during usage of the mass storage device, and the information is accessed to perform wear leveling among the second blocks. The wear-indicator blocks are subjected to an offset number of write and erase cycles in excess of the number of write and erase cycles encountered by the second blocks, after which an integrity check of the first block is performed.Type: GrantFiled: August 24, 2010Date of Patent: December 9, 2014Assignee: OCZ Storage Solutions Inc.Inventor: Franz Michael Schuette
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Patent number: 8897109Abstract: Embodiments described herein are directed to a virtual repair of digital media using a virtual repair service. Digital media stored on a digital media device is read using a media player. A request is received by a virtual repair unit from the media player to perform a virtual repair of a segment of unreadable digital content of the digital media. The virtual repair unit retrieves a readable copy of the digital content corresponding to the segment of unreadable digital content identified in the request from a media repository using the virtual repair unit. The virtual repair unit transmits the readable copy of the digital content to the media player for insertion into a buffer of the media player.Type: GrantFiled: July 11, 2013Date of Patent: November 25, 2014Assignee: Xerox CorporationInventor: Gavan Leonard Tredoux
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Patent number: 8892969Abstract: Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.Type: GrantFiled: December 27, 2013Date of Patent: November 18, 2014Assignee: Micron Technology, Inc.Inventor: Michael Murray
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Patent number: 8887013Abstract: A memory device includes a memory array with random defective memory cells. The memory array is organized into rows and columns with a row and column identifying a memory location of a memory cell of the memory array. The memory device includes a row address device and a column address device and is operative to use a grouping of either the row or the column addresses to manage the random defective memory cells by mapping the memory location of a defective memory cell to an alternate memory location.Type: GrantFiled: July 1, 2011Date of Patent: November 11, 2014Assignee: Avalanche Technology, Inc.Inventors: Siamack Nemazie, Ebrahim Abedifard
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Patent number: 8887012Abstract: The present invention provides a method and apparatus for saving and restoring soft repair information. One embodiment of the method includes storing soft repair information for one or more cache arrays implemented in a processor core in a memory element outside of the processor core in response to determining that a voltage supply to the processor core is to be disconnected.Type: GrantFiled: August 24, 2010Date of Patent: November 11, 2014Assignee: Advanced Micro Devices, Inc.Inventors: Bill K. Kwan, Atchyuth K. Gorti, Norm Hack, David Kaplan
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Patent number: 8887014Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.Type: GrantFiled: December 11, 2012Date of Patent: November 11, 2014Assignee: International Business Machines CorporationInventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras-Montano, Moinuddin K. Qureshi
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Patent number: 8874981Abstract: An exemplary method of creating a target storage layout table referenced for partitioning a storage space of a storage device includes following steps: identifying defective storage areas in the storage space of the storage device, and accordingly generating an identification result; and creating the target storage layout table according to the identification result.Type: GrantFiled: October 27, 2010Date of Patent: October 28, 2014Assignee: Mediatek Inc.Inventors: Meng-Chang Liu, Chen-Tsung Hsieh
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Patent number: 8866502Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.Type: GrantFiled: February 17, 2011Date of Patent: October 21, 2014Assignee: Broadcom CorporationInventors: Arya Reza Behzad, Ahmadreza Rofougaran, Sam Ziqun Zhao, Jesus Alfonso Castaneda, Michael Boers
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Patent number: 8868601Abstract: A method, system, and computer program for consolidating data logged in log files in a network of servers, each server running at least one application that logs data into files on the server, the method comprising: providing a consolidating message queue for receiving the log data and file name; intercepting log data being written into a log file by a file system and sending that log data and the file name of the log file to a consolidating message queue; receiving the log data and file name in a consolidating message queue; and saving the log data in the consolidating message queue from all the servers to a consolidated file or data structure associated with the file name.Type: GrantFiled: July 20, 2010Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventor: Richard Leigh
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Patent number: 8862953Abstract: A method includes directing an access of a memory location of a memory device to an error correction code (ECC) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location. The method further includes determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.Type: GrantFiled: January 4, 2013Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Marc A. Gollub, Girisankar Paulraj, Diyanesh B. Vidyapoornachary, Kenneth L. Wright
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Patent number: 8862952Abstract: A data storage system configured to perform prioritized memory scanning for memory errors is disclosed. In one embodiment, the data storage system prioritizes scanning for memory errors based on a quality attribute of pages or zones of a non-volatile memory array. Pages or zones having quality attributes that reflect a lower level of reliability or endurance than other pages or zones are scanned more frequently for memory errors. When memory errors are discovered, the quality attribute of pages or zones can be adjusted to reflect a lower level of reliability or endurance. In addition, stored data can be recovered before it may become permanently lost and before a host system reads the stored data. Improved performance of the data storage system is thereby attained.Type: GrantFiled: March 16, 2012Date of Patent: October 14, 2014Assignee: Western Digital Technologies, Inc.Inventors: Jing Booth, Andrew J. Tomlin