Abstract: A device and method for controlling an inverter is disclosed. The inverter-controlling device in accordance with the present disclosure determines an operation state of a switching element of an initial charging module based on predetermined time durations and a magnitude of a DC link voltage measured at each of time points corresponding to the predetermined time durations.

Abstract: A system includes at least two capture devices, each switchable from a respective idle mode to a respective recording mode upon receipt of a trigger signal from a trigger via a network. A controller saves data packets generated by the capture devices during the respective idle modes to a short-term memory, and saves data packets generated during the respective recording modes to a long-term memory such that the data packets form respective saved data streams. The synchronizer sends a sync signal to the capture devices via the network. The compensator determines respective delay periods between sending of the sync signal by the synchronizer and receipt of the sync signal by each of the capture devices, and transfers from the short-term memory to the long-term memory any data packets generated during the respective delay period.

Abstract: Provided is a multiphase converter having a plurality of voltage conversion units, and is configured to protect the faulty phase and continue driving using another phase when an abnormality occurs in any phase. A DC-DC converter includes a plurality of voltage conversion units that are in parallel between an input-side conductive path and an output-side conductive path. A control unit subjects the plurality of voltage conversion units to a test operation in which a duty ratio of a PWM signal for each voltage conversion unit is changed. The control unit identifies an abnormal voltage conversion unit based on at least one of the states of the electric current, the voltage, and the temperature of the multiphase conversion unit during this test period, and causes the remaining voltage conversion unit other than the identified abnormal voltage conversion unit to perform voltage conversion.

Abstract: A data recorder stores endpoint activity on an ongoing basis as sequences of events that causally relate computer objects such as processes and files. When a security event is detected, an event graph may be generated based on these causal relationships among the computing objects. For a root cause analysis, the event graph may be traversed in a reverse order from the point of an identified security event (e.g., a malware detection event) to preceding computing objects, while applying one or more cause identification rules to identify a root cause of the security event. Once a root cause is identified, the event graph may be traversed forward from the root cause to identify other computing objects that are potentially compromised by the root cause.

Abstract: Disclosed are systems and methods related to a noise reduction device employing an analog filter and a corresponding inverse digital filter. The combination and placement of the filters within the systems aids in reducing noise introduced by processing the signal. In some embodiments, the combination of filters may also provide for increased flexibility when de-embedding device under test (DUT) link attenuation at higher frequencies. Further, the filters are adjustable, via a controller, to obtain an increased signal to noise ratio (SNR) relative to a signal channel lacking the combination of filters. Additional embodiments may be disclosed and/or claimed herein.

Abstract: A self-test capable integrated circuit apparatus includes a pattern generator, a results store and testable logic. The testable logic includes a plurality of scan channels, each of the channels being respectively coupled between the pattern generator and the results store. A self-test controller is arranged to supervise a self-test in respect of the testable logic to generate self-test result data, the self-test result data being stored in the results store. A processing resource is coupled to the self-test controller and coupled between the pattern generator and the results store, the processing resource being capable of evaluating the self-test result data stored in the results store. The testable logic includes the processing resource, arranged to cooperate with the self-test controller. The processing resource is able, subsequent to the self-test, to evaluate the self-test result data.

Abstract: An apparatus is described having instruction execution logic circuitry. The instruction execution logic circuitry has input vector element routing circuitry to perform the following for each of three different instructions: for each of a plurality of output vector element locations, route into an output vector element location an input vector element from one of a plurality of input vector element locations that are available to source the output vector element. The output vector element and each of the input vector element locations are one of three available bit widths for the three different instructions. The apparatus further includes masking layer circuitry coupled to the input vector element routing circuitry to mask a data structure created by the input vector routing element circuitry. The masking layer circuitry is designed to mask at three different levels of granularity that correspond to the three available bit widths.

Abstract: Example automatic test equipment (ATE) includes: a per-pin measurement unit (PPMU); logic configured to execute a state machine to control the PPMU; memory that is part of, or separate from, the logic; and a control system to command the logic; where, in response to a command from the control system, the state machine is configured to obtain, at a known interval or ATE event, data that is based on an output of a measurement by the PPMU and to store the data in the memory, or to output data to the PPMU from the memory at a known interval or synchronous to an event.

Abstract: A method for testing. An external clock frequency is generated. Test data is supplied over a plurality of SSI connections clocked at the external clock frequency, wherein the test data is designed for testing a logic block. A DSTA module is configured for the logic block that is integrated within a chip to a bandwidth ratio, wherein the bandwidth ratio defines the plurality of SSI connections and a plurality of PSI connections of the chip. The external clock frequency is divided down using the bandwidth ratio to generate an internal clock frequency, wherein the bandwidth ratio defines the external clock frequency and the internal clock frequency. The test data is scanned over the plurality of PSI connections clocked at the internal clock frequency according to the bandwidth ratio, wherein the plurality of PSI connections is configured for inputting the test data to the plurality of scan chains.

Abstract: Devices, systems and methods are provided which comprise testing of a non-volatile memory concurrently during at least a part of a testing of other system parts by a processor. In some examples, a device includes a processor, a non-volatile memory, a test controller, and at least one further circuit part. In a test mode, the processor is configured to test the at least one further circuit part, and wherein the test controller is configured to test the non-volatile memory concurrently with at least part of the testing of the at least one further circuit part.

Abstract: A display device is provided. A data line includes a main line section, a first line section and a second line section spaced apart from one another. The first and second line sections respectively cross over a first scan line set to form first and second crossing regions. The main line section crosses over a second scan line set to form third crossing regions. The first line section is electrically connected to the main line section and one scan line of a third scan line set via a first switch element. The second line section is electrically connected to the main line section and another scan line of the third scan line set via a second switch element. First pixel units, second pixel units and third pixel units correspond respectively to the first crossing regions, the second crossing regions and the third crossing regions.

Abstract: The method includes identifying, by one or more computer processors, elements of a test case, wherein elements include components that provide parameters of the test case. The method further includes assigning, by one or more computer processors, a score for each component of the one or more identified elements. The method further includes determining, by one or more computer processors, a priority score for each of the one or more test cases based upon the assigned score for each component of the one or more identified elements, wherein the priority score is a representation of a measure of importance for each one of the one or more tests case by a user.

Abstract: Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.

Abstract: According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.

Abstract: A method for testing a device under test with regard to spherical coverage is described, wherein a device under test is placed in an anechoic space to which a measurement antenna is assigned. A spherical coverage test is performed. The spherical coverage test is stopped after a minimum test criteria has been fulfilled. Further, a test system is described.

Abstract: A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series.

Abstract: A method for detecting damage of a solder joint of a printed circuit board of an electronic product by using a device for detecting damage of an electronic product according to the present invention includes: generating a digital signal and applying the digital signal to the solder joint of the printed circuit board; measuring a signal transmitted through the solder joint of the printed circuit board; and determining whether the solder joint of the printed circuit board is damaged using the measured signal. Accordingly, the device for detecting damage of an electronic product according to the present invention can nondestructively examine damage of the electronic product by using the digital signal.

Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a first data or a second data which is one's complement of the first data; and performing an encoding operation based on the Lien Code by the ECC encoder. The encoding operation includes: if the first data is received, generating a first codeword according to the first data; and if the second data is received, generating a second codeword which is one's complement of the first codeword according to the second data. In addition, a memory storage apparatus using the encoding method based on the Lien Code is also provided.

Abstract: Apparatus facilitating peak power management include a plurality of dies, with each such die comprising an array of memory cells, a controller for performing access operations on the array of memory cells, and a counter configured to be responsive to a clock signal. A particular die of a first subset of dies of the plurality of dies comprises a clock generator for generating the clock signal. Each die of the first subset of dies is configured to be selectively enabled to receive commands in response to a first chip enable signal, and each die of a second subset of dies of the plurality of dies is configured to be selectively enabled to receive commands in response to a second chip enable signal independent of the first chip enable signal, wherein the first subset of dies and the second subset of dies are mutually exclusive.

Abstract: According to one embodiment, there is provided a storage device including a control chip and a plurality of memory chips. The control chip has an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal. A first transmission path going through the input buffer and a second transmission path not going through the input buffer are provided between the external terminal and the plurality of memory chips. In a first mode, the control chip enables the input buffer so as to activate the first transmission path and, in a second mode, disables the input buffer so as to activate the second transmission path.

Abstract: A video analysis system may utilize display screen snapshots captured from a device. The system may receive time information that indicates a time duration, position-related information that indicates a region, and reference information that indicates information expected to appear in the region during the time duration. The system may transmit an instruction to capture display screen snapshots during a time duration indicated by the time information. The system may receive a display screen snapshot and recognize information in the region indicated by the position-related information. The system may then determine whether the recognized information corresponds to the reference information and based on the result determine whether the video test automation has passed.

Abstract: A method of performing a write operation, the method comprising: comparing a data pattern of a currently received command directing a write operation to data patterns of at least one previously received command; and performing a write operation, based on the currently received command directing the write operation, by writing the data patterns of the at least one previously received command instead of the data pattern of the currently received command when the data pattern of the currently received command directing the write operation is identical to the data patterns of the at least one previously received command

Abstract: Example automatic test equipment (ATE) includes: a test instrument for outputting test signals to test a device under test (DUT), and for receiving response signals based on the test signals; a device interface board (DIB) connected to the test instrument, with the DIB including an application space having a site to which the DUT connects, and with the test signals and the response signals passing through the site; and calibration circuitry in the application space on the DIB. The calibration circuitry includes a communication interface over which communications pass, with the communications comprising control signals to the calibration circuitry and measurement signals from the calibration circuitry. The calibration circuitry also includes non-volatile memory to store calibration data and is controllable, based on the control signals, to pass the test signals from the test instrument to the DUT and to pass the response signals from the DUT to the test instrument.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.

Abstract: Leakage current estimation for a circuit can include generating a cell leakage library including cell-level leakage current geometry data for different states of cells of a cell library, wherein the cells are specified as transistor-level netlists, and determining, using a processor, gate-level leakage current geometry data for gates of a gate-level netlist for the circuit based upon states of the gates for a selected operating state of the circuit and the cell-level leakage current geometry data. Total leakage current geometry data can be determined, using the processor, for the gate-level netlist by aggregating the gate-level leakage current geometry data.

Abstract: Embodiments include methods, and computer system, and computer program products for testing directly and indirectly anchored interfaces for vulnerabilities regarding storage protection keys.

Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.

Abstract: Embodiments are generally directed to board level leakage testing for a memory interface. An embodiment of an apparatus includes multiple logic cells for testing of a memory interface, each logic cell being connected to an interconnect for a respective memory element. Each logic cell includes a driver to drive a signal onto the interconnect with the respective memory element, an element to generate a value for the logic cell by comparing a signal with a reference voltage, a flip-flop to capture a cell value for the logic cell, and a drive control element to control the value driven on the interconnect by the driver. The apparatus further includes a processor to identify failure conditions based at least in part on testing using the logic cells.

Abstract: A method includes obtaining a plurality of clauses associated with a plurality of logical variables, each of the clauses consisting of a weight and a disjunction of one or more literals of the logical variables, detecting conditions associated with one or more inference rules, and simplifying the plurality of clauses on the basis of the detecting.

Abstract: What is disclosed are systems and methods of optical feedback for pixel identification, evaluation, and calibration for active matrix light emitting diode device (AMOLED) and other emissive displays. Optical feedback is utilized to calibrate pixel whose output luminance exceeds a threshold difference from a reference value, and may include the use of sparse pixel activation to ensure pixel identification and luminance measurement, as well as a coarse calibration procedure for programming the starting calibration data for a fine calibration stage.

Abstract: An object of the invention is to provide a semiconductor apparatus capable of achieving conditions that are stricter than the conditions in which the stable operation is guaranteed, without increasing the circuit size. A semiconductor apparatus (10) includes a semiconductor circuit (11); a voltage generator (12) that selects one of at least two types of voltages and applies a power supply voltage, the at least two types of voltages including a normal voltage at which the semiconductor circuit (11) normally operates and a low voltage which is lower than the normal voltage; and a clock generator (13) that supplies the semiconductor circuit (11) with a clock signal having a constant frequency regardless of the power supply voltage.

Abstract: A method of testing an electronic unit by comparing resulting signal shapes from the unit to be tested and a known functioning unit. The method includes powering off the units for testing and feeding one or more predefined signal shapes of two or more different frequencies as input signals to the known functioning unit and to the unit to be tested at corresponding test points. The method further includes measuring the resulting signal shapes from both units at corresponding measurement points and comparing at least one resulting signal shape from the known functioning unit with the corresponding resulting signal shape from the unit to be tested. The method also includes detecting a fault in the unit to be tested on the basis of an existing signal shape distortion in time axis of the resulting signal shape received from the unit to be tested.

Abstract: Systems and methods for inserting flops at the chip-level to produce a signal delay for preventing buffer overflow are disclosed herein. Shells of modules described in an RTL description and their connections are analyzed to determine a signal latency between a sender block and a receiver block. The logical interfaces of the shells are grouped in a structured document with associated rules. Flops are inserted between the sender block and the receiver block to introduce a flop delay to meet physical design timing requirement and prevent a buffer of the receiver block from overflowing due to data that is already in-flight when a flow control signal is sent by the receiver block. The sum of a delay on a data line and a delay on a flow control line measured in clock cycles must be less than a depth of the buffer.

Abstract: A method for generating a validation test may include using a processor, identifying, in a scenario for validation testing, a plurality of actions that address a single resource in a conflicting manner; and automatically generating target code of the scenario that includes one or a plurality of resource management commands so as to prevent conflicting addressing of that resource by said plurality of actions.

Abstract: In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.

Abstract: The test board may include sockets in which a plurality of devices-under-test (DUTs) is inserted, and an auxiliary test device connection tree electrically connected to the sockets. The auxiliary test device connection tree includes at least one first auxiliary test device receiving and outputting a test request from an external apparatus, and at least one second auxiliary test device generating a test clock and a test pattern in response to the test request outputted from the at least one first auxiliary test device, performing a test operation about at least one among the DUTs using the generated test pattern, and outputting whether or not of an error of the test operation to the at least one first auxiliary test device.

Abstract: An integrated circuit includes an energy detection circuit, a switching circuit, and a tamper response circuit. The integrated circuit has an input for receiving a radio frequency (RF) signal, a first output for providing a demodulated signal, and a second output for selectively providing a detect signal. The detect signal is provided in response to detecting that an energy of an internal signal exceeds a first threshold when the integrated circuit is in a secure mode. The switching circuit is used to alternatively switch the input of the energy detection circuit to an RF input terminal in a normal mode and to an internal antenna in a secure mode. The tamper response circuit disables a function of the integrated circuit in response to an activation of the detect signal in the secure mode.

Abstract: Various apparatus and methods associated with a compact electronics test system having user programmable device interfaces and on-board functions adapted for use in various environments are provided. Exemplary embodiments can include a variety of apparatuses and methods to realize an advanced field programmable gate array adapted to perform functional tests on digital electronics within an exemplary 48-pin DIP footprint. One aspect of the invention can include a testing device comprised of components to produce a product that is inexpensive and consumable. A small size of an exemplary embodiment of the invention further allows for desirable shielding to be placed around a highly portable and highly programmable and adaptable testing device in order to protect it from external dangers found in harsh environments (e.g., high levels of radiation when operating in space, etc.).

Abstract: Aspects extend to methods, systems, and computer program products for partially reconfiguring acceleration components. Partial reconfiguration can be implemented for any of a variety of reasons, including to address an error in functionality at the acceleration component or to update functionality at the acceleration component. During partial reconfiguration, connectivity can be maintained for any other functionality at the acceleration component untouched by the partial reconfiguration. Partial reconfiguration is more efficient to deploy than full reconfiguration of an acceleration component.

Abstract: A high speed USB memory controller includes a microprocessor, flash memory, memory buffers directly accessible to the microprocessor and flash memory, and a USB interface for writing data directly into the memory buffers. This allows devices with multiple flash die to operate at full bus speed.

Abstract: An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit.

Abstract: Systems and methods for controlling commits to a search platform in a content management system. Identification information of endpoints may be passed down from endpoints to the search platform. Endpoints may be grouped based on their identification information, and commit policies may be assigned to each group of endpoints. A commit request from an endpoint to the search platform may be intercepted, its group may be determined based on the endpoint identification information, and commit policy for that group may be applied to the commit request.

Abstract: Systems and methods are disclosed for logging encoded diagnostic information from a sequence of processing operations, the processing operations generated by an activity in a computing environment. Diagnostic information is tracked by activity, across process boundaries where the processes can be in computationally isolated, or “sandboxed”. Within each process, diagnostic information for an activity is stored in an activity-specific buffer registered with a kernel in the computing environment. For each activity in the computing system, the kernel keeps a list of all processes that have performed, or are performing, a processing task of the activity. The kernel also keeps a reference to the activity-specific log buffers for the activity for each process associated with the activity. If a processing operation for an activity fails, all activity-specific logs from all processes that are associated with the activity can be collected. A report can be generated from the collected logs for the activity.

Abstract: Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.

Abstract: A nonvolatile memory device includes a cell array comprising memory cells; a voltage generator that provides a program or verification voltage to a word line of memory cells selected from the memory cells; a page buffer that transfers write data to be programmed in the selected memory cells through bit lines and to sense whether the selected memory cells are programmed to target states, based on the verification voltage; and a control logic that controls the voltage generator such that the program voltage and the verification voltage are provided to the word line in units of multiple loops during a program operation, the control logic including a loop status circuit that detects values of state pass loops associated with the target states from a sensing result of the page buffer and determines whether the program operation is successful, based on the values of the state pass loops.

Abstract: A system and method for obfuscating binary codes are disclosed. In one embodiment, the system for obfuscating binary codes comprises one or more processors. The one or more processors may be configured to receive a binary file. The one or more processor may further be configured to obfuscate the binary file. The obfuscation may be based on rewriting the binary file and generating a second binary-randomized binary file. The binary file and the second binary-randomized binary file are functionally equivalent. The obfuscation may be based on randomizing the binary file at a load time, without changing functionality of the binary file.

Abstract: A tester interface unit comprising a test hardware module. The test hardware module may have a simple construction, relying on control and/or signal processing in one or more tester instruments to generate or analyze test signals for a device under test. The test hardware module may be disposed within the tester interface unit, providing a short and high integrity signal path length to the device under test. The tester interface unit may include a purge gas chamber and a cooling chamber, with the hardware module penetrate a separator between those chambers, sealing an opening between the purge gas chamber and the cooling chamber. A heat spreader may move heat generated on the portion of the test hardware module in the purge gas chamber to the cooling chamber.

Abstract: A transparent conductive laminate including a first electrode layer including first electrodes connected with first wirings, and a second electrode layer including second electrodes connected with second wirings. One or more first wirings form a reference connection element, and one or more first wirings form a branch connection element adjacent to the reference connection element and has a path branching from that of the reference connection element. The first and/or second electrode layer includes a correction electrode which functions as a correction pattern structure that reduces a time constant difference between the reference connection element and the branch connection element. The correction electrode is positioned in the first and/or second electrode layer at a location which faces the reference connection element with a transparent dielectric layer interposed therebetween.

Abstract: Various systems and methods for managing node connectivity in distributed storage systems are disclosed. For example, one method involves detecting a communication fault between two nodes. A first node is configured to communicate input/output (I/O) requests to the second node as in-flight I/O requests. The second node is configured to communicate locally generated I/O requests and the received I/O requests to storage devices. Once the communication fault is detected, a fencing operation is performed. The fencing operation can include processing some of the received I/O requests by the second node, and rejecting any additional in-flight I/O requests received from the first node.

Abstract: An efficient test for a flash memory combined with a logic chip and incorporated in a semiconductor integrated device can be executed. A logic chip combined with a rewritable nonvolatile memory and incorporated in a semiconductor integrated device is provided with a test circuit. The test circuit reads a programmable test sequence transmitted from an external tester and stored, generates a memory control signal specific to the nonvolatile memory in accordance with a product ID read on the basis of the test sequence, executes a test in which the generated memory control signal is outputted to the nonvolatile memory, and outputs, to the tester, a test result based on a value outputted from the nonvolatile memory in response to the memory control signal.