Abstract: A pin connection testing system for connector, and a method thereof are disclosed. In the pin connection testing system, a JTAG instruction is used to control a PLD, to drive the demultiplexer to transmit each to-be-tested signal, which is from the connector, to a first line or a second line; and, when the to-be-tested signal is transmitted to the first line, the to-be-tested signal is converted from analog to digital and encoded, and then transmitted to I/O pins of the PLD for reading; and, when the JTAG command is transmitted to the second line, the PLD reads the statuses of the I/O pins electrically connected to the second line; and then the PLD generates a test result according to the to-be-tested signals and the read I/O pins. Therefore, the technical effect of improving convenience in testing the connection status of the connector can be achieved.

Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.

Abstract: A vehicle USB hub system that includes a USB hub, a controller and memory unit is provided. The vehicle USB hub system collects data link quality metrics for messaging to and within a vehicle. The USB hub has a CRC error detector for detecting CRC errors in messaging received via its ports. Information regarding detected CRC errors is stored in the memory unit. The controller generates a CRC error log using the information stored in the memory unit upon receiving an indication that an error log should be sent. The controller then sends the CRC error log to a device via the USB hub port indicated.

Abstract: An on-chip clock (OCC) circuit of an integrated circuit includes a clock generator, an OCC controller, and an OCC observation circuit. The clock generator is configured to generate a plurality of clock signals. The OCC controller is configured to receive the clock signals and generate an OCC output for use by the scan chains of logic blocks. The OCC observation circuit is configured to generate a status output on a status output port based on the OCC output during an at-speed capture phase and a scan enable signal. Patterns of the status output with respect to the scan enable signal include a valid pattern indicating that the OCC output includes a valid number of at-speed capture pulses, a first invalid pattern indicating a first error in the OCC output, and a second invalid pattern indicating a second error in the OCC output that is different from the first error.

Abstract: A system for performing an automated test is disclosed. The system comprises a user computer operable to load a test program from a user to a control server, wherein the test program comprises a plurality of test flows. The system further comprises a tester deploying a plurality of primitives. Further, the control server is communicatively coupled to the user computer and to the tester, wherein the control server is operable to download the test program to a primitive from the plurality of primitives, and wherein the control server is further operable to execute a first test flow from the plurality of test flows on a first DUT within the primitive and concurrently execute a second test flow from the plurality of test flows on a second DUT within the primitive.

Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.

Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: An integrated circuit test method provides an interactive shell environment having analysis modules organized as a directory such that for a given session a user can access any of the analysis modules. This invention describes a virtual directory structure for navigating through the entire test data starting from design, test configuration, ATPG patterns, failure information and callout information. This structure also allows the creation of a scripting environment for the user to select a specific configuration and process the information. User can achieve all of this in a single session as opposed to working on every test configuration in an independent session.

Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.

Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a scan chain configured to receive test pattern data and to shift the test pattern data to the device under test, and being clocked by a reference clock, and a clock circuit configured to operate in either a clock generation mode or a frequency determination mode. The clock circuit, when in the clock generation mode and when the test circuit is in a normal mode of operation, is configured to pass a first clock signal to the device under test. The clock circuit, when in the clock generation mode and when the test circuit is in a test mode of operation, is configured to pass the reference clock to the device under test. The clock circuit, when in the frequency determination mode, counts a frequency of the first clock signal.

Abstract: Provided are a multichip debugging method and a multichip system adopting the same. The multichip system includes: a first chip including a first debugging port and first identification (ID) information, a second chip including a second debugging port and second ID information, and a test access port (TAP) electrically connected to the first debugging port and the second debugging port and configured to connect to a test apparatus via the TAP.

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

Abstract: Circuits and methods for efficient interconnect layout of multiple circuit elements, including integrated circuits (ICs), within a circuit module, while enabling only a single control/status (C/S) connection per module. In a first embodiment, the C/S interfaces of multiple ICs are configured in parallel within a multi-IC module, and coupled through a single module serial bus to a system C/S serial bus. In a second embodiment, the C/S interface of a primary IC is coupled through a single module serial bus to a system C/S serial bus, while a secondary IC is internally serially coupled to a “pass through” interface of the primary IC. In a third embodiment, a dynamic address translation circuit translates device and register address information provided by a master device into corresponding internal addresses, and re-directs command messages from a system C/S serial bus to internal slave devices.

Abstract: Circuits and methods for efficient interconnect layout of multiple circuit elements, including integrated circuits (ICs), within a circuit module, while enabling only a single control/status (C/S) connection per module. In a first embodiment, the C/S interfaces of multiple ICs are configured in parallel within a multi-IC module, and coupled through a single module serial bus to a system C/S serial bus. In a second embodiment, the C/S interface of a primary IC is coupled through a single module serial bus to a system C/S serial bus, while a secondary IC is internally serially coupled to a “pass through” interface of the primary IC. In a third embodiment, a dynamic address translation circuit translates device and register address information provided by a master device into corresponding internal addresses, and re-directs command messages from a system C/S serial bus to internal slave devices.

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract: Methods and apparatus for inter-process communication are provided. A circuit may have a plurality of clusters, and at least one cluster may have a computation element (CE), a memory operatively coupled with the CE, and an autonomic transport system (ATS) block operatively coupled with the CE and the memory. The ATS block may be configured to perform inter-process communication (IPC) for the at least one cluster. In one embodiment, the ATS block may transfer a message to a different cluster based on a request from the CE. In another embodiment, the ATS block may receive a message by allocating a buffer in the memory and write the message into the buffer. The ATS block may also be configured to manage synchronization and schedule tasks for the CE.

Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.

Abstract: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

Abstract: System and method for performing scan test on multiple IC devices by site-multiplexing. Multiple test sites of an ATE are coupled to multiple DUTs through a multiplexer. A scan test includes a scan-in/out phase and consecutive launch/capture cycles. Each site performs scan in/out in parallel on the corresponding DUT. In each launch/capture cycle, a respective site drives/captures data from a DUT while the remaining sites are inactive. The multiplexer allows the active site to borrow test channels assigned to other test sites such that all the test data of a DUT can be driven/captured in the launch capture cycle despite the test channel limitation of the active test site. As the tester channels receive interleaved data of the multiple sites, each strobe edge of a receive channel is assigned to a particular test site and used to quickly identify a failure site without post-processing test data.

Abstract: System and method for performing scan test on multiple IC devices by site-multiplexing. Multiple test sites of an ATE are coupled to multiple DUTs through a multiplexer. A scan test includes a scan-in/out phase and consecutive launch/capture cycles. Each site performs scan in/out in parallel on the corresponding DUT. In each launch/capture cycle, a respective site drives/captures data from a DUT while the remaining sites are inactive. The multiplexer allows the active site to borrow test channels assigned to other test sites such that all the test data of a DUT can be driven/captured in the launch capture cycle despite the test channel limitation of the active test site. As the tester channels receive interleaved data of the multiple sites, each strobe edge of a receive channel is assigned to a particular test site and used to quickly identify a failure site without post-processing test data.

Abstract: A testing system including a plurality of ports, at least one controller, and a programmable memory. The plurality of ports may be adapted to implement an IEEE 1149.x standard interface. The at least one controller may be in electronic communication with at least one of the plurality of ports. The programmable memory may be in electrical communication with the at least one controller and adapted to store at least one clock forming variable. The at least one controller may be adapted to form an IEEE 1149.x clock signal for at least one of the plurality of ports based on the at least one clock forming variable. The at least one controller controls the IEEE 1149.x clock signal for at least one of the plurality of ports independently of the IEEE 1149.x clock signal for any other of the plurality of ports.

Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A Double Data Rate (DDR) gating method is applied to a memory controller of an associated DDR gating apparatus. The DDR gating method includes: outputting from the memory controller an outward clock signal to a memory, and receiving from the memory a backward clock signal corresponding to the outward clock signal, wherein the backward clock signal is utilized as reference for a data read operation of the memory controller with respect to the memory; and providing an input stage of the memory controller with a reference signal to generate, through single ended receiving of the input stage, gating-related information for performing gating when sampling the backward clock signal, and lengthening time of a preamble of the backward clock signal with aid of the single ended receiving of the input stage, for increasing a detection margin of the preamble.

Abstract: An electroluminescent display panel includes a plurality of sub-pixels; a plurality of scan lines, each of the scan lines being electrically connected to a first row of sub-pixels and a second row of sub-pixels of two adjacent rows; a plurality of first data lines electrically connected to the first rows of sub-pixels of corresponding columns respectively; a plurality of second data lines electrically connected to the second rows of sub-pixels of corresponding columns respectively; a scan driving unit for outputting a plurality of scanning signals; and a data driving unit for outputting a plurality of dada signals; wherein the scanning signals sequentially turn on two adjacent rows of sub-pixels via the scan lines, the data signals on the first data lines charge the first rows of sub-pixels of the corresponding columns, and the data signals on the second data lines charge the second rows of sub-pixels of the corresponding columns.

Abstract: A pixel circuit and a display device including the pixel circuit are disclosed. In one aspect, the pixel circuit includes an organic light-emitting diode (OLED) including a first terminal electrically connected to a first node and a second terminal electrically connected to a ground voltage. The circuit also includes a driver including a driving transistor including gate, drain and source terminals, and a first capacitor configured to be charged based on a scan signal and a data signal. The first capacitor includes a first terminal electrically connected to the gate terminal of the driving transistor via a second node. The first capacitor also includes a second terminal electrically connected to a supply voltage. The drain terminal of the driving transistor is electrically connected to the supply voltage, and the source terminal of the driving transistor is electrically connected to the first node.

Abstract: A semiconductor device includes a test data interface, a first data interface, and a second data interface. The test data interface generates first test data and second test data from data inputted through a test pad in response to a test control signal and outputs failure information to the test pad in response to a read control signal. The first data interface generates first aligned data from the first test data or the second test data in response to the test control signal. The second data interface generates second aligned data from the second test data.

Abstract: Disclosed herein is a stacked memory device including a base die and a plurality of core dies stacked using a plurality of through-chip electrodes. Each of the core dies may include a plurality of input pads capable of receiving addresses externally in a wafer-level test mode; a control signal generation unit capable of decoding the addresses received through the input pads to generate a first control signal; an address generation unit capable of generating a first address based on the addresses received through the input pads; and a signal selection unit capable of selecting one of the first control signal and a second control signal received from the base die through a corresponding through-chip electrode to output a global control signal, and selecting one of the first address and a second address received from the base die through a corresponding through-chip electrode to output a global address.

Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

Abstract: An arrangement for disabling a configuration of a first programmable hardware component, having the first programmable hardware component, a second programmable hardware component, and a switching element. The first programmable hardware component has a configuration interface for configuring a logic of the first programmable hardware component, a data interface for communication of the logic with the second programmable hardware component, a debugging interface for debugging and configuring the logic, and a configuration monitoring interface for signaling a configuration process of the logic. The switching element is designed and connected to the debugging interface such that access to the debugging interface during a configuration process of the logic can be disabled.

Abstract: An integrated circuit (IC) includes a logic built-in self-test (LBIST) system that includes scan chains. The scan chains receive a clock signal and test pattern signals, and generate scan out signals. A debug controller receives the scan out signals and shifts a set of the scan out signals to a joint test action group (JTAG) controller. The debug controller also maintains a dynamic count indicative of the number of debug shift operations performed, and compares the dynamic count with a final count. If the dynamic count is less than the final count, the debug controller performs a second debug shift operation, which facilitates determination of a fault location in the IC.

Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A parity error is detected in a header, where the header is in a particular one of a plurality of queues, the header is to include a plurality of fields, and each of the queues is to correspond to a respective transaction type. Fabricated header data is generated for one or more of the plurality of fields to indicate the parity error and replace data of one or more of the plurality of fields. An error containment mode is entered based on the parity error.

Abstract: A technique for detecting unauthorized manipulation of a circuit. In one embodiment, a test data channel of a boundary scan system of a circuit is monitored while the circuit is in operation. By monitoring the test data channel, a monitoring module determines the presence of a signal on the test data channel. During operation, activity on this channel may represent a potential unauthorized manipulation attempt. An alarm condition may therefore be created if a signal is detected.

Abstract: Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

Abstract: A test pattern generation device for generating a new test pattern keeping the feature of original test patterns. The test pattern generation device includes a logic value generation unit for generating a new logic value by referring given logic values of a first bit, a second bit and a third bit and by keeping or reversing a logic value of the second bit, wherein a logic value of the first bit is the same with a logic value of a given initial test pattern or a new test pattern generated by the test pattern generation device based on the initial test pattern, wherein a logic value of the second bit is the same with a logic value of the initial test pattern, and wherein a logic value of the third bit is the same with a logic value of the initial test pattern or the new test pattern.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a register capture state output, and a register update state output. Register circuitry has a test data in lead input, control inputs coupled to the state outputs of the controller circuitry, and a control output. Connection circuitry has a control input connected to the control output of the register circuitry and selectively couples one of a first serial data output of first scan circuitry and a second serial data output of second scan circuitry to a test data out lead. Selection circuitry has an input connected to the serial data input lead, an input connected to a test pattern source lead, a control input coupled to the scan circuitry control output leads, and an output connected to the scan input lead.

Abstract: Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the corresponding power domain in parallel. Once testing of memories within a particular power domain is over, the test circuitry tests memories belonging to another power domain in parallel, and so on.

Abstract: A method for performing scan testing using a scan chain having a plurality of storage elements is described. During a capture phase, each storage element of the scan chain stores data from a first data input of the storage element synchronously to a clock signal. And during a shift phase, a scan pattern is shifted into the scan chain in which each storage element stores data from a second data input of the storage element asynchronously with to the clock signal.

Abstract: In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive. The dedicated clock flip-flop stores a data input signal and provides the data input signal, so stored, as a data output signal in response to transitions of the data clock signal, and stores a scan data input signal and provides the scan data input signal, so stored, as the data output signal in response to transitions of the scan clock signal. The clock gating cell may further provide the input clock signal as the data clock signal when both a scan shift enable signal is inactive and a data enable signal is active.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

Abstract: An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Abstract: An integrated circuit (IC), operable in internal and external testing modes (INTEST and EXTEST), includes first and second partitions and a functional path therebetween. The first partition includes a first scan chain, a first multiplexer, and a first flip-flop. The second partition includes a second flip-flop and a second scan chain. The first scan chain generates an EXTEST vector initialization signal, based on an EXTEST scan input signal. The first multiplexer receives an INTEST vector initialization signal and the EXTEST vector initialization signal, and generates a scan input signal. The first flip-flop generates a first output signal based on the scan input signal. The functional path provides a second output signal based on the first output signal. The second flip-flop generates a third output signal based on the second output signal. The second scan chain receives the third output signal and generates a test output signal.