Boundary Scan Patents (Class 714/727)
  • Publication number: 20150052410
    Abstract: A system on chip includes a debugging controller, a plurality of clusters, and a power management unit (PMU). The debugging controller is included in a first power domain and a joint test action group (JTAG) interface is included in the first power domain. Each of the clusters is included in at least second power domain different from the first power domain. The PMU is configured to release a powered-off state of the debugging controller in response to a debugging request signal output from the JTAG interface.
    Type: Application
    Filed: July 24, 2014
    Publication date: February 19, 2015
    Inventor: GYOUNG HWAN HYUN
  • Publication number: 20150052411
    Abstract: An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer. Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains. The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains. Scan structures like the OCCs, scan chain, etc., may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer.
    Type: Application
    Filed: September 25, 2014
    Publication date: February 19, 2015
    Inventor: Franco CESARI
  • Publication number: 20150052412
    Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 19, 2015
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 8959396
    Abstract: The disclosure describes a novel method and apparatus for improving the operation of a TAP architecture in a device through the use of Command signal inputs to the TAP architecture. In response to a Command signal input, the TAP architecture can perform streamlined and uninterrupted Update, Capture and Shift operation cycles to a target circuit in the device or streamlined and uninterrupted capture and shift operation cycles to a target circuit in the device. The Command signals can be input to the TAP architecture via the devices dedicated TMS or TDI inputs or via a separate CMD input to the device.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Publication number: 20150046763
    Abstract: An apparatus and method for controlling a test controller is disclosed. An apparatus includes test controllers of a first type configured to operate according to a first protocol and test controllers of a second type configured to operate according to a second protocol. A test controller of the second type may be associated with one of the test controllers of the first type, with the former controlling the latter. The test controllers of the second type may each control associated ones of the test controllers of the second type in parallel and independently of one another.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: Apple Inc.
    Inventors: Samy R. Makar, Jianlin Yu, Ravi K. Ramaswami
  • Publication number: 20150039955
    Abstract: An Integrated Automatic Test Equipment that provides the test program development environments and execution of test programs for the assembled Print Circuit Boards. This test equipment includes Microsoft Windows PC executable programs, a digital/analog/SPI test controller, and a JTAG controller for boundary scan test. Both test controllers are attached to PC via USB ports for receiving test commands and replying test results. Test program development allows user to specify the rest stimulus and the expected test response for both digital test and boundary scan test. In addition to perform standalone tests, digital tester and boundary scan tester can drive and detect test signals to and from each other. The combination of digital test function and boundary scan test function can increase PCB production line test fault coverage.
    Type: Application
    Filed: May 21, 2014
    Publication date: February 5, 2015
    Inventor: Mark Cheng Chien
  • Patent number: 8947070
    Abstract: An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: February 3, 2015
    Assignee: Apple Inc.
    Inventors: Ashish R. Jain, Edgardo F. Klass
  • Publication number: 20150033088
    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
    Type: Application
    Filed: October 15, 2014
    Publication date: January 29, 2015
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 8941400
    Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8943376
    Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Publication number: 20150026534
    Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.
    Type: Application
    Filed: October 3, 2014
    Publication date: January 22, 2015
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Publication number: 20150026533
    Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.
    Type: Application
    Filed: July 30, 2014
    Publication date: January 22, 2015
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 8938651
    Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: January 20, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Swoboda, Robert A. McGowan
  • Publication number: 20150019928
    Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
    Type: Application
    Filed: October 2, 2014
    Publication date: January 15, 2015
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Publication number: 20150019929
    Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.
    Type: Application
    Filed: October 2, 2014
    Publication date: January 15, 2015
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Gary L. Swoboda
  • Patent number: 8935585
    Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 13, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8935582
    Abstract: Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: January 13, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Ruifeng Guo, Yu Huang, Wu-Tung Cheng
  • Publication number: 20150006986
    Abstract: Three-dimensional processing systems are provided having one or more layers with circuitry that is dedicated to scanning and testing of other system layers, and which enables dynamic checkpointing, fast context switching and fast recovery of system state. For example, a semiconductor device includes a first chip and a second chip, which are physically conjoined to form a stacked structure. The first chip includes functional circuitry. The functional circuitry includes a plurality of scan cells such as scanable flip-flop and latches. The second chip includes scan testing circuitry, and a scan testing I/O (input/output) interface. The scan cells of the first chip are connected to the scan testing I/O interface of the second chip. The scan testing circuitry on the second chip operates to dynamically configure electrical connections between the scan cells on the first chip to form scan chains or scan rings for testing portions of the functional circuitry on the first chip.
    Type: Application
    Filed: June 26, 2013
    Publication date: January 1, 2015
    Inventors: Alper Buyuktosunoglu, Philip G. Emma, Allan M. Hartstein, Michael B. Healy, Krishnan K. Kailas
  • Patent number: 8924803
    Abstract: The invention provides a boundary scan test interface circuit. The boundary scan test interface circuit includes N test input pads, a test interfacing module and M test output pads, wherein N and M are positive integers, and M is smaller than N. The test interfacing module is coupled to the test input pads. The test interfacing module having a plurality of logical gates, and each of input pins of each of the logical gates coupled to each of the test input pads. The test output pads are coupled to output pins of the logical gates in the test interfacing module.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: December 30, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Glen Earl Hush, Jeffrey P Wright
  • Patent number: 8924801
    Abstract: An integrated circuit comprises scan test circuitry and at least one circuit core coupled to the scan test circuitry. The scan test circuitry comprises input and output scan chains coupled to respective input and output interfaces of the circuit core via respective functional logic blocks, and interface signal selection circuitry. The interface signal selection circuitry is configured to select a particular one of a functional input signal and a plurality of scan test input signals for application to one or more designated input signal lines of the input interface of the circuit core responsive to one or more control signals. By way of example only, the first and second scan test input signals may comprise respective first and second distinct address values and the designated input signal lines of the input interface of the circuit core may comprise address input signal lines of an embedded memory.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: December 30, 2014
    Assignee: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy
  • Patent number: 8924795
    Abstract: A distributed debug system including processing elements connected to perform a plurality of processing functions on a received data unit, a debug trap unit, a debug trace dump logic unit, and a debug initiator unit is provided. At least two of the processing elements include a debug trap unit that has a first debug enable input and output, and a first debug thread. The first debug thread holds at least a first debug trap circuit having a match signal output connected to the first debug enable output. The first debug trap circuit filters a part of the data unit, compares a filtering result with a debug value, and provides a match signal to the match signal output. The debug trace dump logic unit dumps debug trace data to a buffer associated with the data unit on reception of a match event.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gil Moran, Evgeni Ginzburg, Adi Katz, Erez Shaizaf
  • Patent number: 8924804
    Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8924802
    Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: December 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8918688
    Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: December 23, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Publication number: 20140372819
    Abstract: Aspects of the invention relate to generating scan chain configurations for test-per-clock based on circuit topology. With various implementations of the invention, weight vectors between scan chains in a circuit are first determined. Based on the weight vectors, a scan chain configuration is generated by assigning some scan chains in the scan chains to a stimuli group and some other scan chains in the scan chains to a compacting group. Here, the stimuli group comprises scan chains to operate in a shifting-launching mode, and the compacting group comprises scan chains to operate in a capturing-compacting-shifting mode.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Publication number: 20140372820
    Abstract: Aspects of the invention relate to using fault-driven techniques to generate scan chain configurations for test-per-clock. A plurality of test cubes that detect a plurality of faults are first generated. Scan chains for loading specified bits of the test cubes are then assigned to a stimuli group. From the plurality of test cubes, a test cube that detects a large number of faults that do not propagate exclusively to scan chains in the stimuli group is selected. One or more scan chains that are not in the stimuli group and are needed for observing the large number of faults are assigned to a compacting group. The number of scan chains either in the compacting group or in both of the compacting group and the stimuli group may be limited to a predetermined number.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Applicant: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Publication number: 20140372822
    Abstract: A method for masking scan chains in a test circuit of an integrated circuit is disclosed. A test pattern to be fed into the test circuit of the integrated circuit is generated. The generated test pattern can be used for detecting a primary fault, one or more secondary faults, and one or more tertiary faults. A mask to mask the output of the scan chains of the test circuit is generated. If a condition is not met, a mask that increases the total number of detectable faults is generated. If the condition is met, a mask that protects the primary fault of the test pattern is generated.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 18, 2014
    Inventors: Jyotirmoy Saikia, Rohit Kapur
  • Publication number: 20140372821
    Abstract: Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are generated based on combinational paths between scan cells. Scan cells may be assigned to one or more pairs of scan cell partitions based on combinational paths between the scan cells. Each pair of the scan cell partitions comprises one stimuli partition and one compacting partition. Using the plurality of scan cell partitions generated, scan chains are formed based on at least information of combinational paths between scan cell partitions in the plurality of scan cell partitions. The formed scan chains are to be dynamically divided into three groups during a test, which are configured to operate in a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, respectively.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Patent number: 8914692
    Abstract: A 2.5D or 3D test architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic die includes a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The memory die is also mounted on the interposer. The memory die includes dynamic random access memory and channel selection/bypass logic. The control logic is coupled to the dynamic random access memory via the channel selection/bypass logic, the channel selection/bypass logic being controlled by the processor wrapper.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Sandeep Kumar Goel
  • Patent number: 8914693
    Abstract: A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin Doerr, Benedikt Geukes, Holger Horbach, Matteo Michel, Manfred Walz
  • Publication number: 20140365839
    Abstract: There is provided a low-cost electronic control unit that is capable of performing its hardware check every start and stop of the electronic control unit. A monitoring and control circuit section that is an integrated circuit element built in the electronic control unit includes a self-test circuit configured with a built-in self-test control block, scan chain circuits and mask circuitry, and performs a self-test using the built-in self-test control block and a partial combination of the scan chain circuits at start of the operation. In the shipment inspection of the integrated circuit element alone, an external test is performed by a checker microprocessor using an entire combination of the scan chain circuits. Thus, the electronic control unit of low-cost configuration is capable of performing a scan test by making use of part of the scan chain circuits designed for the component inspection.
    Type: Application
    Filed: April 1, 2014
    Publication date: December 11, 2014
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuki IWAGAMI, Susumu TANAKA
  • Publication number: 20140365840
    Abstract: The test circuitry according to various aspects of the presently disclosed techniques comprises: low-toggling pseudo-random test pattern generation circuitry, wherein the low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator; scan chains configurable to shift in a low-toggling pseudo-random test pattern generated by the low-toggling pseudo-random test pattern generation circuitry; background chains configurable to shift in a background test pattern; and weight insertion circuitry configurable to modify a plurality of bits in the low-toggling pseudo-random test pattern based on bits in the background test pattern to form a weighted pseudo-random test pattern.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 11, 2014
    Inventors: Xijiang Lin, Janusz Rajski
  • Publication number: 20140359387
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 4, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • Publication number: 20140359388
    Abstract: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 4, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Publication number: 20140359386
    Abstract: A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.
    Type: Application
    Filed: January 20, 2014
    Publication date: December 4, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Atchyuth Gorti, Anirudh Kadiyala, Bill K.C. Kwan, Venkat Krishna Kuchipudi
  • Patent number: 8904253
    Abstract: Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: Sankaran M. Menon, Robert R. Roeder, Liwei E. Ju
  • Patent number: 8904254
    Abstract: A combo dynamic flop with scan flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a dynamic latch circuit and a static latch circuit. The dynamic latch circuit includes a dynamic latch storage node. The static latch circuit includes a static storage node driven by the dynamic latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit, a scan storage node, and a scan feed-forward circuit driven from the static latch. The output buffer circuit includes a dynamic latch driver driven from the dynamic latch circuit and a static driver driven from the static latch circuit.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 2, 2014
    Assignee: Oracle International Corporation
    Inventors: Robert P. Masleid, Ali Vahidsafa
  • Publication number: 20140351665
    Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
    Type: Application
    Filed: August 11, 2014
    Publication date: November 27, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 8898528
    Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: November 25, 2014
    Assignee: Texas Instruments Incoporated
    Inventor: Lee D. Whetsel
  • Publication number: 20140344636
    Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.
    Type: Application
    Filed: July 30, 2014
    Publication date: November 20, 2014
    Applicant: SYNTEST TECHNOLOGIES, INC.
    Inventors: Laung-Terng Wang, Hsin-Po Wang
  • Patent number: 8892973
    Abstract: A debugging control system using inside-core events as trigger conditions and a method of the same are revealed. The method includes following steps. First set up at least one trigger condition and a search range of the clock cycle according to internal states of a core under debug. Pause clock and recover clock of each clock cycle within the search range. Retrieve data of scan chains of the core under debug by a shift buffer during the clock pausing. Next combine data of the scan chains by a trigger comparator circuit to form trigger signals and check whether the trigger signals satisfy the trigger condition. If the trigger condition is satisfied or the trigger signal is over the search range, the clock is paused continuingly and internal states of the scan chains of the core under debug are output otherwise the core under debug is recovered.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: November 18, 2014
    Assignee: National Cheng Kung University
    Inventors: Kuen-Jong Lee, Jia-Wei Jhou
  • Publication number: 20140337679
    Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
    Type: Application
    Filed: July 28, 2014
    Publication date: November 13, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Publication number: 20140337678
    Abstract: Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.
    Type: Application
    Filed: July 25, 2014
    Publication date: November 13, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 8887017
    Abstract: A processor includes a TCU TAP for access of a TCU for running functional tests and a DAP TAP for access of a debugger. A TAP selection module selects reversibly TAP access by default through the TCU TAP when the processor is a bare die, or by default through the DAP TAP when the processor is packaged, the selection of TAP access being reversible by the TCU. The processor also includes a fuse for irreversibly disabling the selection by the TAP selection module of the TAP access by default through the TCU TAP. Functional tests on bare dies are run with a TCU probing the dies through the TCU TAP by default. Packaged engineering samples can be supplied for debugging with the DAP TAP selected by default, but access possible for the TCU through the TCU TAP.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Akshay K. Pathak, Rakesh Pandey
  • Patent number: 8887016
    Abstract: An integrated circuit (IC) is provided. The IC includes a transceiver, a boundary scan chain and a plurality of routable pathways. The transceiver includes an interconnection coupling circuit components. The transceiver receives data and transfers the received data through the interconnection. The received data is utilized to test the interconnection between the circuit components. The transceiver deserializes the data once the data completes its propagation through the interconnection. The boundary scan chain receives and shifts the deserialized data from the transceiver and transfers the shifted deserialized data out of the IC. The shifting is performed when asserted with an instruction of an Input Output (IO) standard. The plurality of routable pathways provides a pathway between the transceiver and the boundary scan chain so that the deserialized data may propagate.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: November 11, 2014
    Assignee: Altera Corporation
    Inventors: Thiam Sin Lai, Siew Leong Lam
  • Publication number: 20140331097
    Abstract: An IO structure, method, and apparatus are disclosed for using an IEEE™ 1149.1 boundary scan latch to reroute a functional path. The method for a chip using IEEE™ 1149.1 boundary scan latches may include using the IEEE™ 1149.1 boundary scan latches for testing IO on the chip in a test mode. The method may also include using information stored in the IEEE™ 1149.1 boundary scan latches to route signals around a failing path in a functional mode.
    Type: Application
    Filed: May 6, 2013
    Publication date: November 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Publication number: 20140331098
    Abstract: A system and method for image enhancement associated with scan generators is provided. For example, a source stimulates a device under test (DUT) at electrical interconnects. An internal clock of the DUT is synchronized with the scan rate of the source to reduce the noise of the output signal and enhance a resultant image. A phase adjustment is effected to further reduce the noise in the signal. The synchronization and the phase adjustment seek to ensure that the data is collected at uniform times relative to the reference signal and thereby reduce the noise introduced into the system, by such offsets. Post-scan processing increases the signal-to-noise ratio through averaging techniques. Using a pixel overlay algorithm the averaged data is transformed into a 2-D array and the image of the DUT reconstructed.
    Type: Application
    Filed: March 13, 2014
    Publication date: November 6, 2014
    Applicant: United States of America as represented by the Secretary of the Navy
    Inventors: Douglas J. Martin, Adam Duncan, Fred Barsun
  • Patent number: 8880968
    Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8880967
    Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: November 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8880965
    Abstract: A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: November 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Wanggen Zhang, Sian Lu, Shayan Zhang