Abstract: A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur is prepared. One of the faults is selected, and an initialization test pattern v1 which establishes an initial value for activating the fault at the location of a fault is determined by the implication operation, and a propagation test pattern v2 which causes a stuck-at fault to be propagated to a following gate is determined by the implication operation. A sequence formed by v1 and v2 is registered with a test pattern list, and the described operations are repeated until there remains no unprocessed fault in the fault list.

Abstract: A system and method are disclosed for characterizing a signal path. The system includes a system clock configured to produce a system clock signal at a sample frequency. A frequency divider is configured to divide the sample frequency of the system clock signal by a factor of N to produce a chip clock signal at a chip frequency. The system further includes a pseudo-noise (PN) sequence generator configured to produce a PN sequence at the chip frequency and couple the PN sequence to the signal path while the signal path is carrying an operational signal. A sub-chip sampler is configured to correlate the PN sequence and a reflected PN sequence which has been reflected within the signal path to form a correlated signal and to sample the correlated signal at the sample frequency of the system clock signal.

Abstract: In the optical disk apparatus, an arbitrary seed data for randomizing is added to an original data to be recorded on a disk. One-bit randomizing data is determined by operation using one-bit original data or seed data, and plural-bit past randomized data. At the time of descrambling, descrambling is performed without seed data.

Abstract: A method and system for reducing test data volume in the testing of logic products such as integrated circuit chips. Test data loaded by a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. According to the invention, non-care bits in the test vector data are filled with repetitive background data to provide for a high degree of compressibility of the test vector data. A substantial portion of the care bits may also be set to a repetitive value and the original values later recovered.

Abstract: A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Abstract: A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.

Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.

Abstract: A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.

Abstract: A pre-stored digital word generator, more particularly, a digital word generator for providing multiple digital words. The pre-stored digital word generator includes a edge memory used to store a primary preset information; an edge address counter used to point to an address of the edge memory; a reloadable down counter used to count according to the primary preset information and trigger the edge address counter; and multiple word generating circuits having a secondary preset information. Therein, the word generating circuits compare the primary and secondary preset information and then produce the digital words according to a comparison result.

Abstract: A method for preventing the scale of a circuit from being extended and for preventing noise from being generated by a simultaneous value change in output buffers includes: the first process of checking the number of output buffers 15A through 15D whose output values change when boundary scan cells 13E through 13H output input patterns; the second process of checking the noise value generated by the change in the output values when all output values from the output buffers checked in the first process change; the third process of selecting the output buffer from the buffers checked in the first process such that the noise value checked in the second process can be within the noise allowable value; and the fourth process of outputting as a test pattern a pattern obtained by amending the input pattern such that the output value of the output buffer selected in the third process can change.

Abstract: A method for reducing the switching activity during both scan-in and scan-out operations of an integrated circuit with reduced detrimental effect on test pattern effectiveness and test time is described. The method makes use of a sample set of patterns to determine the probabilities of same and opposite relationships between stimulus and result values, and uses these probabilities to determine memory element pair compatibilities. Scan chains are ordered preferentially by connecting adjacently compatible memory elements, and inversions are inserted between selected memory element pairs based on those probabilities. Unspecified stimulus bits are filled in to reduce the switching activity based on the scan chain ordering and inversions.

Abstract: Diagnostic codes from a vehicle or other system in transit are transmitted to an opportunity server, which forwards the codes to a supplemental diagnostic service provider. The diagnostic service provider determines if supplemental diagnostics software functions are available, and if so, downloads them to the vehicle. After executing the supplemental diagnostics, the vehicle reports updated codes to the opportunity server. Multiple cycles of selection, downloading and execution of supplemental diagnostics may be performed until fault isolation is achieved, following which the opportunity server issues requests for bids to potential repair service provides. Responding offers are received, coalesced and presented to the operator. The operator of the vehicle is presented with one or more coalesced offers, upon selection of which, a service is scheduled.

Abstract: A plurality of pseudo random bit-pattern generators (PRPGs), advantageously linear feedback shift registers (LFSRs), having predetermined lengths and individual different tap locations for providing a respective sequence of pseudorandom bit-patterns. An output from a predetermined respective tap location at each LFSR is fed to a common OR-gate, a selected subset of the LFSRs are initialized with all bit storing locations to “0” in order to generate a respective permanent “0”-bit sequence, and the output of the OR-gate is used for reading the weighted or flat random bit output-pattern thereof. By controlling the number of zero-set LFSRs—a subset of the LFSRs—the weight of the generated output-pattern can be controlled.

Abstract: Flat pseudo random test patterns are provided in combination with weighted pseudo random test patterns so that the weight applied to every latch in a LSSD shift register (SR) chain can be changed on every cycle. This enables integration of on-chip weighted pattern generation with either internal or external weight set selection. WRP patterns are generated by a tester either externally or internally to a device under test (DUT) and loaded via the shift register inputs (SRIs or WPIs) into the chip's shift register latches (SRLs). A test (or LSSD tester loop sequence) includes loading the SRLs in the SR chains with a WRP, pulsing the appropriate clocks, and unloading the responses captured in the SRLs into the multiple input signature register (MISR). Each test can then be applied multiple times for each weight set, with the weight-set assigning a weight factor or probability to each SRL.

Abstract: A method for testing and diagnosing shift register latch chains coupled to logic circuits in an integrated circuit, the method including: (a) determining which of the shift register latch chains are failing by propagating a test pattern of zeros and ones through the shift register latch chains while gating which of the shift register latch chains contents are propagated into the means for generating a test signature; and (b) for each failing shift register latch chain: (b1) propagating a test pattern through the shift register latch chains while gating a selected sequential group of latches in a failing shift register latch to propagate into the means for generating a test signature; (b2) reducing the number of latches in the sequential group of latches; and (b3) repeating steps (b1) and (b2) until all failing latches of the failing shift register latch chain have been determined.

Abstract: An apparatus and method provide for an arithmetic built-in self test (ABIST) of a number of peripheral devices having parallel scan registers coupled to a processor core, all within an integrated circuit. Using the data paths of the processor core, operating logic generates pseudo-random test patterns for the peripheral devices, employing a mixed congruential generation scheme.

Abstract: Deterministic ATPG test coverage is provided in a logic BIST architecture while reducing test application time and test data volume, as compared to deterministic ATPG patterns. The logic BIST architecture can include a PRPG shadow operatively coupled to a PRPG circuit. The PRPG shadow allows re-seeding of the PRPG circuit with zero cycle overhead. Two compressions can be provided. In a first compression, multiple tests for faults are compressed into one pattern. In a second compression, multiple deterministic ATPG patterns can be compressed into one seed. All patterns provided from the PRPG can be controlled by these seeds so that all care bits are properly set, while all other scan cells are set to pseudo-random values from the PRPG. In this manner, the PRPG can rapidly deliver highly pertinent data to the scan chains of the device under test.

Abstract: A circuit for controlling the random character of a bit flow, including an input shift register receiving the bit flow and having its outputs exploited in parallel, at least one element for comparing at least a partial content of the input register with predetermined patterns, a plurality of counters in a number at most equal to the number of predetermined patterns, and an element for detecting the exceeding of at least one threshold by one of the counters, the result of this detection conditioning the state of a word or bit indicative of the random or non-random character of the bit flow.

Abstract: Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which are distributed according to the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files.

Abstract: A system and method provides for direct control of a high speed data link in a computer system for purposes of testing the data link under a full range of anticipated operating conditions. The transmission of test data is preferably under hardware control and preferably does not encounter interference from other data sources in the computer system thereby enabling the intended test pattern data to be experienced by the data link under test in unaltered form. The tested data is preferably compared to the original data in order to evaluate the status of the link under test.

Abstract: A logic built-in self-test controller is disclosed. The invention, in its various aspects and embodiments, is a built-in self-test controller capable of performing a logic built-in self-test at a test frequency at least as slow as a slowest frequency of a plurality of timing domains to undergo the logic built-in self-test. A method for performing a built-in self-test on an integrated circuit device.

Abstract: The present invention provides a method for IC identification. It can be used to identify the origin of the IC design, wherein said IC comprises at least a testing circuit for testing the functional correctness of said IC, and said testing circuit is activated by a testing activation signal. The testing circuit, after receiving a testing signal, will generate a testing result. The identification method comprises the steps of (1). providing an original identification data representing the origin of the IC; (2). transforming the original identification data into a digital identification data; (3). providing an identification circuit for generating the digital identification data, wherein the identification circuit is activated by the testing activation signal, and generates the digital identification data; (4).

Abstract: The present invention is generally directed to an improved automatic test pattern generator for generating test patterns that are used by an integrated circuit testing device. In accordance with one aspect of the invention, a method is provided for generating a set of test vectors for testing an integrated circuit, each test vector of the set of test vectors containing a plurality of bits defining test inputs for the integrated circuit. The method includes the steps of defining a list of faults for the integrated circuit, and generating at least one test vector that defines values for those inputs necessary to detect at least one target fault selected from the list of faults, the values comprising only a portion of the bits of the at least one test vector, wherein a remainder of the bits in the at least one test vector are unspecified bit positions. The method further includes the step of setting the values of a plurality of the unspecified bit positions using a non-random filling methodology.

Abstract: A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number generator is implemented in hardware. Once a number in a pseudo-random sequence is generated, a pattern eliminator alters the number to remove any pattern existing in the low order bits. The number may then be combined with an offset and a base to form a memory address for testing a memory device. The generated memory address is output directly to the memory device being tested.

Abstract: A method and an apparatus allows complete and efficient verification of cross-architecture ISA emulation. A random verification framework runs concurrently on two different computer architectures. The framework operates without regard to existing native applications and relies instead on binary instructions in a native ISA. The framework determines emulation errors at a machine instruction level. A random code generator generates one or more sequences of native machine instructions and corresponding initial machine states in a pseudo-random fashion. The native instructions are generated from an entire set of the native ISA. The instructions and the state information are provided to initialize a native computer architecture. The same instructions and state information are provided using standard machine-to-machine languages, such as TCP/IP, for example, to a target computer architecture. A binary emulator then translates the native instructions so that the instructions may be executed on the target computer.

Abstract: A method and system for pseudo-random testing a fault tolerant network for determining the network's response to failure includes generating an image of the network on a host. At least one path of the network is selected to be physically failed through the use of a random number generator such that the selection is done pseudo-randomly. The part is then failed and the network's response to the failure is detected and all attempts to repair the failure logged up to and including the first successful attempt to repair the failure. In the event of a failure to repair a path occurs, the test is stopped, a repair effected, and the test restarted at the point the failure to repair occurred.

Abstract: A method for preparing a logic structure for random pattern testing is disclosed. In an exemplary embodiment of the invention, the method includes configuring a select mechanism within a data scan chain, the select mechanism configured between a first register in the data scan chain and a second register. A parallel data path is routed within the scan chain, the parallel data path beginning from an input side of the first register, running through the select mechanism, and ending at an input side of the second register. Thus configured, the select mechanism is capable of switching a source path of input data to said second register from a normal data path to the parallel data path. When the parallel data path is selected as the source path of input data to the second register, data loaded into the second register matches data loaded into the first register.

Abstract: A circuit includes a built-in self-test, wherein the test coverage of a tested logic circuit is improved given the utilization of a fixed standard interface. Besides a direct interface, the complex circuit has an additional indirect interface, which connects a structural test device to a functional circuit.

Abstract: A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.

Abstract: A method and apparatus for generating a test stream wherein tests of digital TV software at various levels and various digital broadcast standards can be supported. The apparatus includes a data generator module for generating test data by referring to a database based on demands of a user, a data writer module for fetching the test data generated by the data generator module and writing the fetched test data into a text or XML data, a data transformation module for transforming the written text or XML data into a transport stream, and a database in which information needed for the modules to perform their own functions is stored and from which the stored information is fetched. The method of invention may similarly follow the functions of the apparatus.

Abstract: A semiconductor apparatus comprises a processor having an instruction register inside thereof, a pseudorandom number generating device activated in response to a test operation and generating pseudorandom numbers, an input switchover device for switching over between data input in normal operation and input of the pseudorandom numbers from the pseudorandom number generating device in the test operation to thereby output the data or pseudorandom numbers to the instruction register. The pseudorandom numbers generated in the pseudorandom number generating device are inputted to the instruction register via the input switchover device so that the random instructions are implemented and a random test is implemented with an activation rate equivalent to the same in the normal operation.

Abstract: A method and apparatus is presented for measuring jitter tolerance in a device under test. A device under test is established to operate at a specific frequency. A bit pattern is generated from a bit pattern generator. The bit pattern generated by the bit pattern generator is produced at a frequency that is a multiple of the frequency that the device under test is operating under. Bits are systematically changed in the bit pattern and then errors are measured in the device under test. As a results the jitter tolerance of the device under test is measured.

Abstract: A method and apparatus for test vector compression is described. More particularly, a response analyzer is described having a shift register and a multiple-input signature register. The shift register is used to perform a first vector space reduction, and the MISR is used to perform a second vector space compression. Accordingly the MISR may be scaled down in input width by a reduction factor of the shift register.

Abstract: A system for reducing test data volume in the testing of logic products such as modules on integrated circuit chips, and systems comprised of multiple integrated circuit chips. Test stimulus data are loaded from a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. Non-care bits in the test vector data are filled with repetitive, repeating, or other background data sequences. The background data sequences are constructed such that they can be algorithmically recovered from a small amount of initialization data. The recovery can use hardware that is located in the product under test, inside the tester, or between the product under test and the tester, or software residing in the tester and operating while the test is performed.

Abstract: A semiconductor integrated circuit device includes a test circuit including a first latch circuit for holding a test pattern input to an electronic circuit operating in accordance with a clock signal and a second latch circuit for holding the output signal of the electronic circuit corresponding to the test pattern. In the test circuit, the clock signal having a frequency higher than the noise frequency generated in the power line at the time of starting to supply the clock signal to the electronic circuit is continuously supplied to the electronic circuit and the test circuit, while at the same time performing, in accordance with the clock signal in a period longer than the period of the clock signal, the operation of inputting the test pattern to the first latch circuit and the operation of outputting the output signal held in the second latch circuit.

Abstract: A device for generating a spreading code in a CDMA communication system is disclosed. In the device, an ML (Maximal Length) sequence generator generates an ML sequence according to a generator polynomial of an ML sequence having a length 2S−1 and a given initial value, and reloads the initial value whenever an ML sequence having a length shorter than the length 2S−1 is generated, to repeatedly perform an operation of generating the ML sequence. A mask selector including first and second masks having a given offset, selects the first mask in an ML sequence period of the desired length and selects the second mask in the other period. A modulo-2 adder adds an output of the ML sequence generator and an output of the mask selector to generate the spreading code, and truncates the ML sequence upon receipt of the second mask.

Abstract: An error detector for a pseudo-random bit sequence (PRBS). A plurality of bits of a PRBS are received in a predictor circuit. A comparator compares two of the bits to predict a next bit in the sequence. The predicted next bit is compared with the actual next bit that is received to determine if there is an error in the actual next bit, and if so, the actual next bit is corrected accordingly. The erroneous actual next bit is replaced with the corrected actual next bit and is then used to predict a future actual next bit. A trigger circuit delays correction during initial operation until the predictor contains a bit sequence in which no errors have been detected.

Abstract: A system and method for processing scan data for integrated circuit testing. Scan data is divided into three groups of scan data segments: scan-in data segments, scan-out data segments and scan-mask data segments. The sequence of scan data segments in each group constitutes the operative test data in a scan stream. Each scan stream is represented by a table having a row corresponding to each scan data segment in the stream. Each row has four fields: a start address, a segment length, a start pad length and an end pad length. The start address is a pointer to the scan data segment in memory where the scan data segment is stored in a contiguous portion of memory. Scan data segment length is the length in bits of the segment. Start pad length is a delay value measured in number of scan clock cycles that must elapse before processing the respective segment in the scan stream.

Abstract: An integrated circuit (IC) includes a first lead, a second lead and a sensor element that provides a sensed signal. The IC also includes a test signal generator that provides a test signal, a signal processing unit, and a switching device that selectively applies the sensed signal or the test signal to the signal processing unit in response to a command signal, wherein the signal processing unit provides processed data. In response to a test command input signal, the IC generates the command signal, wherein when the test input signal is active the command signal is set to command the switching device to input the test signal to the signal processing unit. A check sum calculator receives the processed data and provides a signal indicative of a check sum value on the second lead when the command signal is set to command the switching device to input the test signal to the signal processing unit.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A method of compressing a test vector creates a compressed test vector for use in conjunction with automated test equipment (ATE). The method comprises generating a test vector having a sequence of elements, at least one element of which comprises a ‘don't care’ value. A random sequence of elements is produced also. The test vector and the random sequence are segmented. Each segment of the test vector is compared to a corresponding segment of the random sequence to determine whether the corresponding segments match. When a match is found, a first flag value is sequentially inserted into a compression test vector. When a mismatch is found, a second flag value is sequentially inserted into the compression vector as well as the elements of the mismatched test vector segment. The compressed test vector may be decompressed according to the invention directly into a completely specified test vector using the flag values.

Abstract: A programmable interface. The inventive interface is designed to be used with an interface controller and includes a first circuit for selecting one or more components from a plurality of components in response to at least one first control signal. A second circuit selectively connects the components in response to at least one second control signal. A third circuit selects a serial output mode or a parallel output mode of said components in response to at least one third control signal. In an illustrative implementation, the inventive interface is used as part of an IEEE 1149.1 bus architecture and includes a plurality of stages. At least one of the stages is associated with each of the components under test and includes circuitry for selecting an associated component. The second circuit includes circuitry within each stage for selectively connecting an associated component to a second component by outputting the output of an associated component or the output a previous stage as the output of the stage.

Abstract: Test pattern generation is performed for a sequential circuit by first separating the circuit into overlapping pipelines by controlling corresponding clocks for one or more registers of the circuit so as to break feedback loops of the circuit, and then processing each of the pipelines separately in order to determine if particular target faults are detectable in the pipelines. Independent clocks may be provided for each of a number of registers of the circuit in order to facilitate the breaking of the feedback loops. The processing of the pipelines may include a first processing operation which detects target faults in a single time frame, and a second processing operation which detects target faults in two or more time frames. The first processing operation generates as many combinational test vectors as possible for each of the pipelines, while the second processing operation generates sequences of two or more combinational test vectors for each of the pipelines.

Abstract: A test-program generator capable of implementing a methodology, based on a formal language, for scheduling system-level transactions in generated test programs. A system to be tested may be composed of multiple processors, busses, bus-bridges, shared memories, etc. The scheduling methodology is based on an exploration of scheduling abilities in a hardware system and features a Hierarchical Scheduling Language for specifying transactions and their ordering. Through a grouping hierarchy, which may also be expressed in the form of an equivalent tree, the Hierarchical Scheduling Language combines the ability to stress related logical areas of the system with the possibility of applying high-level scheduling requests. A method for generating testcases based on request-files written in the Hierarchical Scheduling Language is also presented.

Abstract: Hardware or software to test a circuit with a set of functional vectors. The invention compares expected results of functional vectors with the actual results of the test circuit. If there is a miscompare, a recursive comparison is done prior to the first clock cycle of the miscompare.

Abstract: Deterministic random Logic Built In Self Test (LBIST) is disclosed that applies Deterministic Stored Pattern Tests (DSPTs) by using random LBIST. Basically, the present invention selects the appropriate pseudorandom pattern for use with a scan cycle that needs care bits. The scan cycle may be a current or future scan cycle. In particular, the present invention determines care bits for a particular scan cycle. A pseudorandom pattern is generated that is then aligned with the particular scan cycle. If the pseudorandom pattern contains the care bits, with the correct values and in the proper positions within the pattern, this alignment tests one or more logic devices.

Abstract: A general test application scheme is proposed for existing scan-based BIST architectures. The objective is to further improve the test quality without inserting additional logic to the Circuit Under Test (CUT). The proposed test scheme divides the entire test process into multiple test sessions. A different number of capture cycles is applied after scanning in a test pattern in each test session to maximize the fault detection for a distinct subset of faults. A procedure is presented to find the optimal number of capture cycles following each scan sequence for every fault. Based on this information, the number of test sessions and the number of capture cycles after each scan sequence are determined to maximize the random testability of the CUT.

Abstract: A decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Abstract: A system and method is provided for in situ testing of communications links employing digitally wrapped communications. Portions of the payload to be wrapped are replaced with test patterns. These test patterns can be sent simultaneously with real information. The invention provides that the receiving node generate a test pattern, extract the transmitted test pattern, and determine errors in response to comparing the two test patterns. Analysis of the errors can be used to determine the state of the link between the transmitting and receiving nodes.

Abstract: A plurality of pseudo random bit-pattern generators (PRPG), advantageously Linear Feedback Shift Registers (LFSRs), having a predetermined length and individual different tap locations for providing a respective sequence of pseudorandom bit-patterns. An output from a predetermined respective tap location at each LSR is fed to a common OR-gate, a selected subset of said LFSRs are initialized with all bit storing locations to “0” in order to generate a respective permanent “0”-bit sequence, and the output of said OR-gate is used for reading the weighted or flat random bit output-pattern thereof. By controlling the number of zero-set LFSRs—a subset of said LFSRs—the weight of the generated output-pattern can be controlled.