Built-in Testing Circuit (bilbo) Patents (Class 714/733)
  • Patent number: 10141071
    Abstract: Methods and apparatus related to predictive Count Fail Byte (CFBYTE) for non-volatile memory are described. In one embodiment, logic determines a number of memory cells of the non-volatile memory that would pass or fail verification in a current program loop. The logic determines the number of the memory cells based at least in part on information from a previous program loop. The previous program loop is executed prior to the current program loop. The logic causes inhibition of one or more verification pulses to be issued in the current program loop based on comparison of the information from the previous program loop and a threshold value. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Shantanu R. Rajwade, Pranav Kalavade
  • Patent number: 10132862
    Abstract: Methods and systems for code coverage mapping are provided. In one aspect, a method for code coverage mapping includes generating, by a user application executable by a computing device, a source-code handle corresponding to a transaction code. The source-code handle is communicated through an interface to a server emulating a design-under-test (DUT). Writing a value of the source-code handle to a signal in the DUT is facilitated to mark start of execution, by the user application, of one or more sequences of one or more instructions of the transaction code.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: November 20, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Prashant Vardhan Agarwal, Maneesh Agarwal
  • Patent number: 10127612
    Abstract: A method to assist in the operation of a financial market. The method including receiving one or more transaction messages, where the one or more transaction messages include one or more orders or order commitments to be executed on the financial market; imposing one or more delays on the one or more orders or order commitments using a delay algorithm; processing the one or more order or order commitments by opening the one or more transaction messages after the one or more delays; matching the opened orders or order commitments; and executing the matched orders or order commitments.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 13, 2018
    Assignee: Tamer Trading Technologies LLC
    Inventor: Brian F. Mannix
  • Patent number: 10083762
    Abstract: A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: September 25, 2018
    Assignee: SK hynix Inc.
    Inventor: Min Sik Han
  • Patent number: 10073138
    Abstract: An apparatus is described that includes a plurality of circuits each designed to exhibit a unique signature code that is determined from manufacturing tolerances associated with a manufacturing process used to manufacture the circuits. The apparatus also includes error circuitry to determine an error has arisen based on a change in signature codes from the plurality of circuits.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Suraj Sindia, Robert Kwasnick, Dhruv Singh
  • Patent number: 10044348
    Abstract: A method for operating a field device, and a field device that is operated according to the method, in which a measured value is generated, the measured value being assigned a current set point, a target current signal being issued depending on the current set point, wherein an actual current signal is fed back and the target current signal is compared to the actual current signal. To provide more exact comparison of signals a cross-correlation of the target current signal with the actual current signal is formed for comparison.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 7, 2018
    Assignee: KROHNE Messtechnik GmbH
    Inventor: Johannes Kunze
  • Patent number: 9984767
    Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 29, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hidehiro Fujiwara, Makoto Yabuuchi, Koji Nii, Yoshikazu Saito
  • Patent number: 9983261
    Abstract: Aspects of present disclosure relate to an integrated circuit chip (chip), a method and a computer program product of testing the chip. The method of testing the chip may include: partitioning the chip into various partitions, loading built-in self-test (BIST) test instructions into BIST engine and initializing a current partition counter, performing BIST test on current partition, transmitting test results of the current partition of the chip to an external test data storage, checking whether current partition is the last partition, incrementing current partition counter, and returning to performing BIST on a next partition when current partition is not the last partition, and exiting BIST test when current partition is the last partition. The test results may be stored in one or more inactive storage elements of the chip. The number of partitions may include: one partition, a predetermined number of partitions, and a variable number of partitions.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William V. Huott, Thomas J. Knips, Pradip Patel, Daniel Rodko
  • Patent number: 9933481
    Abstract: A Feedback Shift-Register (FSR) enabling improved testing, e.g., Built-In Self-Tests (BIST), is provided. Each cell of the FSR may either be an observable cell, associated with a non-trivial feedback function implemented by a combinational logic circuit, or a controllable cell, having an associated state variable which belongs to the dependence set of exactly one of the non-trivial feedback functions. Each controllable cell is provided with a multiplexer for selecting either a predecessor cell of the controllable cell or a test value as input. Thus, the sequential circuit of the FSR in an embodiment is tested using tests for combinational logic. The disclosed test procedures utilize a minimal set of test vectors and allow detection of all single stuck-at faults in the FSR. The resulting dynamic power dissipation during test can be considerably less than known BIST designs.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: April 3, 2018
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Göran Selander, Mats Näslund, Elena Dubrova
  • Patent number: 9882564
    Abstract: A method for implementing a programmable critical delay path measurement in-line with the critical path logic cells. Additionally, the delay measurement creates a code to be used with a programmable DLL which indicates the delay of the measured critical path. This code can also be used by an off line First Fail Circuit which can mimic the delay of the critical path and give an indication of the critical path delay. The target of this invention is to create a method to optimize the required operating voltage of an integrated circuit per specific speed requirement, overcoming different process variations, temperatures changes and in die variations.
    Type: Grant
    Filed: March 19, 2017
    Date of Patent: January 30, 2018
    Assignee: PLSENSE Ltd.
    Inventors: Uzi Zangi, Neil Feldman
  • Patent number: 9846205
    Abstract: An integrated circuit includes a magnetic sensor and a magnetic field generating coil. A control circuit on the integrated circuit responds to an activation indication received by the integrated circuit to cause activation of generation of a first magnetic field by the magnetic field generating coil. The control circuit responds to a subsequent activation indication to generate a second magnetic field different from the first magnetic field. The first magnetic field may have a polarity opposite to a polarity of the second magnetic field. A communication interface may be used to communicate one or more indications associated with an expected magnetic field strength, such as coil resistance, and a measured magnetic field strength measured by the magnetic sensor. The magnetic field generating coil may be coaxial with the magnetic sensor and the magnetic field generating coil may have an inner diameter greater than a diameter of the magnetic sensor.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: December 19, 2017
    Assignee: Silicon Laboratories Inc.
    Inventor: Jeffrey L. Sonntag
  • Patent number: 9823296
    Abstract: A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: November 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: Manfred Thanner, Carl Culshaw, Juergen Frank, Michael Staudenmaier
  • Patent number: 9805826
    Abstract: An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 31, 2017
    Assignee: NXP USA,INC.
    Inventors: Weiwei Sang, Wanggen Zhang
  • Patent number: 9759772
    Abstract: In general, a test instrument includes a first processing system that is programmable to run one or more test programs to test a device interfaced to the test instrument, and that is programmed to control operation of the test instrument, a second processing system that is dedicated to device testing, the second processing system being programmable to run one or more test programs to test the device, and programmable logic configured to act as an interface between the test instrument and the device, the programmable logic being configurable to perform one or more tests on the device. The first processing system and the second processing system are programmable to access the device via the programmable logic.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: September 12, 2017
    Assignee: Teradyne, Inc.
    Inventors: David Kaushansky, Lloyd K. Frick, Stephen J. Bourassa, David Vandervalk, Michael Thomas Fluet, Michael Francis McGoldrick
  • Patent number: 9728276
    Abstract: An embodiment of the invention provides an integrated circuit including a core circuit and a memory. The core circuit executes operations of the integrated circuit. The memory stores a subsystem and a repair system. When the repair system runs, the repair system detects whether there is a defect in the memory. When the repair system detects the defect, the repair system repairs the defect, and when the repair system does not detect the defect, a fake defect is injected in the memory to verify whether the repair system runs correctly.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 8, 2017
    Assignee: MEDIATEK INC.
    Inventors: Shi-Wei Chang, Chia-Wei Wang
  • Patent number: 9722702
    Abstract: Disclosed herein are a SATA host bus adapter using a optical signal and a method for connecting SATA storage using the optical signal. The SATA host bus adapter includes: a first conversion unit for converting a PCI-Express signal, transmitted from a host computer, into a data signal, using a protocol defined in a bus; a optical signal conversion unit for converting the data signal into a optical signal and for transmitting the optical signal to a optical signal reception unit; and a second conversion unit for converting the optical signal, received by the optical signal reception unit, into the data signal, for converting the data signal into a SATA signal, using the protocol, and for transmitting the SATA signal to the SATA storage.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 1, 2017
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong-Seok Choi, Hyuk-Je Kwon
  • Patent number: 9704598
    Abstract: A processor has a limited set of guard bands that the processor uses, and when a certain amount of stress is accumulated as indicated by the cumulative stress counters (Seff), and the threshold for the current guard is about to be exceeded, the processor switches to the next wider guard band with this technique occurring until all the guard bands are used and end of life settings are reached. This data that can be stored in the FPFs, and in accordance with one exemplary embodiment, the guard band index itself is also stored in the FPFs and used to ensure the most accurate guard band is used by the processor/device.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: July 11, 2017
    Assignee: INTEL CORPORATION
    Inventors: Vinupama Godavarthi, Mukesh Kataria
  • Patent number: 9689920
    Abstract: A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. The tool initializes, by one or more computer processors, one or more nets contained in an initial nets list, wherein the initial nets list is a representation of a circuit design being tested. The tool removes, by one or more computer processors, the one or more nets initialized in response to initialization of each of one or more latches in one or more test channels of the circuit design being tested. The tool determines, by one or more computer processors, whether a latch of the one or more latches is corrupted by an unknown source.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Satya R. S. Bhamidipati, Mary P. Kusko, Cedric Lichtenau, Srinivas V. N. Polisetty
  • Patent number: 9665934
    Abstract: A fault detection circuit for detecting faults in a video sequence includes a multiple input signature register (MISR) with a linear feedback shift register (LFSR) that receives pixel data for pixels in a frame region for video frames of a video sequence and receives a read signal to read the pixel data and shift the MISR; a multiple signature storage buffer (MSSB) that stores frame signatures; and a signature comparator that compares current and reference frame signatures to determine if a fault condition exists in the video sequence. The MISR holds a frame signature for the frame region of the video frame while receiving a frame end signal. The MSSB stores a current frame signature held by the MISR after receiving the frame end signal. The MSSB also stores a reference frame signature. A display processing circuit includes the fault detection circuit. An integrated circuit includes the display processing circuit.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: May 30, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pramod Krishnamurthy Bettagere, Pratish Kumar KT, Anish Reghunath, Brian O. Chae
  • Patent number: 9659196
    Abstract: A method for data verification may include: receiving by a radio frequency identification (RFID) tag a write command including data to be written; writing by said RFID tag said data to be written into a local storage; reading by said RFID tag data from said local storage; and carrying out by said RFID tag a data verification according to said data read out. Further, a data verification apparatus may include a receiving module for receiving a write command including data to be written; a writing module for writing said data to be written into a first storage module configured for storing said data to be written; a reading module for reading data from said first storage module; and a verifying module for carrying out verification according to the data read out by said reading module. Such method and apparatus may reduce the time of data verification by an RFID tag.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: May 23, 2017
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Hui Li, Dan Yu, Yong Yuan, Liang Zhang
  • Patent number: 9599672
    Abstract: An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output. The clock divider circuit is coupled to receive a test clock and is configured to divide the test clock to provide a divided test clock. The clock selection circuitry has a first input coupled to receive the divided test clock, a second input coupled to receive a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided test clock and the system clock as a clock signal to the clock inputs of the scan chain based on the scan enable signal.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 21, 2017
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Anurag Jindal, Nishant Madan, Mayank Tutwani
  • Patent number: 9594625
    Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
  • Patent number: 9576735
    Abstract: A capacitor structure includes a first metal layer including a first plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a second metal layer including a second plurality of horizontally-spaced neutral conductive lines positioned horizontally between a second plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a third metal layer positioned vertically below the first metal layer and above the second metal layer, the third metal layer including a third plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced low voltage conductive lines. The first plurality of low voltage lines are positioned vertically between the first and second plurality of neutral lines.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Roderick Alan Augur, Jason Eugene Stephens
  • Patent number: 9547042
    Abstract: In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: January 17, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9513337
    Abstract: An integrated circuit sensor includes circuitry and methods for generating a high speed delay fault test clock signal. A trimmable oscillator generates a master clock signal for use by an output protocol processor to provide the sensor output signal. A fault test clock signal generator is responsive to the master clock signal and to a test trigger signal for generating the test clock signal having a launch pulse and a capture pulse, each having edges substantially coincident with like edges of pulses of the master clock signal and a spacing between launch and capture pulses established by the trimmable master clock signal.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: December 6, 2016
    Assignee: Allegro Microsystems, LLC
    Inventors: Glenn A. Forrest, Aaron Cook, Dana Briere, Devon Fernandez, Naota Nakayama
  • Patent number: 9489146
    Abstract: A memory system and method are provided for selecting memory dies for memory access operations based on memory die temperatures. The memory system has a plurality of memory dies, where each memory die has its own temperature sensor. In one embodiment, the memory system selects which memory dies to perform memory access operations in based on the temperatures of the memory dies. In another embodiment, a controller of the memory system selects which memory dies to thermal throttle memory access operations in based on the detected temperatures. In yet another embodiment, a temperature-aware media management layer module of the memory 1 system routes a memory access operation from a first memory die to a second memory die based on the temperatures of the memory dies.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: November 8, 2016
    Assignee: SanDisk Technologies LLC
    Inventor: Eran Erez
  • Patent number: 9460814
    Abstract: A method of determining multi-bit upsets (MBU) during soft error rate (SER) testing of a memory device under test is provided. The method may include receiving an error indication based on a comparison between a generated test data pattern written to an address location on the memory device and a stored version of the generated test data pattern read from the address location on the memory device. The error indication is associated with error information associated with the comparison between the generated test data and the stored version of the generated test data. Based on the received error indication, a count value associated with one of a predetermined number of passes a plurality of generated test data patterns traverse between a first and a second memory address location on the memory device is determined. The MBU is determined based on the address location, the error information, and the count value.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joshua M. Dragula, Charles J. Montrose
  • Patent number: 9384856
    Abstract: A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Henning F. Spruth, Qadeer A. Qureshi, Reinaldo Silveira
  • Patent number: 9373417
    Abstract: The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 21, 2016
    Assignee: Integrated Silicon Solution (Shanghai), Inc.
    Inventor: Mingzhao Tong
  • Patent number: 9348748
    Abstract: Technology is described that increases endurance of memory devices through heal leveling. Heal leveling is a lightweight solution to distribute healing cycles among memory blocks. Approaches described herein can accomplish heal leveling without introducing a large amount of overhead. Heal leveling significantly improves the access performance and the effective lifetime of memory blocks. By more evenly distributing the heal count it may not be necessary to directly apply wear leveling based on access counts of each block because each block will be more evenly accessed in the long run. Heal leveling may be performed by moving data that is seldom or never modified after creation, such as read-only files, to blocks having suffered the greatest number, or a high number, of healing cycles.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 24, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Ming Chang, Hsiang-Pang Li, Hang-Ting Lue, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 9336784
    Abstract: Apparatus, system and method for encoding and decoding ancillary code for digital audio, where multiple encoding layers are merged. The merging allows a greater number of ancillary codes to be embedded into the encoding space, and further introduces efficiencies in the encoding process. Utilizing certain error correction techniques, the decoding of ancillary code may be improved and made more reliable.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 10, 2016
    Assignee: The Nielsen Company (US), LLC
    Inventors: Wendell Lynch, John Stavropoulos, David Gish, Alan Neuhauser
  • Patent number: 9300470
    Abstract: A semiconductor device has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Daisuke Oshida, Shigeru Furuta, Masayuki Hirokawa, Akira Yamazaki, Takashi Fujimori, Shigemasa Shiota
  • Patent number: 9298865
    Abstract: Techniques and mechanisms debug a device implementing an optimized design using a pre-optimized design simulation. For example, data indicating interconnect in a pre-optimized design to simulate may be received. A node in common between the pre-optimized design and an optimized design may be identified. A tap at the output of the node in the optimized design may be inserted for providing data for the simulation.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: March 29, 2016
    Assignee: Altera Corporation
    Inventor: Yi Peng
  • Patent number: 9261558
    Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: February 16, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 9256505
    Abstract: Methods and systems for generating data transformations to improve ROM yield and programming time. A bit flip register can be configured in association with the ROM and a binary string can be read into the bit flip register on reset. Subsequently, data output from the ROM can be selectively complemented utilizing a content of the bit flip register and the content of the bit flip register can be programmed into the ROM in order to reduce programming time for each ROM. A defective cell can be tolerated by selectively flipping a column with respect to the defective cell to improve yield. A built-in self-test (BIST) engine that generates addresses up to and including content of an address limiting register can be employed to limit the ROM access to a programmed part during testing in order to tolerate defects in any unused location.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 9, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Sreejit Chakravarty
  • Patent number: 9222990
    Abstract: A method of performing a self-test associated with a magnetic field sensor includes generating a proximity signal responsive to a proximity of a sensed object with one or more magnetic field sensing elements, and identifying one or more characteristic values associated with the proximity signal while the proximity signal is responding to the proximity signal, The method also includes categorizing the one or more characteristic values into three or more potential categories, including three or more categories, wherein the plurality of potential categories is representative of a plurality of discrete self-test states of the proximity signal that could occur while the proximity signal is responding to the proximity of the sensed object. The method also includes communicating at least one of the plurality of potential categories into which at least one of the one or more characteristic values was categorized. A magnetic field senor implements the above method.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: December 29, 2015
    Assignee: Allegro Microsystems, LLC
    Inventors: Daniel S. Dwyer, Christine M. Graham, P. Karl Scheller
  • Patent number: 9164660
    Abstract: A method of controlling a mobile terminal, for diagnosing a home appliance using the mobile terminal is disclosed. The method includes a menu display step of displaying a diagnosis menu for diagnosis of a home appliance on a display, an information receiving step of receiving information about a current state of the home appliance or presence of a problem as an audio signal when the diagnosis menu is selected, the information being diagnosed by the home appliance, a result display step of displaying a diagnosis result of the home appliance on the display, the diagnosis result being obtained based on the information received in the information receiving step, and a solution display step of displaying a solution based on the diagnosis result to suggest a measure to be taken by a user to the user.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 20, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Mijin Jung, Moonhyun Kim
  • Patent number: 9142324
    Abstract: When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: September 22, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepak Raghu, Gautam Dusija, Chris Avila, Yingda Dong, Man Mui
  • Patent number: 9116876
    Abstract: Some novel features pertain to a memory controller that includes a memory controller logic, a built-in-self-tester (BIST) logic, and a switch. The memory controller logic is for controlling memory on a memory die. The built-in-self tester (BIST) logic is for testing the memory. The switch is coupled to the BIST logic and the memory. In some implementations, the BIST logic bypasses the memory controller logic when testing the memory by accessing the memory through the switch. The switch may be controlled by the BIST logic. In some implementations, the switch is coupled to the memory controller logic. The switch may control data to the memory that is transmitted from the memory controller logic and the BIST logic based on priority of the data.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 25, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Woo Tag Kang, Roberto F. Averbuj, Manish Shah
  • Patent number: 9087279
    Abstract: A system includes a microprocessor that executes microcode designed to query all or some of the electronic circuits that are on a device under test. The results of the query are written to an RFID IC register. The RFID IC is queried by an interrogator to obtain test results.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: July 21, 2015
    Assignee: Horse Sense Shoes, LLC
    Inventors: Roger Roisen, Michael McHugh
  • Patent number: 9069041
    Abstract: A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: June 30, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Patent number: 9043662
    Abstract: A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: May 26, 2015
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventor: John W. Selking
  • Patent number: 9041431
    Abstract: Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: May 26, 2015
    Assignee: Altera Corporation
    Inventors: Alan Louis Herrmann, David W. Mendel
  • Patent number: 9043664
    Abstract: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: May 26, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 9032265
    Abstract: A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 9026872
    Abstract: An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: May 5, 2015
    Assignee: Xilinx, Inc.
    Inventor: Rafael C. Camarota
  • Patent number: 9021320
    Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady
  • Patent number: 9015460
    Abstract: A processor having a number of functional units includes a hybrid reset sequence controller that includes a master reset controller that may be configured to hierarchically control a sequence of initialization operations performed on the functional units based upon a value stored within a master control register. In addition, the processor may also include a number of additional controllers, each configured to control initialization operations for a respective functional unit based upon a value stored within an additional respective control register. The master reset controller may control each of the additional reset controllers dependent on the value stored within the master control register.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 21, 2015
    Assignee: Oracle International Corporation
    Inventor: Ali Vahidsafa
  • Publication number: 20150106673
    Abstract: The present invention discloses a memory channel bridge with a BIST module; and the memory channel bridge interfaces other channels in a SOC to access a memory module. During a DFT test, SOC memory channels and the BIST access the memory module concurrently by using an arbiter in the memory channel bridge to arbitrate the traffics from the SOC memory channels and the BIST to ensure the correctness and completeness of the whole design.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., GLOBAL UNICHIP CORP.
    Inventors: Jung Chi Huang, Wen Hsuan Hu, Chao Yu Chen
  • Patent number: 9009550
    Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Raguram Damodaran, Naveen Bhoria, Aman Kokrady