Structural (in-circuit Test) Patents (Class 714/734)
  • Patent number: 8037377
    Abstract: A circuit includes a receiver channel and a built-in self-test circuit. The receiver channel has a serializer and a deserializer. The built-in self-test circuit generates test signals that are transmitted in parallel to the serializer during a test of the receiver channel. The serializer converts the test signals into serial test signals. The deserializer converts the serial test signals into parallel test signals that are transmitted to the built-in self-test circuit.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: October 11, 2011
    Assignee: Altera Corporation
    Inventors: Ie Chen Chia, Eng Huat Lee, Thow Pang Chong, Boon Jin Ang, Kar Keng Chua
  • Patent number: 8020059
    Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: September 13, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8006141
    Abstract: A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, which corresponds to a baseline jitter amount. In turn, the receive test accelerator tests the device, at the adjusted test time, using a data stream that is modulated by the adjusted jitter amount.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: August 23, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Samuel G. Stephens, Michael P. Baker
  • Patent number: 7984349
    Abstract: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 19, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7984343
    Abstract: A test circuit can use a simple test pattern data without customization for each substrate and considerably reduce a test preparation process. A connection test circuit is generated by receiving the input of the data of the connection relation indicating the devices mutually line-connected among a plurality of devices, the number of connection lines corresponding to the respective connection relations, and the device outputting a test result, sequentially searching for a connection destination device from the output terminal of an output device, and embedding a test circuit module in a test route.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: July 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kohichi Tamai
  • Patent number: 7979759
    Abstract: A memory hub device with test logic is configured to communicate with memory devices via multiple hub device ports, and is also configured to communicate on one or more busses in an upstream and downstream direction. The test logic includes a built-in self test apparatus providing logic to simultaneously and independently test the memory devices interfaced to one or more of the hub device ports using read and write data patterns. The test logic also includes configuration registers to hold fault and diagnostic information, and to initiate one or more tests. The memory hub device can further include command collision detection logic, a trace array, buffer transmit mode logic, trigger logic, clock adjustment logic, transparent mode logic, and a configured command sequencer, as well as additional features.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Carnevale, Elianne A. Bravo, Kevin C. Gower, Gary A. Van Huben, Donald J. Ziebarth
  • Patent number: 7979754
    Abstract: A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: July 12, 2011
    Assignee: Oracle America, Inc.
    Inventors: Robert J. Drost, Ronald Ho, Justin M. Schauer
  • Publication number: 20110161762
    Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.
    Type: Application
    Filed: March 8, 2011
    Publication date: June 30, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 7958472
    Abstract: To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: June 7, 2011
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Frederic J. Neuveux, Yasunari Kanzawa
  • Patent number: 7958413
    Abstract: The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: June 7, 2011
    Assignee: Marvell International Ltd.
    Inventors: Winston Lee, Albert Wu, Chorng-Lii Liou
  • Patent number: 7954030
    Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: May 31, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jayashree Saxena, Lee D. Whetsel
  • Patent number: 7954028
    Abstract: A design structure for implementing redundancy programming in a memory macro of an integrated circuit chip. It is assumed that all fails are row fails until determined to be bitline fails, circuits for implementing a method wherein it is assumed that all fails are row fails until determined to be bitline fails and test patterns are passed back to the failure detecting circuit when a wordline destination of the test patterns has previously been determined to be failing, and the test patterns and resultant patterns are passed between the memory macro and a test engine via logic paths connecting the memory macro to other circuits in said integrated circuit chip.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: John Edward Barth, Jr., Kevin William Gorman
  • Patent number: 7954027
    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: May 31, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7949913
    Abstract: A method for storing a memory defect map is disclosed whereby a memory component is tested for defects at the time of manufacture and any memory defects detected are stored in a memory defect map and used to optimize the system performance. The memory defect map is updated and the system's remapping resources optimized as new memory defects are detected during operation.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: May 24, 2011
    Assignee: Dell Products L.P.
    Inventors: Forrest E. Norrod, Jimmy D. Pike, Tom L. Newell
  • Patent number: 7949914
    Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: May 24, 2011
    Assignee: ARM Limited
    Inventors: Peter Logan Harrod, Edmond John Simon Ashfield, Thomas Sean Houlihane, Paul Kimelman, Simon John Craske, Michael John Williams
  • Publication number: 20110119544
    Abstract: Techniques for assisting a designer in correcting discrepancies identified in layout design data. A user interface may be provided listing identified shorts and relevant information related to those shorts. Still further, the user interface may allow a designer to selectively choose a subset of the identified shorts, and to designate or otherwise provide correction data for use to correct the shorts before performing a short isolation process on the selected shorts. Alternately or additionally a user interface may provide a designer with graphical images showing the correction that should be made by a designer to address an identified discrepancy in layout design data.
    Type: Application
    Filed: June 9, 2010
    Publication date: May 19, 2011
    Inventors: William Matthew Hogan, MacDonald Hall Jackson, III
  • Patent number: 7945824
    Abstract: An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: May 17, 2011
    Assignee: Rambus Inc.
    Inventors: Adrian E. Ong, Naresh Baliga
  • Publication number: 20110107163
    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.
    Type: Application
    Filed: January 6, 2011
    Publication date: May 5, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 7936875
    Abstract: A method and a circuit for protecting a digital quantity stored in a microcontroller including a JTAG interface, including the step of making the digital quantity dependent from a value stored in non-volatile fashion in the microcontroller and made inaccessible if signals are present at the input of the JTAG interface.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: May 3, 2011
    Assignee: STMicroelectronics S.A.
    Inventor: Fabio Sozzani
  • Patent number: 7934134
    Abstract: A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Donato O. Forlenza, Orazio P. Forlenza, Bryan J. Robbins, Phong T. Tran
  • Patent number: 7930604
    Abstract: A system for receiving serial messages from a device under test includes a deserializer configured to i) receive the serial messages and, ii) based on the serial messages, form data frames. A frame sync module is configured to form Joint Task Action Group (JTAG) data bits based on the data frames. A plurality of virtual JTAG test access ports are configured to i) receive the JTAG data bits and ii) shift the JTAG data bits between the plurality of virtual JTAG test access ports.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: April 19, 2011
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Ho, Daniel Smathers
  • Patent number: 7930601
    Abstract: A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Joseph Eckelman, Donato O. Forlenza, Orazio P. Forlenza, William J. Hurley, Thomas J. Knips, Gary William Maier, Phong T. Tran
  • Patent number: 7928750
    Abstract: An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device under test processes the test data and generates response data. A signal representing the response data is transmitted to the interface device through electromagnetically coupled structures on the device under test and the interface device.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: April 19, 2011
    Assignee: FormFactor, Inc.
    Inventor: Charles A. Miller
  • Patent number: 7925942
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: April 12, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • Patent number: 7920987
    Abstract: A method of determining the intrinsic electrical characteristics of a device under test (DUT) includes determining a set of test measurements for a test structure including the device and determining test measurements for a number of de-embedding test structures. Based on the test measurements, DUT measurements are determined using both open-short and three-step de-embedding processes. The DUT measurements are combined to determine an imperfection error, which is used to adjust the calculations of a four-port de-embedding method. The adjusted calculations provide for a more accurate measurement of the parasitic elements in the test structure, thereby improving the determination of the intrinsic electrical characteristics of the device.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: April 5, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shun-Meen Kuo, Marcel N. Tutt
  • Patent number: 7921346
    Abstract: A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: Donato Orazio Forlenza, Orazio Pasquale Forlenza, Bryan J. Robbins, Phong T. Tran
  • Patent number: 7917819
    Abstract: A test-communication path is provided between chips in a multi-chip package. Externally-accessible JTAG input and output pins are provided to a first chip in the multi-chip package, and this first chip is configured to allow signals received on these JTAG pins to be routed to other chips in the multi-chip package. Control signals provided to the first chip control the routing of the JTAG signals to each chip.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: March 29, 2011
    Assignee: NXP B.V.
    Inventors: Jacky Talayssat, Sake Buwalda
  • Patent number: 7917823
    Abstract: A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: David Dehnert, Matthew Heath
  • Patent number: 7913142
    Abstract: A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithmetic unit to a test mode, in which a first scan chain of the first arithmetic unit is accessible; reading the first test data from the second memory unit; shifting the first test data which have been read through the first scan chain of the first arithmetic unit switched to the test mode for providing test result data for the first arithmetic unit; checking the provided test result data for plausibility for providing a test result for the first arithmetic unit.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: March 22, 2011
    Assignee: Robert Bosch GmbH
    Inventor: Axel Aue
  • Patent number: 7908532
    Abstract: This invention involves the use of the JTAG functional test patterns and exercisors to solve the problem of diagnosing broken scan chains in either a serial or a lateral broadside insertion manner across all latch system ports and to analyze the response data efficiently for the purpose of readily identifying switching and non-switching latches with the next to last non-switching latch being the point of the break within a defective scan chain(s). This comprehensive latch perturbation, in conjunction with iterative diagnostic algorithms is used to identify and to pinpoint the defective location in such a broken scan chain(s). This JTAG Functional test function and the JTAG test patterns ultimately derived therefrom, can take on different forms and origins, some external to a product and some internal to a product.
    Type: Grant
    Filed: February 16, 2008
    Date of Patent: March 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Joseph Eckelman, Donato O. Forlenza, Orazio P. Forlenza, Robert B. Gass, Phong T. Tran
  • Patent number: 7902856
    Abstract: An exemplary aspect of the invention is to conduct delay tests under actual operating conditions for a semiconductor integrated circuit including multiple logic circuits operating based on clocks of different frequencies, without causing any inconveniences when a test clock is set to a high-frequency side or a low-frequency side. The semiconductor integrated circuit includes: a first logic block that operates based on a first clock; a second logic block that operates based on a second clock having a frequency different from that of the first clock; and a test circuit connected between the first logic block and the second logic block. The test circuit outputs an output of the first logic block set as a test target, without passing through the second logic block, and transmits an input value received without being passed through the first logic circuit, to the second logic circuit set as a test target.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: March 8, 2011
    Assignee: RENESAS Electronics Corporation
    Inventor: Mitsuhiro Yamamoto
  • Patent number: 7904768
    Abstract: A probing system for an integrated circuit device, which transmits a testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system includes a test head having a first transceiving module. There is a test station having a test unit coupled to the test head to perform a test operation. A communication module has a second transceiving module configured to exchange data with the first transceiving module in a wireless manner. There is an integrated circuit device having a core circuit being tested, and a test module having a self-test circuit coupled to the core circuit and the communication module for performing the core circuit self-testing.
    Type: Grant
    Filed: May 3, 2008
    Date of Patent: March 8, 2011
    Assignee: National Tsing Hua University
    Inventors: Cheng-Wen Wu, Chih-Tsun Huang, Yu-Tsao Hsing
  • Patent number: 7900109
    Abstract: A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions according to a plurality of states and also comprising an adapter. The method comprises the adapter transferring data to the test debug system while the test access port remains in a predefined state. The predefined state comprises a state in which no scans occur.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: March 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 7900107
    Abstract: The invention provides an internal comparison circuits for speeding up the ATPG test. During test, an external test machine transfers original test patterns into at least one scan chain of a chip to be tested. A bi-directional output buffer of the chip also receives the test patterns from the test machine. A comparator of the chip compares the original test patterns from the test machine via the bi-directional output buffer group with scanned-out test patterns from the scan chain, to produce a comparison signal indicating whether the chip passes or fails the test.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: March 1, 2011
    Assignee: Faraday Technology Corp.
    Inventors: Wang-Chin Chen, Augusli Kifli
  • Patent number: 7895484
    Abstract: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: February 22, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Tanaka, Yuji Nakagawa
  • Patent number: 7886206
    Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Young Park, Ki-Sang Kang
  • Publication number: 20110029830
    Abstract: Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.
    Type: Application
    Filed: September 19, 2008
    Publication date: February 3, 2011
    Inventors: Marc Miller, Steven Teig, Jason Redgrave, Brad Hutchings, Danny Thom
  • Patent number: 7882406
    Abstract: An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: February 1, 2011
    Assignee: LSI Corporation
    Inventors: Alexander E. Andreev, Anatoli A. Bolotov
  • Patent number: 7877653
    Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: January 25, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7873891
    Abstract: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: January 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Yuen H. Chan, Rajiv V. Joshi
  • Publication number: 20110010596
    Abstract: A testable circuit includes a first function logic, an input output cell including an input/output unit and a first control multiplexer; and a first testing block is provided, wherein the input/output unit has at least a connection terminal. The first control multiplexer has an output port coupled to the connection terminal, a first input port coupled to the first functional logic, and a second input port. The first testing block is coupled between the first functional logic and the second input port, wherein when the testable circuit is under a testing mode, the first control multiplexer couples the second input port to the output port; and when the testable circuit is under a normal mode, the first control multiplexer couples the first input port to the output port.
    Type: Application
    Filed: July 9, 2009
    Publication date: January 13, 2011
    Inventors: Tao-Yen Yang, Kun-Chin Huang
  • Patent number: 7870455
    Abstract: A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface and a user interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system. The host system is connected to the at least one of the plurality of SOC ICs via the user interface.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: January 11, 2011
    Assignee: Infineon Technologies AG
    Inventor: Albrecht Mayer
  • Patent number: 7865795
    Abstract: Methods and apparatuses for generating a random sequence of commands for a semiconductor device. The method generates random state transitions within a finite state machine model of the semiconductor device. A sequence of commands is determined which are associated to the generated random state transitions based on the finite state machine model of the semiconductor device.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: January 4, 2011
    Assignee: Qimonda AG
    Inventors: Thomas Nirmaier, Wolfgang Spirkl
  • Patent number: 7859293
    Abstract: A semiconductor integrated circuit includes a digital circuit and a first-stage register circuit provided in a stage followed by the digital circuit. The digital circuit includes a logic circuit and a register circuit configured to temporarily retain a logic output from the logic circuit. The first-stage register circuit has a function as an alternative configured to test at least one register circuit and a function as an interface which supplies input data from an external input terminal to the digital circuit. The first-stage register circuit retains the input data from the external input terminal in synchronization with a clock signal, supplies the retained data to the digital circuit at the time of system operation, and outputs the retained data from an external output terminal connected to a dedicated output terminal or the digital circuit at the time of testing.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuyuki Niwa
  • Patent number: 7849373
    Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
  • Patent number: 7848899
    Abstract: Embodiments described herein relate to systems and methods for testing integrated circuit devices within an environment that is representative of the application environment in which an integrated circuit device will be used. In at least one embodiment, the testing system comprises a second reference integrated circuit device that provides flexibility in testing, allowing only the input to a first reference integrated circuit device of an application system to be tapped and not necessarily both input to and output from the first reference integrated circuit device to be tapped. In some embodiments, the input to the first reference integrated circuit device may be subsequently modified by a controller.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: December 7, 2010
    Assignee: KingTiger Technology (Canada) Inc.
    Inventors: Bosco Chun Sang Lai, Sunny Lai-Ming Chang, Hong Liang Chan, Yu Kuen Lam, Lawrence Wai Cheung Ho
  • Patent number: 7844869
    Abstract: A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: November 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Louis Bernard Bushard, Todd Alan Christensen, Jesse Daniel Smith
  • Publication number: 20100287431
    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.
    Type: Application
    Filed: July 21, 2010
    Publication date: November 11, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Patent number: 7831874
    Abstract: A reconfigurable high performance computer includes a stack of semiconductor substrate assemblies (SSAs). Some SSAs involve FPGA dice that are surface mounted, as bare dice, to a semiconductor substrate. Other SSAs involve memory dice that are surface mounted to a semiconductor substrate. Elastomeric connectors are sandwiched between, and interconnect, adjacent semiconductor substrates proceeding down the stack. Each SSA includes a local defect memory and a self-test mechanism. The self-test mechanism periodically tests the SSA and its interconnects, and stores resulting defect information into its local defect memory. The computer is configured to realize a user design and then is run. A defect is then detected. If the defect is determined to be in a part of the computer used in the realization of user design, then the computer is reconfigured not to use the defective part and running of the computer is resumed, otherwise the computer resumes running without reconfiguration.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 9, 2010
    Assignee: siXis, Inc.
    Inventor: Robert O. Conn
  • Patent number: 7827018
    Abstract: A method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects provides a mechanism for raising short-term and long-term performance of memory arrays beyond present levels/yields. Available redundant elements are used as replacements for selected elements in the array. The elements for replacement are selected by BOL (beginning-of-life) testing at a selected operating point that maximizes the end-of-life (EOL) yield distribution as among a set of operating points at which post-repair yield requirements are met at beginning-of-life (BOL). The selected operating point is therefore the “best” operating point to improve yield at EOL for a desired range of operating points or maximize the EOL operating range. For a given BOL repair operating point, the yield at EOL is computed. The operating point having the best yield at EOL is selected and testing is performed at that operating point to select repairs.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: November 2, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chad A. Adams, Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif