Abstract: A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.

Abstract: A new gridding method is disclosed for forward stratigraphic modeling that allows for syndepositional and/or postdepositional fault movement. The new gridding algorithm may represent both the lateral move of structure block, and provide efficiency that is comparable to the structured grid for forward stratigraphy model accessing previous deposited sediments stored in the grid. Embodiments of the disclosed methods allow for structural moves by performing a set of simple operations on the grid. The operations are generally simple, and do not change the overall topology of the grid. Therefore the operation can be easily repeated and the overall topological structure of the grid remains largely unchanged for simple access by the forward stratigraphic model. Further details and advantages of various embodiments of the method are described in more herein.

Abstract: A method for automatic debug session analysis for related work item discovery, is provided. The method includes recording metadata describing a particular debug session associated with a user for a respective work item. The method further includes associating the metadata recorded in the particular debug session with the respective work item. In response to the user working on a new issue, comparing the metadata saved with other work items. In response to identifying a work item with a predetermined level of similar metadata from debug sessions, notifying the user of a potential work item match. In response to not identifying a work item with a predetermined level of similar metadata from debug sessions, refraining from suggesting the new issue for future matches.

Abstract: A magnetic speed sensor may comprise a digital component configured to estimate a zero crossing event based on a plurality of sensor signal samples. The digital component may output, to a control unit, a speed signal that is based on the estimated zero crossing event.

Abstract: The present disclosure illustrates a testing circuit board with self-detection function and a self-detection method. A test for a to-be-tested circuit board is executed and a self-detection for a testing circuit board is performed by a JTAG chip. After the self-detection is passed, a first JTAG connection interface and a second JTAG connection interface are conducted by a controller, a multiplexer and a switch chip, to connect test circuit boards in series. Therefore, the efficiency of solving self-detection of JTAG chip with series connection conveniently and quickly may be achieved.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: A substrate inspection apparatus can efficiently inspect electric characteristics of the semiconductor device. A prober 10 includes a probe card 15 having a multiple number of probe needles 17 to be brought into contact with electrodes of a semiconductor device formed on a wafer W; and a test box 14 electrically connected to the probe card 15. A card-side inspection circuit of the probe card 15 reproduces a circuit configuration on which the semiconductor device is to be mounted after separated from the wafer W, e.g., the circuit configuration of a function extension card, and a box-side inspection circuit 21 of the test box 14 reproduces a circuit configuration on which the semiconductor device is to be mounted, e.g., a part of the circuit configuration of the mother board.

Abstract: A tester for integrated circuits on a silicon wafer includes an input/output connection for testing an integrated circuit. The tester comprises circuitry arranged for transferring a first data frame to the integrated circuit via the input/output connection, the first data frame including a time reference for the data included in the data frame, a field for validating the time reference and a data field including at least one test command and for receiving a second data frame via the input/output connection, the data in the second data frame received having a duration that is a multiple of the time reference.

Abstract: At least some embodiments are directed to a system that comprises storage comprising a data structure that cross-references an identifier of a semiconductor wafer, a location of a die in the wafer, an identifier of a lead frame strip, a location of a lead frame in the lead frame strip, and results of a first test on the die. The system also comprises mechanical equipment configured to test packaged die. The system further comprises a processor, coupled to the storage and to the mechanical equipment, configured to perform a second test on a package containing the die and the lead frame using the mechanical equipment and the results of the first test.

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

Abstract: A controller for modifying a clock signal from a first clock, the controller comprising: a time comparison unit configured to estimate a time difference between a first signal associated with the first clock and a reference signal received at the controller, wherein the time comparison unit is configured to determine if the time difference is greater than or less than one clock period of the first clock; a first signal modifier configured to modify the clock signal by an integer number of clock periods; and a second signal modifier configured to modify the clock signal by a fraction of the clock period, wherein the controller is configured to select, for modifying the clock signal, the first signal modifier if the time difference is greater than one clock period or the second signal modifier if the time difference is less than one clock period.

Abstract: Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.

Abstract: A circuit and a method for testing for faults in a circuit path. The circuit comprises a memory, a collar flop connected in parallel with the memory, and a feedback path in communication with the output of the memory and the input of the collar flop. The method comprises applying a fault test vector to logic in the circuit path to produce a fault test vector response, propagating the vector or the response through a memory in the circuit path, and capturing the response in a collar flop.

Abstract: The present invention discloses a channel estimation method, apparatus, and device and a multichannel microwave communications system. According to the channel estimation method, a first vector group corresponding to a transmit end and a second vector group corresponding to a receive end are first obtained according to a transmit-receive array size; then a subchannel estimation procedure is performed multiple times according to the transmit-receive array size, the first vector group, and the second vector group, to obtain multiple corresponding subchannel estimated coefficients; and finally, a real channel matrix is determined according to the first vector group, the second vector group, and an estimation matrix consisting of the multiple subchannel estimated coefficients.

Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.

Abstract: Various embodiments include apparatus and methods to track and/or correct timing signals. Timing signals generated from an interface can be compared to the timing signals returned to the interface. A timing delta from the comparison can be applied to calculate a correction value make adjustments that can include adjustment to a subsequent timing signal, adjustment to a reference voltage setting associated with the subsequent timing signal, other adjustments, or combinations thereof. Additional apparatus, systems, and methods are disclosed.

Abstract: A computer implemented process is described for testing multiple electronic devices under test (DUTs). A design test pattern or command/instruction is generated with an electronic design automation tool (EDA). The generated design test pattern and command/instruction is sent directly to an automated test equipment apparatus (ATE) over a UNIX or scripting language based, and/or a network based, communication pipeline. The ATE converts the sent design test pattern to an instance of the test pattern directly executable by the ATE. The ATE apparatus inputs test signals to each of the multiple electronic DUTs based on the executable test pattern. The ATE apparatus then receives, from each of the multiple electronic DUTs, a test result based on the input test signals. The ATE returns the received test result, and a report of an action responsive to the command/instruction to the EDA tool, which may then process the test results and report.

Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.

Abstract: A method of manufacturing an array of semiconductor device packages includes placing a plurality of semiconductor chips on a temporary carrier, covering the plurality of semiconductor chips with an encapsulation material to form an encapsulation body, providing a plurality of microwave components each including at least one electrically conducting wall structure integrated in the encapsulation body, forming a plurality of electrical interconnects each configured to electrically couple a semiconductor chip and a microwave component, and separating the encapsulation body into single semiconductor device packages each including a semiconductor chip, a microwave component and an electrical interconnect.

Abstract: A system and method for testing wireless transceivers in a virtual wireless environment including emulating an RF environment, creating virtual spectrum users having selectable transmission parameters and physical characteristics and evaluating the operation of the wireless transceiver in the virtual wireless environment.

Abstract: Exemplary method, computer-accessible medium, test architecture, and system can be provided for a partial-scan test of at least one integrated circuit. For example, it is possible to obtain a plurality of test cubes using a first combinational automatic test pattern generation (ATPG) and identify at least one flip-flop of the integrated circuit using the test cubes to convert to a non-scan flip-flop and facilitate the partial-scan test to utilize the cubes without a utilization of a sequential ATPG or a second combinational ATPG.

Abstract: In an embodiment, a memory interface includes integrated circuitry to verify the integrity of the memory interface. The circuitry propagates a test pattern through different paths of the memory interface, and checks the result against a reference value to determine whether the components of the paths are operating within an acceptable tolerance. The memory interface can also communicate with ATE to initiate such tests and return the results to the ATE.

Abstract: A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.

Abstract: Implementations of the present disclosure involve an apparatus and/or method for mixing high speed and low speed clock signals during structural testing of a digital integrated circuit to improve the test precision and efficiency. In particular, the apparatus and/or method allow for a testing device to perform stuck-bit testing of the circuit by releasing one or more clock cycles of a low speed clock signal. Further, without having to reset the testing of the circuit, at-speed testing of the circuit may be conducted by the testing device. In one embodiment, at-speed testing occurs by activating a mode signal associated with the circuit design that instructs one or more clock cycles from an internal clock signal to the circuit to be released. The testing device may return to stuck-bit testing at a low speed clock signal, or continue with at-speed testing using the high speed internal clock signal.

Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

Abstract: A method for localizing at least one scan flop associated with a fault in an integrated circuit. A first test pattern, including a first scan-in data and first control data, is generated. Based on the first control data of the first test pattern, a first fault data is generated by applying the first scan-in data of the first test pattern to scan flops in a test circuit of the integrated circuit. If the first fault data indicates that a fault may be present in the integrated circuit, a second test pattern, including a second scan-in data and a second control data is generated.

Abstract: A receiver circuit etc. which can receive a high-speed signal is provided without providing a PLL circuit etc. A first receiver circuit for capturing an input signal at a plurality of capture timings determined based on a capture clock signal, includes a delay circuit configured to delay the input signal by a set delay time, and output the delayed input signal, a data latch circuit configured to capture the input signal delayed by the delay circuit at each capture timing, a data test circuit configured to test a latch signal captured by the data latch circuit, and a data test result register configured so that a test result value is set therein. The data test circuit compares the latch signal captured by the latch circuit at each capture timing with an expected value, and outputs the result of the comparison.

Abstract: Disclosed is a storage interface apparatus for a solid state drive (SSD) tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used in a multiple interface for interfacing a storage. The storage interface apparatus for the solid state driver tester includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for generating a test pattern corresponding to the test condition to test the storage. The test control unit includes a storage interface unit for interfacing the storage, and the storage interface unit includes a plurality of interfaces that share a protocol in parts where the protocol is commonly used.

Abstract: In this invention, a test system includes a tester and a switching module for connecting any pin to the tester for testing a device-under-test (DUT), the test system has a rectifying device between the ground of the DUT and the ground of the switching module in order to isolate the DUT from the switching module, thereby blocking unwanted current flowing between the DUT and the switching module to ensure the correctness of the testing. Since the ground of the switching module is not directly connected to the ground of the DUT and the tester, the rectifying device will keep the voltage difference between the ground of the switching module and the DUT in a range between zero and the cut-in voltage of the rectifying device, thereby allowing single-ended signals to be used between the switching module and the tester or the DUT.

Abstract: A semiconductor device includes a compression block configured to compare and compress data of a plurality of core array blocks, by a unit of a group; a combination block configured to combine outputs of the compression block and output compression data; and a control block configured to latch the compression data and output latched data, and drive the latched data and the compression data and output resultant data to a first data line and a second data line.

Abstract: A test generator generating a test for a system having a plurality of executing entities that are capable of concurrent execution, the test comprises transactions that comprise one or more access transactions that are configured to access a shared resource and one or more reconfiguration transactions configured that are configured to reconfigure the shared resource, wherein said generating comprises: determining a partial order between pairs of transactions that are both associated with the shared resource and that at least one of which is a reconfiguration transaction; and generating the test so as to enforce the partial order during execution of the test by the system.

Abstract: Techniques for debugging an application are provided. In some examples, a user interface (such as a graphical user interface) is provided for a user to specify a breakpoint associated with a breakpoint location in an application and a message flow direction associated with the breakpoint. The message flow direction may be selected from one or more message flow directions associated with the breakpoint location. For example, a message flow direction may be a request message flow direction or a reply message flow direction. The breakpoint location may be a logical breakpoint location associated with a component in a component-based application such as an application based on Service Component Architecture (SOA). In an embodiment, an execution of the application is suspended when the breakpoint is reached in connection with the specified message flow direction.

Abstract: Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them.

Abstract: In one embodiment, a method includes executing a first forward loop of a detection algorithm on a block of signal samples during a first time interval, executing a first reverse loop of the detection algorithm on the block during a second time interval to produce first soft information, executing a decoding algorithm on the block during a third time interval using the first soft information to produce second soft information, executing a second forward loop of the detection algorithm on the block during a fourth time interval using the second soft information, executing a second reverse loop of the detection algorithm on the block during a fifth time interval to produce third soft information, executing the decoding algorithm on the block during a sixth time interval using the third soft information to produce a decoded block of signal samples, and outputting the decoded block of signal samples.

Abstract: An apparatus may include: first circuitry configured to operate at a first frequency; second circuitry configured to operate at a second frequency that is different from the first frequency, where the second circuitry is for receiving input from, and for providing output to, the first circuitry; and logic that bridges the first circuitry and the second circuitry. The logic to enables the second circuitry to appear to run an integer number of cycles of the first frequency, and operates by receiving first signals at the first frequency and generating second signals at the second frequency, where the second signals are for triggering operations performed by the second circuitry. The apparatus may also include an output buffer circuit bridging the first circuitry and the second circuitry.

Abstract: A system and method for verifying that a processor design having caches conforms to a specific memory model. The caches might not be maintained coherent in real time. Specifically, the system and method make use of a checker that conforms to the memory model, a time-stamping scheme, and a store buffering scheme to identify a bug(s) in the processor design that violates the memory model and/or loads an incorrect value in response to a load instruction.

Abstract: A circuit includes a plurality of scan chains each including a plurality of scan blocks. Each scan block includes a storage element and a switching device having an output directly coupled to an input of the storage element. The switching device has a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed and a second input configured to receive one of a function logic output signal or a scan input signal. The switching device is configured to selectively couple the first input or the second input to the input of the storage element.

Abstract: Measurements, e.g. S-parameter measurements may be performed by obtaining a complex ratio of at least two signals, using a single signal-receiver while eliminating noise problems traditionally associated with single receiver systems. A Vector Signal Generator (VSG) may be used to generate the input stimulus (signal), making it possible to share the local oscillator (LO) signal of the VSG with a single vector receiver, such that the phase noise of the LO signal is common to both the VSG and the vector receiver. When the stimulus signal from the VSG is observed with the vector receiver, the LO phase noise is unobservable, resulting in a significant reduction of the phase noise in the measured signals in both the numerator and the denominator, which in turn leads to a significant reduction in the phase noise of the ratio while retaining the benefits of a simple, single receiver.

Abstract: A method for enabling concurrent testing is described. The method includes generating a plurality of test objects on a computing device. The plurality of test objects is generated using derived classes that are based on a base test class and each of the plurality of test objects corresponds to a separate block in a Device Under Test (DUT). The method also includes adding the plurality of test objects to a queue and sending information based on the plurality of test objects to an Automated Test Equipment (ATE). The method also includes causing the ATE to concurrently test the separate blocks in the DUT using the plurality of test objects.

Abstract: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment.

Abstract: In general, the disclosure relates to techniques for identifying a reduced set of remediation actions that are to be performed by a network endpoint to achieve compliance with a security policy defined by a network entity. One example method comprises receiving integrity data via a network from a network endpoint, performing a plurality of tests on the integrity data to generate corresponding test results, identifying a set of remediation actions based upon the test results, and comparing the remediation actions in the set. The method further comprises eliminating at least one remediation action in the set based upon the comparison to form a reduced set of remediation actions, and sending the reduced set of remediation actions to the network endpoint, wherein each remediation action in the reduced set specifies an action to be performed by the network endpoint to achieve compliance with a security policy.

Abstract: An unchecked signal detection mechanism runs simulation tests of circuit designs that normally pass. Before a simulation test is run, noise is injected into one randomly chosen signal. A random constant value is assigned to the randomly chosen signal. The constant random value is forced on the selected signal for the duration of the simulation test. Signals for which simulation tests always pass, even when their value is forced, are likely not checked and declared as suspect. The subset of suspect signals is then checked to determine whether their checkers are indeed missing or defective. Any verification flaws (holes) found are then fixed.

Abstract: A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out.

Abstract: A method and an apparatus for dynamic signal switching with multiple measurement sources, for a merging unit in an electrical power system, said merging unit receiving at least two input signals from at least one current transformer measuring the same physical primary quantity. The method comprises a step of outputting from said merging unit, in a real-time mode, a digitized output stream of sampled values with the truest representation of the physical primary quantity, based on the actual values of the input signals.

Abstract: Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.

Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.

Abstract: A method, system, and computer program product to test a semiconductor device are described. The system includes an input interface to receive a set of test patterns to test the semiconductor device and a user selection corresponding to a subset of the set of test patterns. The system also includes a processor to process the subset of the set of test patterns to output test data to the semiconductor device.

Abstract: A method, system, and computer program product to test a semiconductor device are described. The method includes receiving a set of test patterns for testing the semiconductor device and a user selecting a subset of the set of test patterns. The method also includes cataloging a content of pattern files associated with the subset of the set of test patterns to generate a catalog, and processing the catalog to output test data to the semiconductor device.