Abstract: A semiconductor device includes an error correction circuit and a write operation control circuit. The error correction circuit generates corrected data and an error flag from read data according to whether an error is included in the read data outputted when a read operation is performed. The write operation control circuit generates a write control signal for controlling a write operation based on the error flag.

Abstract: A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.

Abstract: A method and system for transferring encrypted data from a first electronic device to a second electronic device. The method includes the steps of displaying a first encrypted two-dimensional code at the output interface of the first electronic device, reading the first encrypted two-dimensional code with the input interface of the second electronic device, and decrypting the first two-dimensional code with the second electronic device, generating a second encrypted two-dimensional code with the second electronic device, and displaying the second encrypted two-dimensional code on the output interface of the second electronic device, reading the second two-dimensional code encrypted with the input interface of the first electronic device and decrypting the second two-dimensional code with the first electronic device and generating an action on the first electronic device based on the second decrypted two-dimensional code. The second two-dimensional code is a plurality of two-dimensional codes.

Abstract: An FEC codec module is provided. Code elements, i.e., code words of forward error correction code, are added to the data code stream of each transmission link through the codec module, so that accurate error determination and automatic error correction may be realized at the receiving end. The interleaving process is performed on multi-link data to prevent the occurrence of continuous burst errors in the data link in a transmission process, and the error correction capability of FEC is utilized to improve the data transmission efficiency and anti-interference ability of the system.

Abstract: A memory device includes: a memory device configured to store data bits to be written to the memory device; and a memory controller. The memory controller includes: a first level error correction code (ECC) circuit coupled to the memory device, wherein the first level ECC circuit is configured to generate a first plurality of first level check bits corresponding to the data bits based on a first error detection scheme; and a second level ECC circuit coupled to the memory device, wherein the second level ECC circuit is configured to generate a second plurality of second level check bits corresponding to both the data bits and the first plurality of first level check bits based on a first error correction scheme.

Abstract: A system and method for adaptive RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to determine a first RAID layout for use in storing data, and write a first RAID stripe to the device group according to the first RAID layout. In response to detecting a first condition, the controller is configured to determine a second RAID layout which is different from the first RAID layout, and write a second RAID stripe to the device group according to the second layout, whereby the device group concurrently stores data according to both the first RAID layout and the second RAID layout.

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

Abstract: A method and device for energy-efficient decoders. The decoder device can include a plurality of decoder modules configured to process an input data signal having a plurality of forward error correction (FEC) codewords. This plurality of decoder modules can include at least a first decoder followed by a second decoder. The first decoder can be low-power to first eliminate most of the errors of the codewords and the second decoder can be high-performance to correct the remaining errors. Alternatively, the first decoder can be high-performance to correct the codewords until the low-power decoder can correct the remaining errors. A classifier module can be included to determine portions of the codewords to be directed to any one of the plurality of decoder modules. These implementations can be extended to use additional decoders with different decoding algorithms and optimized to maximize decoder performance given a maximum power constraint.

Abstract: Systems and methods are provided for implementing forward error correction (FEC) on data transferred on a data link on the physical layer. Binary encoding can be done in accordance with a physical unit (phit) FEC format. The phit FEC format allows for correction of two bit errors and comprises a codeword having a variable bit size. Pre-coding the phit enables burst errors associated with the link to converted into bit errors. The data can be transmitted in the phit FEC format to a receiving PHY. The correctable two bit errors at one or more locations within the phit FEC format can then be corrected by decoding at the receiving PHY in accordance with the phit FEC. The FEC techniques can minimize latency in the PHY.

Abstract: Methods, systems, and devices for latency minimization in wireless communications employing multi-level coding and multi-level sequential demodulation and decoding are described. A user equipment (UE) receive a set of codeblock groups in a first time period. Each codeblock group jointly sharing same channel resources may be associated with a respective decoding level of a set of decoding levels. The UE may determine a first outcome for a first codeblock group and a second outcome for a second codeblock group. The UE may then transmit a feedback message that is based on the first outcome and the second outcome. In case that the feedback message indicates that the first outcome or the second outcome is a failed decoding procedure, the UE may receive, in a second time period, a retransmission of all the codeblock groups. These retransmissions may continue on additional time periods until all related codeblock groups are successfully decoded.

Abstract: A deinterleaving method and a deinterleaving system performing the same are disclosed. According to an example embodiment, a data processing method includes dividing data into first data blocks of a first number of bits, performing deinterleaving on the first data blocks, and dividing deinterleaved data into second data blocks of a second number of bits and outputting the second data blocks, wherein the first number of bits is determined based on a minimum switching unit of a deinterleaving operation and the second number of bits.

Abstract: An encoder apparatus for reliable transfer of a source data block d in a communication system includes an outer transform configured to receive a data container block v and compute an outer transform block u, whereby u=vGout for an outer transform matrix Gout. The encoder apparatus also includes an inner transform configured to receive the outer transform block u and compute a transmitted code block x, whereby x=uGin for an inner transform matrix Gin. The data container block v is obtained from the source data block d and a frozen data block a. The frozen data block a is a predetermined block of symbols. The outer transform matrix Gout and the inner transform matrix form a triangular factorization of a transform matrix G, which optionally is a non-triangular matrix, while the outer transform matrix Gout and the inner transform matrix Gin are strictly upper- and lower-triangular matrices, respectively.

Abstract: Methods and system for error correction based on rate adaptive LDPC codes with flexible column weights in the parity check matrices are described. Data is encoded according to a first encoding parity check matrix of a first Low Density Parity Check (LDPC) code to obtain a first codeword with first parities. The first codeword is encoded according to a second encoding parity check matrix of a second LDPC code to obtain second parities. The first codeword is received. Responsive to failure of error correction of the first codeword based on the first parities, the second parities are received. The first codeword is corrected based on the second parities and a decoding parity check matrix of a rate adaptive LDPC code that is constructed by vertically concatenating the second encoding parity check matrix and the first encoding parity check matrix and adding an all-zero sub-matrix to complete its dimensions.

Abstract: An image of a check may be presented for payment in a banking system in place of the physical paper check. The check to be deposited can be collected from a depositor using a scanner. A web site, accessed through a depositor's web browser, can be used to drive the process of collecting the check, but in some contexts (e.g., in less popular computing environments, such as those that do not run the most popular operating systems), it is economically infeasible to obtain the certificates that would be used to allow a program executing in the web browser to control the scanner. Thus, a depositor can be instructed to capture and upload images of the check in the form of files, where the image files are then presented for payment through a banking system.

Abstract: This application discloses a service signal transmission method and apparatus, and belongs to the field of communications technologies. The method includes: obtaining, by a first network device, N first service signals, where coding types of the N first service signals are the same, and at least two of the N first service signals have different transmission rates, where N?2; inserting padding signals into the N first service signals, to obtain N second service signals, where transmission rates of the N second service signals are integer multiples of a reference rate; and multiplexing the N second service signals into one third service signal, and sending the third service signal to a second network device. In this application, the padding signals are inserted into the N first service signals, to obtain the N second service signals whose transmission rates have an obvious integer-ratio characteristic.

Abstract: A decoding method and device for Turbo product codes, a decoding device, a decoder and a computer storage medium are provided. The method includes: a received codeword of a Turbo product code is acquired, and iterative decoding is performed on the received codeword for a set first iterative decoding times (S101); a decoding result of iterative decoding performed for the first iteration times is judged according to a first decoding rule to obtain a decoding identifier representing the decoding result (S102); and error correction processing is performed on the Turbo product code on which iterative decoding is performed for the first iteration times according to the decoding identifier (S103).

Abstract: Embodiments of this application disclose a polar coding method, apparatus, and device, so as to reduce storage overheads of a system. A sequence for polar coding is obtained based on a length M of a target polar code, wherein the sequence comprises L sequence numbers, ordering of the L sequence numbers in the sequence is the same as ordering of the L sequence numbers in a maximum mother code sequence, wherein the maximum mother code sequence is obtained by sorting N sequence numbers of N polarized channels in ascending order or descending order of reliability metrics, wherein L and N are integer power of 2, M is smaller than or equal to L, L is smaller than or equal to N.

Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

Abstract: Systems and methods for host-assisted storage device error correction are described. A host may first encode host data with a forward error correction code (ECC) and send the encoded host data to the storage device. The storage device may further encode the host data using its own ECC. The host may also provide the forward ECC parity information to be stored on the storage device in a different location than the host data. When the host data is read by the storage device, the storage device will decode with its ECC. If the storage device ECC decode is incomplete and the bit error rate is below the recoverable error threshold of the forward error correction, the partially-recovered host data will be sent to the host. The host will complete decode using the forward ECC and parity data. Forward ECC may be selectively applied to important host data.

Abstract: The present invention relates to a method for a secure execution of a whitebox cryptographic algorithm applied to a message (m) and protected by countermeasures based on pseudo-random values, comprising the steps of: executing a pseudo-random function (PRP) generating pseudo-random output values and an encrypted main output value based on an encrypted input value (*Xi*) derived from said message, securing said cryptographic algorithm by applying to the cryptographic algorithm said countermeasures based on said generated pseudo-random output values retrieving, from said generated encrypted main output value, the input value or part of the input value, under an encrypted form (*Xi*), executing said secured cryptographic algorithm on said encrypted retrieved value.

Abstract: A method begins by a processing module of a storage network receiving a first plurality of pairs of coded values corresponding to first data segments of a first data stream and a second data stream. The method continues with the processing module generating a received coded matrix to include a plurality of groups of selected coded values and when the received coded matrix includes a decode threshold number of pairs of coded values, generating a data matrix from the received coded matrix and an encoding matrix. The method continues with the processing module reproducing the first data segment of the first and second data streams, while maintaining the time alignment of the first and second data streams.

Abstract: A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.

Abstract: Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.

Abstract: Techniques of memory operations management are disclosed herein. One example technique includes retrieving, from a first memory, data from a data portion and metadata from a metadata portion of the first memory upon receiving a request to read data corresponding to a system memory section. The method can then include analyzing the data location information to determine whether the first memory currently contains data corresponding to the system memory section in the received request. In response to determining that the first memory currently contains data corresponding to the system memory section in the received request, transmitting the retrieved data from the data portion of the first memory to the processor in response to the received request. Otherwise, the method can include identifying a memory location in the second memory that contains data corresponding to the system memory section and retrieving the data from the identified memory location.

Abstract: A memory system may include a memory controller suitable for transmitting write data and a first write ECC corresponding to the write data during a write operation, a first error correction circuit suitable for detecting whether the write data received from the memory controller has an error, using the first write ECC received from the memory controller, and correcting the error when the error is detected, a second ECC generation circuit suitable for generating a second write ECC using the write data received from the memory controller, and generating the second write ECC using the write data whose error has been corrected by the first error correction circuit, when the detection of the error is noticed from the first error correction circuit, and one or more memories suitable for storing the second write ECC and write data corresponding to the second write ECC.

Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system and performing error recovery for the set of CWs using a set of error handing (EH) steps until each CW of the set of CWs are indicated as correctable in the error recovery data structure. The error recovery can include determining if each CW of the set of CWs is correctable by an EH step, storing indications of CWs determined correctable by the EH step in the error recovery data structure, determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for channel bonding in an adaptive coding and modulation mode. In some implementations, a system receives packets of a data stream for transmission in a satellite communications system. The system determines a modulation and coding arrangement for the received packets. The system generates code blocks that include data from the packets of the data stream. The system assigns the generated code blocks for transmission on different carriers. One or more of the different carriers is operated in an adaptive coding and modulation mode to support multiple modulation and coding arrangements within a single carrier. The system transmits the code blocks on the different carriers using the determined one or more modulation and coding arrangements.

Abstract: N storage nodes that are coupled via a network are selected to store a file of size |F| and redundancy of size |Fred|. A value Z<N is selected such that an attacker having access to Z storage nodes is unable to decode any partial information of the file. The file is divided into d partitions of size |PsN|, wherein |PsN| is a maximum factor of |F| subject to |PsN|?|sN|. Independent linear combinations hi's of the d partitions are created and random keys are generated and stored in the first Z of the N storage nodes. Independent linear combinations gi's of the random keys are created and combinations of the hi's and gi's are stored in the Z+1 to Nth storage nodes.

Abstract: Provided are a signaling coding and modulation method and a demodulation and decoding method and device, characterized in that the method comprises the steps of: extending signaling which has been subjected to first predetermined processing according to an extension pattern table to obtain an extended codeword, and conducting predetermined coding on the extended codeword to obtain a encoded codeword; conducting parity bit permutation on a parity bit portion in the encoded codeword and then splicing the permutated parity bits to the end of information bits in the encoded codeword, to obtain a permutated encoded codeword; according to the length of the signaling, punching the permutated encoded codeword according to a predetermined punching rule to obtain a punched encoded codeword; and conducting second predetermined processing on the punched encoded codeword to obtain a tuple sequence, which is used for mapping, and then mapping the tuple sequence.

Abstract: Embodiments of the present disclosure provide methods and apparatuses for data processing in a communication system. For example, the method comprises: generating, based on an intended performance, an error detection code to be used; distributing bits of the error detection code in information bits to be coded; and perform polar encoding on the information bits together with the error detection code distributed in the information bits. The embodiments of the present disclosure also provide a communication device capable of implementing the method.

Abstract: In various embodiments, the disclosed systems, methods, and apparatuses describe the application of non-orthogonal multiple access (NOMA) over networks (e.g., cable networks). In particular, the disclosure describes: determining a signal for transmission to a receiving device; determining, by a processing component of the device, parameters associated with the transmission of the signal, the parameters comprising at least one of a power level, a modulation scheme, a frequency band, and a power spectral density; and transmitting, by a transmitting component of the device, the signal over a medium based on the parameters and using a NOMA technique.

Abstract: Recovery of chunk segments stored via hierarchical erasure coding in a geographically diverse data storage system is disclosed. Chunks can be stored according to a first-level erasure coding scheme in zones of a geographically diverse data storage system. The chunks can then be further protected via one or more second-level erasure coding schema within a corresponding zone of the geographically diverse data storage system. In response to determining a segment of a chunk has become less accessible, recovering at least the segment to enable intra-zone recovery of the compromised chunk can be performed according to the hierarchical erasure coding scheme of relevant chunks at relevant zones of the geographically diverse data storage system.

Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.

Abstract: Systems and methods for ACM trajectory include receiving data at a communications receiver; decoding the received data based on a selected MODCOD; monitoring a number of iterations used to decode the data using the selected MODCOD; comparing the number of iterations used to decode the data using the first selected MODCOD to a reference number of iterations; and adjusting a SNR threshold value for the selected MODCOD where the number of iterations used to decode the data using the first selected MODCOD is greater than the reference number of iterations.

Abstract: An integrated circuit is provided. The integrated circuit includes a first volatile memory, a second volatile memory, and a video decoder. In response to the video decoder starting video decoding on a current frame of a video stream, the video decoder reads an initial probability table for the current frame from a memory unit external to the integrated circuit, and stores the initial probability table in the first volatile memory. When a decoding phase of the current tile is completed, the video decoder complements the probability table corresponding to each row of the second volatile memory according to control flags corresponding to the rows of the first volatile memory and the second volatile memory to obtain a complete probability table, and writes the complete probability table to the memory unit.

Abstract: Channel encoding is provided that includes applying turbo coding with a coding rate of 1/5 to an input bit sequence, applying a subblock interleaver to each of first to fifth code bit sequences to which the turbo coding is applied, applying bit collection to the first to fifth code bit sequences output from the subblock interleaver, the bit collection outputting the first code bit sequence in order, outputting the second code bit sequence and the fourth code bit sequence alternately on a bit-by-bit basis after the first code bit sequence, and outputting the second code bit sequence and the fifth code bit sequence alternately on a bit-by-bit basis.

Abstract: A data processing apparatus is provided, which includes storage circuitry comprising a plurality of lines, each of the plurality of lines comprising a data value. Access circuitry accesses a pair of the plurality of lines at a time, the pair of the plurality of lines comprising a further data value, distinct from the data value, and a plurality of error bits to detect or correct errors in the data value in each line in the pair of the plurality of lines.

Abstract: A communication system includes a transmitter having an encoder configured to encode input data using FEC codewords and a receiver including a decoder configured to decode the FEC codewords using a parity check matrix. The decoder includes check node processing units each configured to perform a check node computation on an FEC codeword using a different row of the parity check matrix. Each of the check node processing units includes an input computation stage configured to compute initial computation values, a pipelined message memory configured to shift the initial computation values at a predefined clock interval, an output computation stage configured to generate a plurality of check node output messages, a plurality of variable node processing units each configured to perform variable node update computations to generate the variable node messages, and an output circuit configured to generate a decoded codeword based on the variable node messages.

Abstract: An operation method of a first communication node in a communication system includes receiving a signal from a second communication node; demodulating the signal to obtain LLR values; calculating a first codeword based on the LLR values; selecting error patterns from among all error patterns based on Hamming weights; generating second codewords by applying the first codeword to each of the selected error patterns; and determining a codeword having a highest similarity to the first codeword among the second codewords as an optimal codeword.

Abstract: A method for generating an LDPC (low-density parity check) code with a required error floor, comprising: using a parity generation circuit to generate an LDPC code; using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information; using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information; using the verification circuit to separately compare each of the estimated error floors with an expected error floor; and when all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code.

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.

Abstract: A data storage device configured to access a magnetic tape is disclosed, wherein the data storage device comprises at least one head configured to access the magnetic tape. A first plurality of data blocks are encoded into a first plurality of ECC sub-blocks including a first ECC sub-block, and the first plurality of ECC sub-blocks are encoded into a first ECC super-block. The first ECC sub-block is written to the magnetic tape, and a write-verify of the first ECC sub-block is executed by reading the first ECC sub-block. When the write-verify passes, a second plurality of data blocks are encoded into a second ECC super-block, and when the write-verify fails, a third plurality of data blocks and the first ECC sub-block are encoded into the second ECC super-block, wherein the second ECC super-block is written to the magnetic tape.

Abstract: Multiple memory systems with respective decoders employ a low latency implementation of a read recovery level feature in decoding data. The decoding comprises receiving from a host a read request for decoding read data at a first recovery level by a first memory system, a first decoder of the first memory system being set at a second recovery level with a corresponding maximum iteration number when the read request is received by the first memory system; and operating the first decoder, after a set time elapses, to decode the read data at the second recovery level. A second decoder of a second memory system is set at the first recovery level for at least part of the time during which the first decoder operates to decode the read data at the second recovery level.

Abstract: This application provides a polar encoding and decoding method, a sending device, and a receiving device, to help overcome disadvantages in transmission of medium and small packets, a code rate, reliability, and complexity in the prior art.

Abstract: A memory system including a memory device and a memory controller including a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host and to convert the read outputs to a first codeword. The processor performs a first error correcting code (ECC) operation on the first codeword. The processor is further configured to apply, for each selected memory cell among the memory cells, a corresponding one of the read outputs and at least one related feature as input features to a machine learning algorithm to generate a second codeword, and the memory controller is configured to perform a second ECC operation on the second codeword, when the first ECC operation fails.

Abstract: Devices, systems and methods for reducing complexity of a bit-flipping decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular QC-LDPC code, the irregular QC-LDPC code having an associated parity matrix, storing, based on a weight of a plurality of columns of the parity matrix of the irregular QC-LDPC code, a portion of the noisy codeword corresponding to the plurality of columns in a first buffer of a plurality of buffers, and accessing and processing the portion of the noisy codeword that includes applying a vertically shuffled scheduling (VSS) scheme that uses a plurality of processing units to determine a candidate version of a portion of the transmitted codeword that corresponds to the portion of the noisy codeword.

Abstract: Certain aspects of the present disclosure generally relate to techniques for encoding and decoding bits of information using cyclic redundancy check (CRC) concatenated polar encoding and decoding. The CRC concatenated polar encoding techniques may avoid transmission of dummy bits. A method generally includes obtaining the bits of information to be transmitted. The method includes performing CRC outer encoding of the bits of information using an even-weighted generator polynomial to produce CRC encoded bits. The method includes performing polar inner encoding of the CRC encoded bits to generate a codeword. The method includes discarding a first code bit at a beginning of the codeword. The shortened codeword is transmitted over a wireless medium. In another method, bit-level scrambling is performed on the CRC encoded bits before the polar encoding to avoid generating a dummy bit. In another method, only odd-weighted generator polynomials are selected to avoid generating the dummy bit.

Abstract: Systems and methods include receiving blocks of data that has been Forward Error Correction (FEC) encoded via Open Forward Error Correction (OFEC) adaptation; decoding the blocks of data; processing Cyclic Redundancy Check (CRC) data that is included in padding data required in the OFEC adaptation, wherein the padding data is distributed across N rows of payload data; and determining a location of any errors in the payload data based on the processed CRC data. The OFEC adaptation is for mapping the blocks of data into any of a FlexO-x frame structure, a ZR frame structure, and variants thereof, and the location of any errors can be used for error marking.

Abstract: A decoder decodes a soft information input vector represented by an input vector that is binary and that is constructed from the soft information input vector. The decoder stores even parity error vectors that are binary and odd parity error vectors that are binary for L least reliable bits (LRBs) of the input vector. The decoder computes a parity check of the input vector, and selects as error vectors either the even parity error vectors or the odd parity error vectors based at least in part on the parity check. The decoder hard decodes test vectors, representing respective sums of the input vector and respective ones of the error vectors, based on the L LRBs, to produce codewords that are binary for corresponding ones of the test vectors, and metrics associated with the codewords. The decoder updates the soft information input vector based on the codewords and the metrics.