Abstract: Methods and apparatus for successive interference cancellation (SIC). In an embodiment, a method includes receiving symbols from a plurality of user equipment (UE), identify a target UE and non-target UEs, decoding code blocks from the symbols received from the non-target UEs to generate decoded bits for each code block. The method also includes performing a CRC check on each code block to generate a tag (0) when the CRC check passes and a tag (1) when the CRC check fails, and re-encoding the decoded bits to generate re-encoded code blocks having the associated tags attached. The method also includes reconstructing symbols from the re-encoded code blocks where symbols reconstructed from re-encoded code blocks having tag (0) are reconstructed with data and symbols reconstructed from re-encoded code blocks having tag (1) are reconstructed as zero value symbols, and utilizing the reconstructed symbols to cancel interference on symbols from the target UE.

Abstract: When a plurality of write data is merged to generate a code for protecting data stored in the main memory, the write data is protected in the memory controller. A first code generation unit generates a first code based on the write data stored in a first sub memory, and stores the generated first code in a second sub memory. The sub memory controller reads the write data to be merged from the first sub memory, and verifies whether the read write data includes an error by using the first code stored in the second sub memory. When the read write data does not include an error, the sub memory controller merges valid data of the write data read from the first sub memory, and outputs the merged data to a second code generation unit. The second code generation unit generates a second code based on the merged data.

Abstract: One embodiment provides a system and method for facilitating error-correction protection in a storage device. In response to a write request, the system organizes a block of data in a two-dimensional (2D) array, forms a plurality of first-dimension sub-blocks by dividing the 2D array along a first dimension, and forms a plurality of second-dimension sub-blocks by dividing the 2D array along a second dimension. In response to determining that second-dimension error correction code (ECC) encoding is enabled, the system performs second-dimension ECC encoding on the second-dimension sub-blocks to generate a set of second-dimension ECC bits and performs first-dimension ECC encoding on the first-dimension sub-blocks and the second-dimension ECC bits to generate a set of first-dimension ECC bits. The system writes the data block along with the second-dimension ECC bits and the first-dimension ECC bits to the storage device.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.

Abstract: An error correcting code (ECC) decoder for a non-volatile memory device is configured to decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights. The ECC decoder is further configured to artificially slow processing of one or more of the columns of the parity check matrix in response to column weights for the one or more columns satisfying a threshold.

Abstract: A method for performing encoding on the basis of a parity check matrix of a LDPC code, according to one embodiment of the present invention, comprises the steps of: generating, by a terminal, a parity check matrix, wherein the parity check matrix corresponds to a characteristic matrix, each element of the characteristic matrix corresponds to a shift index value determined by a modulo operation between a corresponding element in a base matrix and a lifting value, and the base matrix is a 46×68 matrix; and performing, by the terminal, encoding of input data by using the parity check matrix, wherein the lifting value is associated with the length of the input data.

Abstract: This disclosure presents a technique to include a packet sequence number and an integrity check value (ICV) into a data frame while maintaining a total number of transmitted bytes. A transmitting device includes circuitry that generates the ICV, inserts a transmitter packet sequence number into the data frame that includes a data packet including a payload, the data packet following a preamble and an interpacket gap (IPG) following the data packet. The circuitry also inserts the ICV into the data frame, and transmits the data frame, wherein inserting the ICV into the data frame reduces a size of the IPG while maintaining a total number of bytes in the data frame. A receiving device includes circuitry that receives the data frame, compares a receiver packet sequence number to the transmitter packet sequence number, and determines whether the transmitter packet sequence number is valid based on the receiver packet sequence number.

Abstract: A memory controller is configured to perform first error correcting code (ECC) encoding on a plurality of first frames of data, generate a plurality of delta syndrome units corresponding, respectively, to the plurality of first frames of data, generate a delta syndrome codeword by performing second ECC encoding on the plurality of delta syndrome units, the delta syndrome codeword including one or more redundancy data units, perform third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits, and determine a second vector of bits such that, adding the second vector of bits to the first vector of bits forms a combined vector of bits which is an ECC codeword having a delta syndrome a value of which is pre-fixed based on at least one of the one or more redundancy data units.

Abstract: An operating method of a memory controller to update metadata using journaling data in a short time during a booting operation, and to maintain reliability of the updated metadata. The operating method of a memory controller includes loading metadata into sub-regions of a buffer memory, updating the metadata using journaling data in a state that error correction code (ECC) functions of memory controller for the sub-regions are disabled, generating a first parity data of data stored in the first sub-region, and enabling the ECC function of the first sub-region, after the first parity data is generated.

Abstract: The invention relates to method and apparatus for improving the performance of communication systems using Run length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.

Abstract: A method is disclosed for use in an electronic device having a non-volatile storage device and a volatile storage device, the method comprising: retrieving a first encoded data packet from a first address in the non-volatile storage device; decoding the first encoded data packet to obtain a first data item and a first error code corresponding to the first data item, the first encoded data packet being decoded by using a first coding key that is associated with the first address; detecting whether the first data item is corrupt based on the first error code and an error correction function, storing the first data item at a first address in the volatile storage device when the first data item is not corrupt, and transitioning the electronic device into a safe state when the first data item is corrupt.

Abstract: A mobile terminal is provided. The mobile terminal includes a light emitter, a light receiver, a light fidelity (LiFi) controller coupled with the light emitter and the light receiver, and a time-of-flight (TOF) controller coupled with the light emitter and the light receiver. The LiFi controller is configured to control the light emitter to emit a signal and control the light receiver to receive another signal. The TOF controller is configured to control the light emitter to emit a measurement light and determine a measured distance by performing distance measurement according to a reflected light of the measurement light received by the light receiver.

Abstract: Provided is a method for writing and deleting files on a tape medium and a cache storage device. The method includes receiving a command to write one or more files of a directory to a tape medium. The method further includes identifying a cache limit associated with the tape medium. The method further comprises determining whether the amount of data of the directory that is already on the cache storage device exceeds the cache limit. In response to the amount of data not exceeding the cache limit, the method includes writing data of the one or more files to the cache storage device and the tape medium in parallel.

Abstract: A malicious code detection module identifies potentially malicious instructions in volatile memory of a computing device before the instructions are executed. The malicious code detection module identifies an executable file, including an .exe file, in memory, validates one or more components of the executable file against the same file stored in non-volatile storage, and issues an alert if the validation fails.

Abstract: A data storage device has a controller that is configured to generate SECDED codes based on a plurality (at least 2) of codes, where each of the constituent codes is a cyclic code over a finite field of size 2m for some integer m. Any 2 constituent codes are associated with 2m1 and 2m2, where m1 and m2 are coprime (i.e., gcd(m1,m2)=1) where gcd is the greatest common divisor. In such a case, it is possible to generate a cyclic code of length (2m1?1)*(2m2?1), which will be a long code, but enjoy the complexity, in encoding and decoding, of the small fields of the constituent codes.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.

Abstract: A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.

Abstract: The embodiments of the present disclosure provide a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding.

Abstract: A storage system has a controller with an encoder. The encoder is configured to perform first and second stages of an encoding process in parallel on pipelined data blocks. In this way, while the first stage of the encoding process is being performed on a first data block, the second stage of the encoding process is performed on a second data block.

Abstract: The present disclosure relates to information transmission method, decoding method, and apparatus. One example method includes encoding, by a sending device, a to-be-encoded sequence based on preset parameters to obtain an encoded sequence, where the preset parameters include a quantity of check bits, positions of the check bits, and a check equation, and sending the encoded sequence to a receiving device.

Abstract: This application relates to the communications field, and discloses an encoding method, a decoding method, an encoding apparatus, and a decoding apparatus. The encoding method includes: receiving a data bitstream; performing forward error correction FEC encoding on the data bitstream to obtain X Reed-Solomon RS outer codes, where each of the X RS outer codes includes N1 symbols, K1 of the N1 symbols are payload symbols; and performing FEC encoding on the X RS outer codes to obtain Y RS inner codes, where each of the Y RS inner codes includes N2 symbols, K2 of the N2 symbols are payload symbols. According to this application, error correction performance of FEC decoding can be improved.

Abstract: Devices and methods for error correction are described. An exemplary error correction decoder includes a mapper configured to generate, based on a first set of read values corresponding to a first codeword, a first set of log likelihood ratio (LLR) values; a first buffer, coupled to the mapper, configured to store the first set of LLR values received from the mapper; and a node processor, coupled to the first buffer, configured to perform a first error correction decoding operation using the first set of LLR values received from the first buffer, wherein a first iteration of the first error correction decoding operation comprises refraining from updating values of one or more variable nodes, and performing a syndrome check using a parity check matrix and sign bits of the first set of LLR values stored in the first buffer.

Abstract: A method for storing data. The method includes receiving data to write to persistent storage, calculating parity values for a grid using the data, where each of the parity values is associated with one selected from of the Row Q Parity Group, the Row P Parity Group, the Column Q Parity Group, the Column P Parity Group, and the Intersection Parity Group. The method further includes writing the data to a data grid in the persistent storage, where the data grid is part of the grid, and writing the parity values for the grid to a portion of the grid, where the portion of the grid comprises physical locations associated with a Row Q Parity Group, a Row P Parity Group, a Column Q Parity Group, a Column P Parity Group, and an Intersection Parity Group, wherein the portion of the grid is distinct from the data grid.

Abstract: This application discloses an information processing method and apparatus, a communications device, and a communications system. The method includes: encoding an input sequence by using a low density parity check LDPC matrix to obtain a bit sequence D, where a base matrix of the LDPC matrix is represented by a matrix of m rows and n columns, each column corresponds to a group of Z continuous bits in the bit sequence D, and both n and Z are integers greater than 0; and obtaining an output bit sequence based on a bit sequence V, where the bit sequence V is obtained by permuting groups of bits corresponding to at least two parity check columns in the bit sequence D.

Abstract: A physical broadcast channel (PBCH) transmission method and an apparatus. The method includes scrambling PBCH based on a first scrambling code of the PBCH, where the first scrambling code is one of four scrambling codes, where a combination of a second least significant bit and a third least significant bit of a system frame number (SFN) indicates one value of four values, and where the four scrambling codes have a one-to-one correspondence with the four values, and sending the PBCH to a terminal device.

Abstract: A flash memory controller is configured to decode a codeword. During the decoding process, the flash memory can check the decoding status of each codeword segment in the codeword and skip the decoding of a codeword segment whose decoding status is passed, thereby saving time decoding and also improving decoding efficiency. Even though only a part of the codeword segments in the codeword have been successfully decoded in the decoding process at the previous time, the flash memory controller can replace the part of the codeword segments in the codeword with the correct results obtained previously, and then decoding the re-formed codeword again. Accordingly, the decoding accuracy can be increased and the burden on the subsequent decoding process or data recovery can be reduced.

Abstract: A method for extracting path overhead (POH) data blocks from a data stream in a 64B/66B-block communication link, the method includes receiving at a sink node a data stream in a 64B/66B-block communication link, detecting within the data stream at a PCS sublayer a micro-packet starting with an /S/ control block, including K POH data blocks, and ending with a /T/ control block, extracting the micro-packet from the data stream, and extracting the POH data blocks from the micro-packet.

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may measure a physical channel such as a narrowband physical broadcast channel (NPBCH) to supplement (e.g., or as an alternative to) reference signal measurements when determining a received signal measurement, such as a received signal strength or received signal quality of a cell. A base station may transmit an indication to a UE that identifies the frequency at which a portion of NPBCH transmissions (e.g., reserved fields of a master information block (MIB)) is expected to change from one NPBCH transmission to another. The UE may adjust its utilization of NPBCH for determining the received signal measurement based on the indication. Further, the UE may communicate with the cell based on the determination of the received signal measurement, which are based on the indication.

Abstract: A method for polar encoding includes: receiving a message including information bits; encoding the message using a first polar code to obtain a first codeword; and encoding the message using a second polar code to obtain a second codeword. The second codeword includes two parts, and the first part of the second codeword is same as the first codeword. The method for polar encoding also includes transmitting the first codeword to a receiver in a first transmission; and transmitting the second part of the second codeword in a second transmission without transmitting the first part of the second codeword when the receiver is unable to decode the message based on the first codeword.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing blockchain data based on error correction code. One of the methods includes determining, by a blockchain node, block data associated with a current block of a blockchain; performing error correction coding of the block data to generate encoded data; dividing, based on one or more predetermined rules, the encoded data into a plurality of data sets; storing, based on the one or more predetermined rules, one or more data sets of the plurality of data sets; hashing each data set of remaining data sets of the plurality of data sets to generate one or more hash values corresponding to the remaining data sets; and storing the one or more hash values.

Abstract: Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.

Abstract: Provided is an optical transmission/reception device including an error correction decoding unit (36) for decoding a received sequence encoded with an LDPC code, in which the error correction decoding unit (36) is configured to perform decoding processing using a parity check matrix (70) of a spatially-coupled LDPC code, which includes a plurality of parity check sub-matrices (71) combined with each other, in which the decoding processing is windowed decoding processing that uses a window (80) over one or more parity check sub-matrices (71), and in which a window size of the window (80) and a decoding iteration count due to throughput and requested correction performance are variable and input from a control circuit (12) connected to the error correction decoding device (36).

Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.

Abstract: An apparatus comprising data processing circuitry for processing data in one of a plurality of operating states, an instruction decoder for decoding instructions and error checking circuitry for performing error checking operations. In response to a touch instruction being decoded by the instruction decoder, error checking operation is performed on selected architectural state. The architectural state is architecturally inaccessible to the operating state. As a result of the touch instruction, the architectural state remains unchanged, at least when no error is detected.

Abstract: A display panel driving apparatus includes an interface, a timing controller, a gate driver, and data driver. The interface includes a data determiner to determine whether or not input image data has a communication error and to process a packet of a data stream of the input image data, even though the input image data has the communication error. The timing controller receives the processed input image data from the interface and generates a data signal, a gate control signal, and a data control signal. The gate driver generates a gate signal based on the gate control signal. The data driver generates a data voltage based on the data control signal and the data signal.

Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

Abstract: An exemplary communications receiver includes an error detector for determining whether a first and second received frame is corrupted, each frame comprising of a plurality of bits. The receiver includes a filter for determining whether the second received corrupted frame should be recovered. The receiver includes a frame generator for generating a recovered frame based on the plurality of bits of the first and second corrupted frame and frame information of the second corrupted frame, in response to the error detector determining that the first and second received frames are corrupted and the filter determining that the second received frame should be recovered.

Abstract: This document discloses a solution for error detection. According to an aspect, a method comprises: generating, by a first apparatus, a transport block and error detection bits for the transport block; generating, by the first apparatus, a first number of code block groups by using the transport block and the error detection bits, wherein the first number is two or higher and based on a number of code blocks a second apparatus is able to decode in parallel processing; generating, by the first apparatus, error detection bits for at least one of the code block groups; generating, by the first apparatus, a plurality of code blocks for each code block group, and causing transmission of the plurality of code blocks to the second apparatus.

Abstract: An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.

Abstract: A technique of managing storage includes receiving a request to change an initial portion of data, the initial portion of data (i) associated with an initial redundant region and (ii) including a first segment to be changed and a set of other segments not to be changed; updating the first segment in response to the request; and generating an updated redundant region based on a computation involving the initial redundant region and the first segment but not involving the set of other segments.

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

Abstract: A circuit and method for verifying the operation of error checking circuitry. In one example, a circuit includes a memory, a first error checking circuit, a second error checking circuit, and a comparison circuit. The memory includes a data output. The first error checking circuit includes an input and an output. The input of the first error checking circuit is coupled to the data output of the memory. The second error checking circuit includes an input and an output. The input of the second error checking circuit is coupled to the data output of the memory. The comparison circuit includes a first input and a second input. The first input is coupled to the output of the first error checking circuit. The second input is coupled to the output of the second error checking circuit.

Abstract: A data storage device is disclosed comprising a head actuated over a disk. A first plurality of codewords and corresponding parity sector are generated, and a second plurality of codewords and corresponding parity sector are generated. The first and second plurality of codewords are written to the disk, and during a read of the first and second set of codewords, M codeword locations within the data track that are unrecoverable are saved, and N codeword locations out of the M codeword locations are selected based on a quality metric of the read. The N codewords are reread from the data track at the N codeword locations and reliability metrics associated with the N codewords are saved. The saved reliability metrics are updated using at least one of the first parity sector or the second parity sector.

Abstract: Parity logic is widely used in forward error correction codes and error detection codes. When used for error correction and error detection applications, the role of parity bits is to increase code distance by introducing memory between encoded bits and input bits at cost of overhead bits. Present disclosure provide systems and methods for implementing invertible parity functions using parity logic wherein ‘k’ input bits are received and encoded using a first invertible parity function. The ‘k’ input bits can be iteratively encoded to obtain nonlinearity and higher dependency between set of encoded parity bits and the ‘k’ input bits or other data bits. Further the decoding is performed on the set of encoded bits to retrieve original ‘k’ input bits using a second invertible parity function.

Abstract: This application provides an encoding method. The method includes: determining a frame of an outer code of to-be-encoded data, where the frame of the outer code includes a data information code and a check code of the data information code, the frame of the outer code is divided into Q data blocks, each data block in the Q data blocks includes W bits, and W and Q are integers greater than 0; and encoding the Q data blocks to obtain Q codewords of an inner code, where the Q data blocks are in a one-to-one correspondence with the Q codewords of the inner code, a first codeword in the Q codewords of the inner code includes a first data block and a check code of the first data block, the first codeword is any codeword in the Q codewords of the inner code.

Abstract: An optical communication system includes a first communication device configured to transmit optical signals, and a second communication device configured to receive the optical signals. The first transmission device includes encoding circuit that configured to assign, to a plurality of bit strings, symbols each corresponding to a value of every one of the plurality of bit strings, the symbols being among a plurality of symbols in a constellation of a multi-level modulation scheme, convert values of bit strings, generate the second error correction code from a second bit string among the plurality of bit strings in every one of a plurality of periods, delay the first error correction code, and delay the second error correction code, wherein the encoding circuit uses the delayed first error correction code and the delayed second error correction code to convert a value of the second bit string.

Abstract: A network node and a user device are provided. The network node comprises a processor to determine for each of the plurality of user devices a corresponding check element position of a corresponding check element in a control information message addressed to the user device; a transmitter to transmit a first control signal (CS1) to each of the plurality of user devices, the CS1 indicating the determined corresponding check element position. The user device comprising: a receiver to receive a CS1 indicating a corresponding check element position of a check element associated with the user device in a control information message (M), the control information message (M) comprising control information (d) and at least two check elements, a processor to derive the corresponding check element position of the check element associated with the user device from the CS1.

Abstract: A data processing method and apparatus. The data process method includes: determining, by a transmitting node, a code block length N0 for encoding an information bit sequence to be transmitted according to a data characteristic for representing the information bit sequence to be transmitted and a preset parameter corresponding to the data characteristic; performing, by the transmitting node, polar encoding on the information bit sequence to be transmitted according to the code block length N0; and transmitting, by the transmitting node, a code block obtained through the polar encoding to a receiving node.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.