Abstract: An ARQ transmission method in a communication system, wherein data packets comprising modulation symbols are transmitted based on an automatic repeat request and subsequently combined with previously received data packets. The symbols of the transmitted data packets are modulated in a mapping entity employing at least a first and second signal constellation. The method further comprises the step of obtaining the second signal constellation from the first signal constellation by exchanging a logical bit position and/or inverting a logical bit. The invention further relates to a corresponding transmitter and receiver.

Abstract: Method and system for incdicating that at least one C2 codeword or C1 codeword of a CD data block has an uncorrectable number of errors, by marking or flagging the corrupted symbols of a codeword with defect signals. When a C1 codeword (or C2 codeword) of the data block is found to contain more than a threshold number of errors, a selected number w of distinguishable symbol values (DSVs) is associated with at least one C1 codeword (or with at least one C2 codeword) of the block. When the block is further processed and the presence of more than a threshold number of DSVs is sensed, the system interprets this occurrence as indicating that an uncorrectable group of errors has occurred in a C1 codeword and/or in a C2 codeword of the block.

Abstract: Error bursts are detected and corrected in a communication system using shortened cyclic codes, such as shortened Fire codes. Data is loaded into a first error syndrome register and a second error syndrome register. The data in the registers may be evaluated to determine if the data bits contain a correctable error. Shortened zero bits are shifted into the second error syndrome register. A number of zero bits are shifted into the first error syndrome register to trap an error burst pattern in the data. A determination is made as to the number of zero bits shifted into the second error syndrome register to trap the location of the error burst in the data. Using the number of zero bits shifted into the second error syndrome register and the error burst pattern, the error in the data is located and corrected.

Abstract: An optical disk apparatus reads data written in an optical disk in units of code blocks arranged by joining a plurality of correcting codes. The optical disk apparatus includes a reading unit for reading the code block from the optical disk and an error correcting unit for combining first error correcting processing performed on the code block read by the reading unit with second error correcting processing performed by adding remove information to codes that cannot be corrected during at least the first error correcting processing.

Abstract: A method is provided that verifies whether K original packets have been correctly reconstructed, and if not, locates an erroneously marked packet so that it may be removed from the reconstruction process. The reconstruction, verification and location process may then be repeated, if there are enough remaining packets, until the reconstructed original packets are deemed correct.

Abstract: A data encoding apparatus is provided wherein, in one aspect, bit data are encoded by using at least one kind of error-correcting code out of two kinds of error-correcting modes—random error-correcting code mode and burst error correcting code mode. The encoded bit data are then arranged in a specific two-dimensional region in a matrix to form a two-dimensional image, which is then printed on a medium. The encoded bit data may be relocated in accord with a relocation map.

Abstract: A method for interleaving data in packet based communications includes interleaving elements of data in a source sequence to form an interleaved sequence and transmitting the interleaved sequence of the elements of the data. Adjacent elements of data in the interleaved sequence originally were separated by a first number of elements of data in the source sequence. Additionally, originally adjacent elements of data in the source sequence are separated by at least a second number of elements of data in the interleaved sequence.

Abstract: A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.

Abstract: The present invention provides an encoding apparatus, comprising means (21) for generating a checksum for incoming data, means (22) for constructing frames on the basis of said incoming data and said generated checksum, and means (23) for multidimensionally coding said frames. Further, the present invention comprises a decoding apparatus for iterative decoding of multidimensionally decoded information, comprising means (28) for performing at least one decoding iteration on multidimensionally coded information, and means (32) for checking the decoded information after each decoding iteration and for causing said decoding iteration means (28) to perform a further decoding iteration on the basis of a checking result. The present invention further comprises the corresponding encoding method and decoding method. The average processing delay and the computational complexity is significantly reduced, since only the required number of iteration steps is adaptively performed in the decoding apparatus.

Abstract: Data are simultaneously written to plural tracks of a magnetic tape storage device while preventing elongated tape scratches from corrupting data blocks. A byte stream of user data is arranged into plural codewords that are distributed amongst plural heads that write the codewords to the plural tracks. When the data are read from the plural tracks, data are verified as being written to the tape successfully. If not, codewords are distributed amongst the plural read/write heads in a different order and re-written data to the tape.

Abstract: An interleaving method for a high density recording medium and an interleaving circuit therefor. In this circuit, an intrablock interleaver interleaves received data having a predetermined error correction code within an error correction block to output intrablock-interleaved data. An interblock interleaver interleaves the intrablock-interleaved data between the error correction blocks in units of a predetermined number of the error correction blocks to output interblock-interleaved data. Accordingly, the capability of correcting a burst error due to a scratch on a disc is improved while maintaining compatibility with a general DVD format in an error correction format. Also, each row having position information is not interleaved while interblock interleaving is performed, so that a similar access time to the access time in a DVD is achieved. Therefore, high-speed searching is possible.

Abstract: A method for generating correction codes that can correct a single error and detect two adjacent errors in an information word for a range of (n, k) values, where k denotes the length of the information word in bits and n denotes the length of the coded information word in bits. The method generates a parity check matrix, then multiplies a received word by the parity check matrix to produce a syndrome corresponding to one of two mutually exclusive sets of syndromes if the word contains at least one error. Information in the word is corrected by inverting a bit containing an error if the produced syndrome corresponds to one of the sets of syndromes. An uncorrectable two bit adjacent error is reported if the produced syndrome corresponds to the other of the two sets of syndromes and no error is reported if the produced syndrome contains all zeros.

Abstract: A system for memory word error correction that enables correction of burst errors in memory words. The system is based on an adaptation of two-error correction BCH code which yields burst error correction without increasing the number of error correction bits in the memory words over prior two-error BCH code error correction schemes. The adaptation of two-error correction BCH code when combined with additional techniques for detecting columns of burst errors enables the correction of burst errors and additional random bit errors in memory words.

Abstract: An error correction and detection technique provides a correction code for correcting single bit errors as well as detecting but not correcting two adjacent bits in error. A received word, which may contain errors, is multiplied by a parity check matrix to produce a syndrome corresponding to one of first and second mutually exclusive sets of syndromes if the received word contains at least one error, each single bit error in the received bit word corresponding one-to-one with a member of the first of the sets of syndromes and each two bit adjacent error corresponding non-uniquely to a member of the second of the sets of syndromes. A syndrome containing all zeros is produced if the received word contains no errors. One bit data errors in the received word are corrected, two bit errors are reported, and no action is taken if the word contains no errors.

Abstract: Disclosed herein is a disk drive in which servo-sector addresses are reproduced from a disk, a target data sector to be accessed is specified, and data is read from or written in the target data sector. The servo-sector addresses are recorded on the disk and randomized in accordance with a specific translation rule, thus arranged in an order different from the order they should be arranged in the same cylinder. The disk drive has a read head and a CPU. The head reads the randomized servo-sector addresses from the disk. The CPU refers to a back translation table, translating the servo-sector addresses back to the original servo-sector addresses. The CPU then checks the continuity of each servo-sector address with respect to the adjacent ones. If the servo-sector address has have no continuity, the CPU determines that the servo-sector address has an error.

Abstract: The present invention provides a system and method for the time-varying randomization of a signal stream to provide for a robust error recovery. A current block of data is randomized in accordance with data from the current block and data from at least one temporally adjacent block of data. The present invention also provides a system and method for time-varying derandomization of a randomized signal stream and alternately delayed-decoding of the signal stream. Randomized data is derandomized using the current block of data and data from at least one temporally adjacent block. In addition, decoding of the current block and the adjacent block is delayed in order to facilitate recovery of lost or damaged compression parameters of encoded data.

Abstract: A method is provided that verifies whether K original packets have been correctly reconstructed, and if not, locates an erroneously marked packet so that it may be removed from the reconstruction process. The reconstruction, verification and location process may then be repeated, if there are enough remaining packets, until the reconstructed original packets are deemed correct.

Abstract: In a digital communication system, a method is provided for recognizing and acting upon differences in information field characteristics when transmission errors are detected. Information having more than one field protected by a channel code is received and decoded according to the channel code. Based on the outcome of the decoding, fields of the information into which transmission errors fall are identified. These are called flawed fields. A characteristic of a flawed field is determined. The information is then processed according to the characteristic. In one embodiment of the invention, the syndrome of an incoming packet is computed. When the syndrome is all-zero, the packet is passed up a communication protocol stack conventionally. When the syndrome is not all-zero, the coset leader associated with the syndrome is found, and used to determine which fields of the packet are most likely flawed.

Abstract: Multiword information is based on multibit symbols disposed in relative contiguity with respect to a medium, and is encoded with a wordwise interleaving and wordwise error protection code for providing error locative clues across multiword groups. In particular, the clues originate in high protectivity clue words (BIS) that are interleaved among clue columns, and also in synchronizing columns constituted from synchronizing bit groups. The synchronizing columns are located where the clue columns are relatively scarcer disposed. The clues are directed to low protectivity target words (LDS) that are interleaved in a substantially uniform manner among target columns which form uniform-sized column groups between periodic arrangements of clue columns and synchronizing columns.

Abstract: A method is provided that verifies whether K original packets have been correctly reconstructed, and if not, locates an erroneously marked packet so that it may be removed from the reconstruction process. The reconstruction, verification and location process may then be repeated, if there are enough remaining packets, until the reconstructed original packets are deemed correct.

Abstract: A novel and improved method and apparatus for address generation in an interleaver is provided. In accordance with one embodiment of the invention, an address is generated using a random address fragment and a bit reversed address fragment. The bit reversed address fragment is selected by first generating two consecutive candidate bit reversed fragments. The second bit reversed address fragment is selected when the first bit reversed address fragment generates an address that is greater than a maximum address. The address generator allows address generation for interleaver and deinterleaver frame sizes of N, where N is not an integer power of two, without any cycle penalty.

Abstract: A method for error correction coding (ECC) by using shuffling of a digital data supplied as a bit stream in a digital-video home system. Three methods are suggested for error correction coding/decoding. One method is where an outer ECC process for 18 ECC blocks is performed earlier than an inner ECC process for the 18 ECC blocks. Another method is where an outer ECC process and an inner ECC process for an ECC block are carried out sequentially and implemented in order for 18 ECC blocks. These two methods employ a predetermined shuffling algorithm. The third method is where an outer ECC process is firstly performed for 18 ECC blocks by using the shuffling algorithm, and then an inner ECC process is implemented by the sync block according to a recording order on tracks. The outer parity information is produced by processing the data from the shuffled sync block.

Abstract: An apparatus for encoding digital data for storage on a data storage medium includes a non-deterministic randomizer code generator. The randomizer code generator may select different randomizer codes for different portions of the data to be stored. The randomizer code used to randomize a given portion of the data may be stored on the media for use in subsequent data retrieval.

Abstract: There is provided an apparatus for processing data for generating an error correction product code block devised so as to maintain the current level of redundancy after the error correcting ability is modified as a result of advancement of semiconductor and data recording/transmission technologies. Unlike any known technique of configuring a Reed-Solomon error correcting product code block of (M+P0)×(N+PI) bytes for an information data of (M×N) bytes, an error correcting product code block data structure is obtained by configuring a (K×(M+1)×(N+P))-byte Reed-Solomon error correcting product code block for (K×M×N)-byte data, making K variable to consequently make the entire size of the Reed-Solomon error correcting product code block variable. At the same time, the error correcting ability varies in proportion to the value of K without increasing redundancy.

Abstract: Data is encoded to maximize subsequent recovery of lost or damaged compression constants of encoded data. In one embodiment, a compression constant is used to define a randomization pattern and the data is randomized using the randomization pattern. In one embodiment, a bit reallocation process and code reallocation process are performed on the data to randomize the data.

Abstract: A first error corrector performs error detection and error correction using inner codes on data subjected to an error correction coding processing with multiplication codes and a second error corrector performs error detection and error correction using outer codes on the data. A condition discriminator discriminates whether or not the data satisfies predetermined conditions, and a controller responds to the discriminator to prevent error detection and error correction using outer codes. Consequently, power for error detection and error correction is consumed only when sufficiently reliable data can be obtained by error detection and error correction using inner codes.

Abstract: The present invention relates to a small size decoder reducing power consumption and more particularly to a series reed-Solomon decoder synchronized with a bit clock signal. In a Reed-Solomon decoder according to the present invention, the syndrome calculation part comprises a classification element for classifying the input coding data into an even data and an odd data and for calculating, in series, coefficient of the syndrome polynomial on bit-by-bit basis, being synchronized with a bit clock signal. The error position and estimation polynomial calculation part comprises a classification element for classifying an initial syndrome polynomial, a correction syndrome polynomial, an initial deletion pointer polynomial and an initial deletion pointer polynomial into an even data and an odd data and for an error value polynomial and an error position value polynomial on bit-by-bit basis, being synchronized with a bit clock signal.

Abstract: A coding and decoding system which uses CRC check bits is disclosed. When a coding apparatus performs coding, symbol interleaving is performed after coding by an outer code of a concatenated code, and coding by an inner code is performed after CRC check bits are added. Then, upon decoding by a decoding apparatus, error detection using the CRC check bits is performed after decoding of the inner code. After symbol deinterleaving is performed, decoding of the outer code by erasure decoding or error correction is performed depending upon the number of symbols included in a frame in which an error has been detected.

Abstract: Apparatus and methods for storing predefined information with error correcting code (ECC) in a direct access storage device are provided. Predetermined information is identified and loaded to an ECC generator for customer data to be read and written. The identified predetermined information includes an address for customer data to be read and written. The customer data is written and loaded in parallel to the ECC generator. Then the generated ECC that reflects the pre-loaded predetermined information is written at the end of the written customer data. The customer data and ECC is read and loaded in parallel to the ECC generator. Errors in the predetermined information that is not written to the disk surface, can be detected from the read ECC.

Abstract: In a hard disk drive, a two-level pipelined method of processing data errors which minimizes disk re-reads. In the first level, a sector is read and a syndrome is generated based on the ECC bits appended for that sector. If there are no errors, the next sector is read. However, if an error is detected, a flag is checked. If the flag is currently set, the disk drive is prevented from reading the next sector. If the flag is not set, the disk drive is allowed to proceed with reading the next sector; the syndrome is stored in a register; and hardware error correction is performed. If the error is corrected by the hardware circuit, the process repeats by reading the next sector. But if the hardware circuit cannot correct the error, a second level firmware error correction is eventually initiated for handling the error. The flag is set in order to prevent a subsequent syndrome from overwriting the syndrome currently in the register.

Abstract: An error correcting apparatus and method of a digital processing system. The error correcting apparatus of the digital processing system includes a demodulator for demodulating channel data to source data and generating an error flag when an error occurs during demodulation, a synchronous detector for receiving the error flag and demodulation data generated from the demodulator and detecting a synchronizing signal to distinguish data by a unit of code which can correct an error, a first decoder for decoding the demodulation data and the error flag by a unit of row by the synchronizing signal to correct an error and an erasure, and a second decoder for decoding the demodulation data and the error flag by a unit of column by the synchronizing signal to correct an error and an erasure.

Abstract: A method and system are provided for transferring data from a host computer to one or more subscriber computers, the data consisting of k original packets. The method includes the steps of encoding the k original packets to form n encoded packets, where n>k, transmitting the encoded packets from the host computer to the subscriber computers, receiving some of the transmitted packets, and decoding any combination of k correctly-received encoded packets to reconstruct the k original packets.

Abstract: An error correction arrangement that contains a Viterbi decoder and an RS decoder to provide inner and outer code decoding, respectively. A score keeper is arranged at the output of the Viterbi decoder to form a score for a decoded byte to indicate the number of error bits in the byte. A tie breaker is provided to compare the score with a preset threshold level. If the score is higher than the threshold level, the corresponding error byte is replaced with an erasure supplied to the RS decoder.

Abstract: A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A CPU is coupled to the processor bus. A memory sub-system is coupled to the processor bus and includes memory check bits, memory address bits, and memory data bits, and an error detection and correction device for detecting an error in the memory address bits using the memory check bits and for detecting an error in the memory data bits using the memory check bits. The CPU can include a processor from the Pentium.RTM. Pro family of processors. The error detection and correction device generates a syndrome table which includes a plurality of entries mapped to correctable or uncorrectable errors, in which a detected multiple-bit error in the memory data bits is mapped to an uncorrectable error entry and a detected error in the memory address bits is mapped to an uncorrectable error entry.

Abstract: The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.

Abstract: An optical disk having a diameter less than 140 mm and, a thickness of 1.2 mm±0.1 mm, with a plurality of record tracks having data recorded thereon as embossed pits representing information and exhibiting a track pitch in the range between 0.646 &mgr;m and 1.05 &mgr;m; with the tracks being divided into a lead-in area, a program area and a lead-out area. The data includes table of contents (TOC) information recorded in a plurality of sectors in at least one TOC track and user information recorded in a plurality of sectors in user tracks; with the TOC information including addresses of start sectors recorded in the user tracks. The data (both user and TOC information) is encoded in a long distance error correction code having at least eight parity symbols, and is run length limited (RLL) modulated.