Dynamic Data Storage Patents (Class 714/769)
  • Patent number: 8959417
    Abstract: A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: February 17, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Jun Zhu, Joseph Jun Cao, Sheng Lu, Pantas Sutardja
  • Patent number: 8954819
    Abstract: Aspects of the disclosure provide a circuit that includes a decoder, an error checking module, and a controller. The decoder is configured to receive codewords, and decode the codewords based on an error correcting code. The error checking module is configured to error-check sectors using an error detecting code in the sectors. Each sector is formed of a plurality of decoded codewords. The controller is configured to store in a memory, when the error checking fails for at least one sector, the decoded codewords and corresponding flags indicative of pass or fail of the decoding of the codewords.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 10, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Mats Oberg, Jin Xie
  • Patent number: 8949312
    Abstract: An embodiment generally relates to a method of updating clients from a server. The method includes maintaining a master copy of a software on a server and capturing changes to the master copy of the software on an update disk image, where the changes are contained in at least one chunk. The method also includes merging the update disk image with one of two client disk images of the client copy of the software.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: February 3, 2015
    Assignee: Red Hat, Inc.
    Inventors: Mark McLoughlin, William Nottingham, Timothy Burke
  • Patent number: 8949693
    Abstract: Examples of the present invention include an electronic-memory-system component. The electronic-memory-system component includes an array of data-storage elements and an encoder that receives input data, processes the input data as a two-dimensional array of bits by carrying out two passes, in one pass subjecting a portion of each row of the two-dimensional array of bits having more than a threshold weight to a first weight-reduction operation, and, in another pass, subjecting a portion of each considered column of the two-dimensional array of bits having more than a threshold weight to a second weight-reduction operation, one of the first and second weight-reduction operations employing an antipodal mapping and the other of the first and second weight-reduction operations employing bit inversion, generates a codeword corresponding to the input data, and stores the codeword in the array of data-storage elements.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: February 3, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Erik Ordentlich, Ron M. Roth
  • Patent number: 8938658
    Abstract: Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: January 20, 2015
    Assignee: Sandisk Enterprise IP LLC
    Inventors: Ying Yu Tai, Yueh Yale Ma
  • Patent number: 8938552
    Abstract: A method begins by a processing module detecting a potential dispersed storage network (DSN) protocol issue that effects access of dispersed storage error encoded data within a DSN. The method continues with the processing module identifying a DSN entity based on the DSN protocol issue and generating a DSN protocol inquiry frame. The method continues with the processing module transmitting the DSN protocol inquiry frame to the DSN entity. The method continues with the processing module receiving a DSN protocol response frame from the DSN entity and resolving the DSN protocol issue based on the DSN protocol response frame.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: January 20, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Andrew Baptist, Wesley Leggette, Jason K. Resch
  • Publication number: 20150019937
    Abstract: A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated.
    Type: Application
    Filed: June 30, 2014
    Publication date: January 15, 2015
    Inventors: Don BAKER, Paul R.M. CARPENTIER, Andrew KLAGER, Aaron PIERCE, Jonathan RING, Russell TURPIN, David YOAKLEY
  • Publication number: 20150012800
    Abstract: A data processing system is disclosed including a data detector, a data decoder and an alignment detector. The data detector is operable to apply a data detection algorithm to generate detected values for a data sector. The data decoder is operable to apply a data decode algorithm to a decoder input derived from the detected values to yield decoded values. The alignment detector is operable to calculate an offset between multiple versions of the data sector by correlating the multiple versions.
    Type: Application
    Filed: July 26, 2013
    Publication date: January 8, 2015
    Applicant: LSI Corporation
    Inventors: Shaohua Yang, George Mathew, Jefferson E. Singleton, Jongseung Park, Richard Rauschmayer
  • Patent number: 8930780
    Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 6, 2015
    Assignee: LSI Corporation
    Inventors: Shaohua Yang, Bruce A. Wilson
  • Patent number: 8930779
    Abstract: The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: January 6, 2015
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern, Thomas Vogelsang
  • Publication number: 20150006997
    Abstract: A method includes destructively reading bits of a spin torque magnetic random access memory and immediately writing back the original or inverted values. A detection of the majority state of the write back bits and a conditional inversion of write back bits are employed to reduce the number of write back pulses. A subsequent write command received within a specified time or before an original write operation is commenced will cause a portion of the write back pulses or the original write operation pulses to abort. Write pulses during subsequent write operations will follow the conditional inversion determined for the write back bits during destructive read.
    Type: Application
    Filed: August 5, 2014
    Publication date: January 1, 2015
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Syed M. Alam, Thomas Andre, Matthew R. Croft, Chitra Subramanian, Halbert Lin
  • Patent number: 8902530
    Abstract: A set of decisions is determined based at last in part on a set of samples. For a given sample in the set of samples, a low frequency noise estimate is estimated based at least in part on (1) at least some samples from the set of samples and (2) at least some decisions from the set of decisions. A reduced noise sample is generated by removing the low frequency noise estimate from the given sample.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 2, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Zheng Wu, Jason Bellorado, Naveen Kumar, Marcus Marrow
  • Patent number: 8898548
    Abstract: A data storage device may comprise an array of flash memory devices and a controller coupled thereto, configured to program and read data from the array responsive to received data access commands. The array may comprise a plurality of blocks, each comprising a plurality of flash pages (F-Pages), each of which comprising an integer number of one or more error correcting code pages (E-Pages), at least some of which comprising a data portion and an error correction code (ECC) portion. The controller may be configured to store a plurality of logical pages (L-Pages) in one or more of the plurality of E-Pages, at least some being unaligned with boundaries of the E-Pages; and to adjust, in at least one of the blocks, the size of the ECC portion and correspondingly adjust the size of the data portion of the E-Pages.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: November 25, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rodney N. Mullendore, Radoslav Danilak, Justin Jones, Andrew J. Tomlin
  • Patent number: 8869001
    Abstract: Techniques for optimizing data storage are disclosed herein. In particular, methods and systems for implementing redundancy encoding schemes with data storage systems are described. The redundancy encoding schemes may be scheduled according to system and data characteristics. The schemes may span multiple tiers or layers of a storage system. The schemes may be generated, for example, in accordance with a transaction rate requirement, a data durability requirement or in the context of the age of the stored data. The schemes may be designed to rectify entropy-related effects upon data storage. The schemes may include one or more erasure codes or erasure coding schemes. Additionally, methods and systems for improving and/or accounting for failure correlation of various components of the storage system, including that of storage devices such as hard disk drives, are described.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: October 21, 2014
    Assignee: Amazon Technologies, Inc.
    Inventor: Colin L. Lazier
  • Patent number: 8862962
    Abstract: A system is described for recovering data from a number of sectors, such as the sectors of a hard disk drive (HDD) disk platter, and so forth. The system receives data from the sectors via a read channel and uses a layered data decoder to recover data from the sectors. A memory is coupled with the processor and configured to retain data received from one or more of the sectors, e.g., in retained sector reprocessing (RSR) embodiments. The system is configured to update messages in different circulant layers of the data decoder's parity-check matrix. The system uses one message update order in a processing iteration, and different message update orders in subsequent reprocessing iterations. In some embodiments, layer reordering is used for RSR. In some embodiments, circulant reordering is used for RSR.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: October 14, 2014
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Jun Xiao
  • Patent number: 8856618
    Abstract: A technique for recovering of “squeezed” sectors in a set of sequential sectors such as are used in Shingled Magnetic Recording (SMR) is described. Embodiments of the invention use a programmable erased sector recovery scheme, which is a concatenation of a “Cauchy-type” track erasure correction code, together with a media-error correction code that generates N-weighted parity-sectors per track and is capable of replacing up to N-erased sectors per track in any possible combination.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: October 7, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Kei Akiyama, Sridhar Chatradhi, Jonathan Darrel Coker, Martin Aureliano Hassner, Kirk Hwang, Roger William Wood
  • Patent number: 8850290
    Abstract: Embodiments of the invention relate to calculation of error rate for data storage which includes determining a completion status of a read operation of data stored in a storage device, the completion status being one of at least partially complete or not complete. The fault monitoring count is incremented based on the completion status being not complete. The fault monitoring count is decreased based on the completion status being at least partially complete. The fault monitoring count being decreased according to a value based on the number of bytes successfully read. The error rate indicator value is being calculated based on an exponential decay rate related to the number of bytes read. The fault monitoring count threshold is monitored every time the fault monitoring count is incremented and the storage device is identified as faulty once the threshold limit is exceeded.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventor: D. Scott Guthridge
  • Publication number: 20140281817
    Abstract: A method begins by one or more computing devices obtaining data for storage in a storage as service network environment. The method continues by determining storage preferences regarding the data. The method continues by determining a set of storage units based on the storage preferences and sending a solicitation request to the set of storage units. When at least a minimum number of favorable solicitation responses have been received within a time period, the method continues by determining a dispersed storage error encoding function based on the favorable solicitation responses, the storage preferences, and available encoding schemes. The method continues by encoding the data based on the selected dispersed storage error encoding function to produce a plurality of sets of encoded data slices. The method continues by outputting the sets of encoded data slices to at least some of the storage units providing the favorable solicitation responses.
    Type: Application
    Filed: June 2, 2014
    Publication date: September 18, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Publication number: 20140258812
    Abstract: The technology disclosed herein provides a method of verifying data read from a data block when the cell number of the data block does not match an ECC value stored in the data block. In particular, the method includes designating as unusable a data block in an indexed sequence of data blocks, wherein each data block is associated with a physical index; associating a cell number with a subsequent usable data block following the identified data block in the indexed sequence; and recording in an offset table accessible by an error detection and correction module an offset in association with the cell number of the subsequent usable data block, wherein the combination of the offset and the cell number represents a seed for the error detection and correction module.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Daniel J. Coonen, Abhay T. Kataria
  • Patent number: 8819519
    Abstract: The present invention is related to systems and methods for adaptive parameter modification in a data processing system. As one example, a system is disclosed that includes a filter calibration circuit that is operable to calculate an updated coefficient for a filter circuit using a data set pair including a converged output and a corresponding data set.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 26, 2014
    Assignee: LSI Corporation
    Inventors: Madhusudan Kalluri, Fan Zhang, Bruce Wilson, Johnson Yen
  • Patent number: 8819521
    Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. Such systems and methods may include data pre-processing and detection to identify a media defect.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 26, 2014
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Weijun Tan, Haitao Xia, Shaohua Yang, Xuebin Wu, Wu Chang
  • Patent number: 8799746
    Abstract: A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: August 5, 2014
    Assignee: Caringo, Inc.
    Inventors: Don Baker, Paul R. M. Carpentier, Andrew Klager, Aaron Pierce, Jonathan Ring, Russell Turpin, David Yoakley
  • Patent number: 8788876
    Abstract: The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Publication number: 20140201590
    Abstract: Disk drives are described in which blocks of data spanning multiple sectors are encoded into a plurality of codewords which are then divided into segments that are physically separated (distributed) on the disk surface over multiple sectors in a distributed codeword block so that the codewords have an improved worst case SNR in comparison to individual sectors. This results in more even SNR performance for each codeword, which improves the performance for portions of a track which have lower than the average SNR. Embodiments are described in which the distributed codeword blocks span across tracks.
    Type: Application
    Filed: May 1, 2013
    Publication date: July 17, 2014
    Applicant: HGST Netherlands B.V.
    Inventors: Jonathan Darrel Coker, Richard Leo Galbraith, Weldon Mark Hanson, Travis Roger Oenning, Roger William Wood
  • Publication number: 20140189467
    Abstract: A decoder including a decode module, a matrix module, and a marking module. The decode module receives data and performs a first decoding iteration to decode the data. The first decoding iteration includes generating a first matrix having a first byte. The matrix module generates a second matrix based on the first matrix. The second matrix includes the first and second bytes. The second byte is adjacent and sequentially prior or subsequent to the first byte. The marking module: determines whether the first byte has been correctly decoded; based on determining whether the first byte has been correctly decoded, determines a status of the second byte; and based on the status of the second byte, marks the first byte as an erasure. The decode module, based on the second byte being marked as an erasure, corrects the second byte during the second decoding iteration.
    Type: Application
    Filed: March 10, 2014
    Publication date: July 3, 2014
    Applicant: Marvell World Trade LTD.
    Inventors: Mats Oberg, Jin Xie
  • Publication number: 20140189466
    Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code.
    Type: Application
    Filed: March 7, 2014
    Publication date: July 3, 2014
    Applicant: Rambus Inc.
    Inventors: Ian Shaeffer, Craig E. Hampel
  • Patent number: 8769389
    Abstract: Techniques are described to store and retrieve an encoded info bit stream, and appropriate first and second sets of parity bits to perform interleaving and rate matching, prior to transmission. On the receiver side, a recovery technique is provided which operates on the same principle as that of encoding, but decoding occurs in reverse. In accordance with an exemplary embodiment, three dedicated logical memories are provided for each of the encoded info bit stream and two sets of parity bits, respectively. The proposed solution provides an alternative methodology and/or hardware implementation for performing LTE compliant rate matching and de-rate matching when required to interleave info bits and parity bits.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 1, 2014
    Assignee: Analogies SA
    Inventors: Fotios Gioulekas, Angelos Spanos, Michael Birbas
  • Patent number: 8762814
    Abstract: A method for enhancing error correction capability of a controller of a memory device without need to increase a basic error correction bit count of an Error Correction Code (ECC) engine includes: according to an error correction magnification factor, respectively obtaining a plurality of portions of data, where the portions are partial data to be encoded/decoded; and regarding the portions that are the partial data to be encoded/decoded, respectively performing encoding/decoding corresponding to the error correction magnification factor, in order to generate encoded/decoded data corresponding to a predetermined error correction bit count, where a ratio of the predetermined error correction bit count to the basic error correction bit count is equal to the error correction magnification factor. An associated memory device and the controller thereof are further provided.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: June 24, 2014
    Assignee: Silicon Motion Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 8762798
    Abstract: The subject technology includes adjusting an error correcting code rate in a solid-state drive. A first plurality of memory operations are performed on a flash memory device of the solid-state drive using a first code rate. During operation of the drive, a controller monitors an operating condition associated with one or more memory units of the flash memory device for a trigger event. On the trigger event, the first code rate is adjusted in accordance with the operating condition to produce a second code rate, and a second plurality of memory operations is performed on the flash memory device using the second code rate.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: June 24, 2014
    Assignee: STEC, Inc.
    Inventors: Xinde Hu, Richard D. Barndt
  • Patent number: 8762815
    Abstract: The present invention is related to systems and methods for maintaining additional processing information during extended delay processing.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: June 24, 2014
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Yang Han, Wu Chang, Shaohua Yang
  • Patent number: 8762821
    Abstract: An apparatus is provided that comprises a processor. The processor comprises a cache to store data, a decoder, an error classification module, and an error correction module. The cache stores data, the data encoded as a codeword. The decoder reads the codeword from cache and calculates a syndrome of the codeword using an H-matrix. The error classification module determines an error type of the syndrome. The H-matrix is redesigned such that the columns form a geometrical sequence, and as a result not only t-bit random errors but also (t+1) bit adjacent errors can be corrected. The error correction module, triggered by the enhanced error classification module, takes one of two sets of inputs depending on error type (either random error or adjacent error) and produces corrected data from the syndrome when the syndrome comprises a detectable and correctable error.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 24, 2014
    Assignee: Intel Corporation
    Inventors: Wei Wu, Shih-Lien L. Lu, Muhammad M. Khellah
  • Publication number: 20140173381
    Abstract: A method for reducing the number of error events in a transmitted data stream (34) comprises the steps of (i) generating at least a first most probable sequence (16(1)) and a second most probable sequence (16(2)) with a detection algorithm (12); (ii) determining if a first correctable error occurred in the first most probable sequence (16(1)) with an EDC decoder (14); and (iii) determining if a second correctable error occurred in the second most probable sequence (16(2)) with the EDC decoder (14). Additionally, the steps of determining if a first correctable error occurred and determining if a second correctable error occurred can be performed substantially simultaneously. The method can further comprise computing a plurality of path metrics (42) for the transmitted data stream (34); and selecting a first q smallest path metrics out of the first and second most probable sequences (16(1)), (16(2)) with a Q value selector (44).
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: QUANTUM, INC.
    Inventors: Jaewook Lee, Suayb S. Arslan, Turguy Goker
  • Publication number: 20140164876
    Abstract: A communication system, such as a magnetic recording channel, configured to apply modulation coding to parity bits of a block error-correction code. An embodiment of the communication system may have a transmitter having two different modulation encoders, one configured to apply a first modulation code to information bits and the other configured to apply a second modulation code to the parity bits that have been generated from the information bits using a block error-correction code. Alternatively or in addition, an embodiment of the communication system may have a receiver that incorporates a soft modulation codec configured to use the second modulation code in the log-likelihood-ratio space to enable decoding iterations between a sequence detector and a parity-check decoder.
    Type: Application
    Filed: July 18, 2013
    Publication date: June 12, 2014
    Inventors: Elyar Eldarovich Gasanov, Pavel Anatolyevich Panteleev, Yurii Sergeevich Shutkin, Andrey Pavlovich Sokolov, Ilya Vladimirovich Neznanov
  • Patent number: 8751906
    Abstract: Systems and methods for adaptively operating a storage device are provided. A level of integrity of storing data in the storage device is determined. A coding scheme is selected based on the determined level of integrity of the storage device. An operation is performed on the storage device using the selected coding scheme.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: June 10, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Engling Yeo, Zining Wu
  • Patent number: 8751905
    Abstract: A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: June 10, 2014
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie
  • Patent number: 8745464
    Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Ramesh Subashchandrabose, Tessil Thomas, Sambaran Mitra, Debaleena Das, Kai Cheng
  • Patent number: 8739007
    Abstract: A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: May 27, 2014
    Assignee: Apple Inc.
    Inventor: Micha Anholt
  • Publication number: 20140139943
    Abstract: Read channel circuitry comprises a decoder and error correction circuitry. The error correction circuitry is configured to calibrate a first set of filters using a read channel data signal, to determine first hard decision information regarding the read channel data signal using the calibrated first set of filters, to determine an error corrected read channel data signal using the first hard decision information, to calibrate a second set of filters using the error corrected read channel data signal, to determine second hard decision information regarding the error corrected read channel data signal using the calibrated second set of filters, and to decode the second hard decision information. The first set of filters and the second set of filters are calibrated in respective first and second calibrators.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicant: LSI Corporation
    Inventors: Weijun Tan, Shaohua Yang
  • Patent number: 8732555
    Abstract: The disclosure is related to an apparatus and methods for addressing variations in bit error rates amongst data storage segments. In a particular embodiment, an apparatus includes a controller that detects variations in bit error rates amongst different segments of a plurality of segments in a storage medium. The controller also adjusts a read/write operation parameter according to the detected variations amongst the bit error rates in the plurality of segments.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: May 20, 2014
    Assignee: Seagate Technology LLC
    Inventors: Clifford Jayson Bringas Camalig, Mui Chong Chai
  • Patent number: 8726120
    Abstract: A method begins with a processing module receiving an access request for the data object. The method continues by ascertaining that the data object is divided into a plurality of data segments and that plurality of data segments are dispersed storage error encoded to produce a plurality of sets of encoded data slices. The method continues by ascertaining batching of the plurality of sets of encoded data slices, wherein the plurality of sets of encoded data slices are arranged into a set of batched encoded data slices. The method continues by outputting a set of access requests for the set of batched encoded data slices to storage units of the DSN.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: May 13, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Andrew Baptist, Ilya Volvovski, Wesley Leggette, Greg Dhuse, Jason K. Resch
  • Patent number: 8726127
    Abstract: A method begins by a computing device determining that dispersed storage network (DSN) memory is to be accessed regarding data. The method continues when the computing device is paired with a DSN access token module with the DSN access token module retrieving a plurality of sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with at least one of the computing device and the DSN access token module decoding the plurality of sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function and executing, by one or more of the computing device and the DSN access token module, the DS error coding function to access the DSN memory regarding the data.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 13, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison, Greg Dhuse, Jason K. Resch, Ilya Volvovski, Wesley Leggette
  • Publication number: 20140129905
    Abstract: Various embodiments of the present inventions provide systems and methods for data processing with a flexible LDPC seed.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: LSI CORPORATION
    Inventors: Lei Chen, Shaohua Yang, Johnson Yen
  • Patent number: 8719647
    Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to read performance of phase change memory. During a reading process, a bias condition can be applied to a memory cell to determine the memory cell's state. The determined state of the memory cell can depend on a threshold voltage of the memory cell. The threshold voltage of the memory cell may shift over time. The shift in threshold voltage may result in read errors. The applied bias condition may be modified based on the resulting read errors.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Ferdinando Bedeschi
  • Patent number: 8719666
    Abstract: A method of extraction of a key from a physical unclonable function using the states of cells of a volatile memory after a powering on, wherein: cells are read according to addresses stored in a non-volatile memory; an error-correction code corrects the read states; and, in case an error has been corrected, the address of the cell providing an erroneous state is replaced in the non-volatile memory with that of another cell providing the non-erroneous state.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: May 6, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Fabrice Marinet
  • Publication number: 20140115425
    Abstract: The disclosure is related to an apparatus and methods for addressing variations in bit error rates amongst data storage segments. In a particular embodiment, an apparatus includes a controller that detects variations in bit error rates amongst different segments of a plurality of segments in a storage medium. The controller also adjusts a read/write operation parameter according to the detected variations amongst the bit error rates in the plurality of segments.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: Seagate Technology LLC
    Inventors: Clifford Jayson Bringas Camalig, Mui Chong Chai
  • Patent number: 8707123
    Abstract: In one embodiment a variable barrel shifter includes a shifter operable to apply a cyclic shift to each of a number of portions of a data word, a pivot circuit operable to swap sections of the data word around at least one pivot point in the data word, a first multiplexer operable to select between an input of the variable barrel shifter or an output of the pivot circuit as an input to the shifter, a second multiplexer operable to select between the input of the variable barrel shifter or an output of the shifter as an input to the pivot circuit, and a third multiplexer operable to select between the output of the shifter or the output of the pivot circuit as an output to the variable barrel shifter.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: April 22, 2014
    Assignee: LSI Corporation
    Inventors: Dan Liu, Qi Zuo, Yong Wang, Yang Han, Shaohua Yang
  • Publication number: 20140108890
    Abstract: A method begins by a processing module forward error correction (FEC) encoding data to produce FEC encoded data and dividing the FEC encoded data into a set of FEC encoded words. The method continues with the processing module generating integrity information based on the data and generating a word name for an FEC encoded word of the set of FEC encoded words. The method continues with the processing module affiliating an address of allocated address space of a dispersed storage memory with the word name and storing the integrity information, the word name, and the address. The method continues with the processing module creating a write command to store the FEC encoded word at the address in the dispersed storage memory.
    Type: Application
    Filed: December 16, 2013
    Publication date: April 17, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8694862
    Abstract: A data processing apparatus is provided having error code generation circuitry configured to generate an error code associated with a received data value, such that a bit change in the received data value can be known about by reference to the error code. Stored data values are stored in a data store and associated error codes are stored in an error code store. Error checking circuitry performs a verification operation on a stored data value and an associated error code to determine if an error has occurred in at least one of the stored data value and the associated error code during storage. The received data value comprises at least one additional bit with respect to the stored data value and the error checking circuitry is configured to reconstruct the at least one additional bit by reference to the stored data value and the associated error code.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: April 8, 2014
    Assignee: ARM Limited
    Inventors: Yiannakis Sazeides, Emre Özer, Daniel Kershaw, Jean-Baptiste Brelot
  • Patent number: 8694841
    Abstract: A method to enable defect margining of a disk drive may comprise executing a data access command on a target sector on the disk drive. Upon encountering a data access error at the target sector, an address of the target sector may be added to an error list. The address of the target sector in the error list may then be converted to a physical location on the disk drive. A thermal asperity scan may be performed at and around the physical location and, upon detecting a thermal asperity, and at least sectors around the detected thermal asperity may be margined, and the data stored within the margined sectors may be relocated. Instead of sectors, entire tracks may be margined and the data stored therein relocated to a spare or reserve location, one track at a time.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 8, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Heon Ho Chung, Chun Sei Tsai, Carl E. Barlow, Kenneth J. Smith
  • Patent number: 8694864
    Abstract: Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of an array. The cyclic redundancy check error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry uses parallel processing to continuously monitor the data to identify the row and column location of each error.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 8, 2014
    Assignee: Altera Corporation
    Inventor: Ninh D. Ngo