Dynamic Data Storage Patents (Class 714/769)
  • Publication number: 20140095961
    Abstract: A system is described for recovering data from a number of sectors, such as the sectors of a hard disk drive (HDD) disk platter, and so forth. The system receives data from the sectors via a read channel and uses a layered data decoder to recover data from the sectors. A memory is coupled with the processor and configured to retain data received from one or more of the sectors, e.g., in retained sector reprocessing (RSR) embodiments. The system is configured to update messages in different circulant layers of the data decoder's parity-check matrix. The system uses one message update order in a processing iteration, and different message update orders in subsequent reprocessing iterations. In some embodiments, layer reordering is used for RSR. In some embodiments, circulant reordering is used for RSR.
    Type: Application
    Filed: October 3, 2012
    Publication date: April 3, 2014
    Applicant: LSI Corporation
    Inventors: Fan Zhang, Jun Xiao
  • Patent number: 8689062
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, and a reliability monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output that includes soft data. The reliability monitor circuit is operable to determine a proxy error count based at least in part on the soft data, and to modify a parameter governing an operation of the data processing system based at least in part on the proxy error count.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: April 1, 2014
    Assignee: LSI Corporation
    Inventors: Haitao Xia, Shaohua Yang, Kenneth M. Hall, Mark A. Landreth
  • Patent number: 8683297
    Abstract: A method includes generating a replacement default read threshold at least partially based on a default read threshold and on an updated read threshold. The method also includes sending the replacement default read threshold to the memory.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: March 25, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Seungjune Jeon, Steven Cheng
  • Patent number: 8677213
    Abstract: An electronic device comprises an error correction coding device. The error correction coding device comprises a parity code generator. This generator is a circuit for computing a remainder polynomial by dividing a user data polynomial by a generator polynomial and generating a parity code from this remainder polynomial. This generator computes the remainder polynomial by dividing and inputting either a bit string comprising coefficients of the generator polynomial, or a bit string comprising coefficients of the generator polynomial and a bit string comprising coefficients of the generator polynomial, and dividing a minimal unit multiple times based on either a division width of the user polynomial or a division width of the user polynomial and the generator polynomial, and outputs a bit string comprising the coefficient of this remainder polynomial.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: March 18, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Nagamasa Mizushima
  • Patent number: 8661320
    Abstract: A data memory is organized as a logical matrix having multiple virtual data words. Along with the physical representation of the data as being associated with physical memory cells, other virtual data words and their virtual check bits are formed that intersect (logically) with the real data word in a multi-dimensional array. Each of these virtual words can possess errors that can be quickly corrected using independent EDAC methodology. The validity of the virtual word can be used to verify the validity of a single bit in the real word thus correcting multiple bit errors.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: February 25, 2014
    Assignee: Aeroflex Colorado Springs Inc.
    Inventors: Matthew Von Thun, Jonathan Mabra
  • Patent number: 8656251
    Abstract: The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host. Next, upon reading each block from the set of blocks from the storage device, the communication mechanism transfers the block over an interface with the host. The system also includes an error-detection apparatus that performs error detection on the block upon reading the block, and an error-correction apparatus that performs error correction on the block if an error is detected in the block. The communication mechanism may then retransfer the block to the host after the error is removed from the block.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: February 18, 2014
    Assignee: Apple Inc.
    Inventors: Christopher J. Sarcone, David G. Conroy, Jim Keller
  • Patent number: 8654621
    Abstract: A data recovery method includes the following steps. Firstly, plural sampling values are classified into a first group, a second group, a third group and a fourth group. A first channel estimation value and a second channel estimation value are generated according to the sampling values of the second group and the third group. A judging step is performed to judge whether a first sampling value of the first group is lower than the first channel estimation value or a second sampling value of the fourth group is higher than the second channel estimation value. If the judging condition is satisfied, a polarity of the first sampling value or the second sampling value is changed and then the plural sampling values are outputted. If the judging condition is not satisfied, the plural sampling values are directly outputted.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: February 18, 2014
    Assignee: Sunplus Technology Co., Ltd.
    Inventors: Yen-Chien Cheng, Yung-Chi Yang, Zheng-Xiong Chen
  • Patent number: 8645795
    Abstract: The present invention provides a nonvolatile semiconductor memory device that can optimize a timing of performing an error detection and correction process to shorten a processing time. Upon receiving a write request to a memory cell array including a variable resistive element where information is stored based on a resistance state of a variable resistor, an input/output buffer outputs write data to a write control unit and an ECC control unit. The write control unit performs a data write process of writing divided data, obtained by dividing the write data into a predetermined number of data, to the databanks. The ECC control unit generates a first error correction code by performing an error correction code generation process to the write data or the divided data, in parallel with the data write process. The write control unit performs a code write process of writing first test data into an ECC bank.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: February 4, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazuya Ishihara, Yoshiaki Tabuchi
  • Patent number: 8645798
    Abstract: The parallel RS-RAID data storage architecture can aggregate that data and checksums within each cluster into intermediate or partial sums that are transferred or distributed to other clusters. The use of intermediate data symbols, intermediate checksum symbols, cluster configuration information on the assignment of data storage devices to clusters and the operational status of data storage devices, and the like, can reduce the computational burden and latency for the error correction calculations while increasing the scalability and throughput of the parallel RS-RAID distributed data storage architecture.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: February 4, 2014
    Assignee: Marvell World Trade Ltd.
    Inventor: Arvind Pruthi
  • Patent number: 8640007
    Abstract: A test system including a storage device and a protocol analyzer coupled to the storage device. The storage device can include a diagnostic data transmission unit configured to transmit diagnostic data related to an operation of the storage device, and a host interface unit including a first selector configured to receive idle characters and the diagnostic data, wherein the first selector selectively transmits the idle characters or the diagnostic data. The protocol analyzer can be configured to autonomously receive the idle characters or the diagnostic data via the host interface unit.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: January 28, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Martin E. Schulze
  • Patent number: 8631311
    Abstract: A method for recovering data is disclosed. A sensed analog signal is converted into digital samples using an analog-to-digital converter (ADC). The digital samples are processed into processed digital samples using a first filter. The processed digital samples are decoded into decoded data. Whether the decoded data is acceptable is then determined. The processed digital samples are fed back to the first filter using a reprocessing circuit such that the processed digital samples are reprocessed into reprocessed digital samples in the event that the decoded data is unacceptable. A set of reprocessing coefficients is provided for the first filter to reprocess the processed digital samples.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: January 14, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Kai Keung Chan, Yu Kou, Xin-Ning Song, Wing Hui
  • Patent number: 8627179
    Abstract: Reproduction of encoded data which includes a split-mark. FIR data corresponding to split-mark and FIR data affected by the split-mark due to inter-symbol-interference are identified. FIR data corresponding to the split-mark is removed from the received FIR data. Recovered data is created by removing incorrect inter-symbol-interference from the FIR data due to the split-mark, and adding correct inter-symbol-interference from codeword bits. The recovered data is stitched together with data unaffected by split-mark data.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: January 7, 2014
    Assignee: Marvell International Ltd.
    Inventors: Zining Wu, Gregory Burd, Nitin Nangare
  • Patent number: 8627180
    Abstract: Memory controllers having a data buffer coupled to receive and hold data from a memory device, and an Error Correction Code (ECC) generator/checker coupled to the data buffer. The ECC generator/checker is configured to generate ECC codes for the data and to compare the generated ECC codes with ECC codes received with the data. The memory controllers are configured to permit different ECC coverage area sizes and/or different ECC code types for different portions of the memory device.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • Patent number: 8627177
    Abstract: A method begins with a processing module determining a retrieval threshold for retrieving a set of encoded data slices from a dispersed storage network (DSN). The set of encoded data slices represents data encoded using a dispersed storage error encoding function having a number of encoded data slices in the set of encoded data slices equal to or greater than a decode threshold and the retrieval threshold is equal to or greater than the decode threshold. The method continues with the processing module issuing data retrieval requests to the DSN for the set of encoded data slices and receiving encoded data slices of the set of encoded data slices to produce received encoded data slices. The method continues with the processing module decoding the received encoded data slices to recapture the data when a number of received encoded data slices compares favorably to the retrieval threshold.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: January 7, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Greg Dhuse, Ilya Volvovski, Andrew Baptist, Sebastien Vas, Zachary J. Mark
  • Patent number: 8621271
    Abstract: A method begins by a processing module identifying a memory device having an expired useable memory life with respect to a legacy storage protocol. The method continues with the processing module extracting data from the memory device. The method continues with the processing module reprovisioning the memory device from the legacy storage protocol to a dispersed storage error coding storage protocol.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: December 31, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison, Jason K. Resch
  • Patent number: 8601348
    Abstract: Provided are a method, system, and article of manufacture for error checking addressable blocks in storage. Addressable blocks of data are stored in a storage in stripes, wherein each stripe includes a plurality of data blocks for one of the addressable blocks and at least one checksum block including checksum data for the addressable block. A write request is received to modify data in one of the addressable blocks. The write and updating the checksum are performed in the stripe having the modified addressable block. An indication is made to perform an error checking operation on the stripe for the modified addressable block in response to the write request, wherein the error checking operation reads the data blocks and the checksum in the stripe to determine if the checksum data is accurate. An error handling operation is initiated in response to determining that the checksum data is not accurate.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: James L. Hafner, David R. Kahler, Robert A. Kubo, David F. Mannenbach, Karl A. Nielsen, James A. O'Connor, Richard B. Stelmach, Krishnakumar R. Surugucchi
  • Patent number: 8595572
    Abstract: A data storage device may include an interface that is arranged and configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller may be arranged and configured to receive a read metadata command for a specified one of the memory devices from the host using the interface, read metadata from the specified memory device and communicate the metadata to the host using the interface.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: November 26, 2013
    Assignee: Google Inc.
    Inventors: Albert T. Borchers, Andrew T. Swing, Robert S. Sprinkle, Jason W. Klaus
  • Patent number: 8583989
    Abstract: An input/output processing method includes generating and storing at least one address control word (ACW) including a data check word generation field and/or a data check word save field in local channel memory of a channel subsystem, and generating and forwarding to a network interface an address control structure specifying a location in the local channel memory of a corresponding ACW. The method also includes, responsive to a data transfer request, storing the at least one data check word in the data check word save field and routing the data to a host memory location specified by the corresponding ACW responsive to performing a check of the data and determining that the data has not been corrupted, or retrieving the data based on the corresponding ACW, generating and appending at least one data check word and routing the data and the at least one data check word to the interface.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: November 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Clinton E. Bubb, Daniel F. Casper, John R. Flanagan
  • Patent number: 8583991
    Abstract: Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: November 12, 2013
    Assignee: Marvell International Ltd.
    Inventors: Pantas Sutardja, Zining Wu, Toai Doan, Aditya Ramamoorthy
  • Patent number: 8583990
    Abstract: An apparatus and associated method provided for a plurality of storage elements arranged and concurrently accessible in an array. A controller executes programming instructions stored in memory to append an error correction code (ECC) block to a first data block and to store the first data block with appended ECC block in a first storage element of the plurality, the appended ECC block associated with a second data block other than the first data block.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: November 12, 2013
    Assignee: Spectra Logic Corporation
    Inventor: Matthew Thomas Starr
  • Patent number: 8583988
    Abstract: A computer program product for performing input/output (I/O) processing is provided. The computer program product is configured to perform: obtaining information relating to an I/O operation at a channel subsystem; generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data check word generation field and/or a data check word save field; responsive to receiving an input data transfer request including at least one data check word, storing the at least one data check word in the data check word save field and performing a check of the data to determine whether the data has been corrupted; and responsive to receiving an output data transfer, generating at least one data check word based on the data check word generation field and appending the at least one data check word to the data.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: November 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Clinton E. Bubb, Daniel F. Casper, John R. Flanagan
  • Patent number: 8578246
    Abstract: Methods and apparatus are provided for recording input data in q-level cells of solid-state memory (2), where q>2. Input data words are encoded as respective codewords, each having a plurality of symbols. The coding scheme is such that each symbol can take one of q values corresponding to respective predetermined levels of the q-level cells, and each of the possible input data words is encoded as a codeword with a unique sequence of relative symbol values. The symbols of each codeword are then recorded in respective cells of the solid-state memory by setting each cell to the level corresponding to the recorded symbol value. Input data is thus effectively encoded in the relative positions of cell levels, providing resistance to certain effects of drift noise.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Thomas Mittelholzer, Nikolaos Papandreou, Charalampos Pozidis
  • Publication number: 20130290812
    Abstract: A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.
    Type: Application
    Filed: June 25, 2013
    Publication date: October 31, 2013
    Inventor: Thomas Vogelsang
  • Patent number: 8572464
    Abstract: A recording and/or reproducing method, a recording and/or reproducing apparatus, and a computer readable recording medium storing a program for performing the method. A recording unit block in which invalid data is partially padded is written on an information storage medium along with padding information indicating that the invalid data is included in the recording unit block. The padding information is useful in determining whether the recording unit block includes the padding data. Accordingly, unnecessary retrial processes of a drive system are reduced such that the performance of the drive system is improved and error correction capability is enhanced.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: October 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hee Hwang, Jung-wan Ko
  • Patent number: 8566675
    Abstract: Methods and apparatus to facilitate determining or selecting a depth of error detection and/or error correction coverage, and detecting and/or correcting errors in data in accordance with the determined or selected depth of error detection and/or error correction coverage.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: October 22, 2013
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • Patent number: 8555130
    Abstract: A method begins by a processing module receiving a write request that includes a batch of encoded data slices and a corresponding batch of slice names, wherein the batch of encoded data slices includes encoded data slices that have slices names that have a common data object storage name, a common slice storage name, and a different data segment storage name. The method continues with the processing module determining whether a storage file exists based on the common data object storage name. The method continues with the processing module creating the storage file based on the common data object storage name when the storage file does not exist. The method continues with the processing module storing the batch of encoded data slices in the storage file based on the corresponding batch of slice names.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: October 8, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Andrew Baptist, Ilya Volvovski, Wesley Leggette, Greg Dhuse, Jason K. Resch
  • Patent number: 8549380
    Abstract: Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: October 1, 2013
    Assignee: Intel Corporation
    Inventor: Ravi H Motwani
  • Patent number: 8533569
    Abstract: An apparatus, system, and method are disclosed for managing data in a solid-state storage device. A solid-state storage and solid-state controller are included. The solid-state storage controller includes a write data pipeline and a read data pipeline The write data pipeline includes a packetizer and an ECC generator. The packetizer receives a data segment and creates one or more data packets sized for the solid-state storage. The ECC generator generates one or more error-correcting codes (“ECC”) for the data packets received from the packetizer. The read data pipeline includes an ECC correction module, a depacketizer, and an alignment module. The ECC correction module reads a data packet from solid-state storage, determines if a data error exists using corresponding ECC and corrects errors. The depacketizer checks and removes one or more packet headers. The alignment module removes unwanted data, and re-formats the data as data segments of an object.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 10, 2013
    Assignee: Fusion-io, Inc.
    Inventors: David Flynn, Bert Lagerstedt, John Strasser, Jonathan Thatcher, Michael Zappe
  • Patent number: 8527836
    Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: September 3, 2013
    Assignee: Intel Corporation
    Inventors: Ramesh Subashchandrabose, Tessil Thomas, Sambaran Mitra, Debaleena Das, Kai Cheng
  • Patent number: 8522108
    Abstract: A recording medium on which a recording/reproducing unit block is recorded, an apparatus to record and/or reproduce data on/from the recording medium, and a method of recording/reproducing the data on/from the recording medium. The recording/reproducing unit block comprises invalid data used in disc certification, and an identifier to indicate that the invalid data is included in the recording/reproducing unit block, the invalid data being used during the disc certification on a portion of the recording medium or the entire recording medium.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: August 27, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hee Hwang, Jung-wan Ko
  • Patent number: 8516348
    Abstract: Various embodiments of the present invention provide systems and methods for detecting storage medium defects. As one example, a media defect detection system is disclosed that includes a data detector circuit that applies a detection algorithm to the data input and provides a hard output and a soft output. A first circuit combines a first derivative of the hard output with a derivative of the data input to yield a first combined signal. A second circuit combines a second derivative of the hard output with a derivative of the first combined signal to yield a second combined signal. A third circuit combines a derivative of the soft output with the second combined signal and a threshold value to yield a defect signal.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: August 20, 2013
    Assignee: AGERE Systems Inc.
    Inventors: Weijun Tan, Hongwei Song, Shaohua Yang
  • Patent number: 8516341
    Abstract: A method is provided for correcting a write defect in a data storage apparatus comprising a storage medium. The method comprises reading information from a track of the storage medium in which a write defect occurs, calculating a number of error-corrected error correction code symbols in sectors of the track based on the read information, determining a number of sectors on which write defect correction is to be performed by comparing the calculated number of error-corrected error correction code symbols with a threshold, and performing a rewrite operation on the track, beginning at a starting sector determined by the number of sectors on which write defect correction is to be performed.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: August 20, 2013
    Assignee: Seagate Technology International
    Inventors: Kyung-jin Kim, Jae-hyuk Yu
  • Patent number: 8504897
    Abstract: A memory controller carries out error detection on a wide range of area of a memory cell array, which includes not only readout addresses but also non-readout addresses. Thus, by carrying out error detection at an address at which an error occurs without accessing the address for readout, it is possible to detect occurrence of an error at the address. Accordingly, it is possible to prevent a “read disturb phenomenon” in which repetition of access to a readout address for readout may probably cause an error at a non-readout address other than the readout address.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: August 6, 2013
    Assignee: MegaChips Corporation
    Inventors: Masayuki Imagawa, Tetsuo Furuichi
  • Patent number: 8484537
    Abstract: A system including a first buffer module, a first encoder module, a control module, and a second buffer module. The first buffer module receives (i) a first block and (ii) a first logical block address (LBA) for the first block from a host, where the first block includes first data. The first encoder module generates a first checksum based on (i) the first data and (ii) the first LBA. The control module generates a second block, where the second block includes (i) the first data, (ii) the first LBA, and (iii) the first checksum. The second buffer module receives a third block from the first buffer module, where the third block includes a second LBA. The second buffer module determines whether the third block is different than the first block depending on whether the second LBA in the third block is different than the first LBA in the second block.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 9, 2013
    Assignee: Marvell International Ltd.
    Inventors: Tang Heng, Gregory Burd, Soichi Isono, Son Hong Ho, Vincent Wong, Zining Wu
  • Publication number: 20130173995
    Abstract: Aspects of the disclosure provide a circuit that includes a decoder, an error checking module, and a controller. The decoder is configured to receive codewords, and decode the codewords based on an error correcting code. The error checking module is configured to error-check sectors using an error detecting code in the sectors. Each sector is formed of a plurality of decoded codewords. The controller is configured to store in a memory, when the error checking fails for at least one sector, the decoded codewords and corresponding flags indicative of pass or fail of the decoding of the codewords.
    Type: Application
    Filed: December 20, 2012
    Publication date: July 4, 2013
    Applicant: Marvell World Trade Ltd.
    Inventor: Marvell World Trade Ltd.
  • Publication number: 20130173994
    Abstract: In one embodiment a variable barrel shifter includes a shifter operable to apply a cyclic shift to each of a number of portions of a data word, a pivot circuit operable to swap sections of the data word around at least one pivot point in the data word, a first multiplexer operable to select between an input of the variable barrel shifter or an output of the pivot circuit as an input to the shifter, a second multiplexer operable to select between the input of the variable barrel shifter or an output of the shifter as an input to the pivot circuit, and a third multiplexer operable to select between the output of the shifter or the output of the pivot circuit as an output to the variable barrel shifter.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Inventors: Dan Liu, Qi Zuo, Yong Wang, Yang Han, Shaohua Yang
  • Publication number: 20130132800
    Abstract: Allocation process that allows erasure coded data to be stored on any of a plurality of disk drives, in a pool of drives, so that the allocation is not tied to a fixed group of drives. Still further, the encoded data can be generated by any of multiple different erasure coding algorithms, where again storage of the encoded data is not restricted to a single group of drives based on the erasure algorithm being utilized to encode the data. In another embodiment, the encoded data can be “stacked” (aligned) on select drives to reduce the number of head seeks required to access the data. As a result of these improvements, the system can dynamically determine which one of multiple erasure coding algorithms to utilize for a given incoming data block, without being tied to one particular algorithm and one particular group of storage devices as in the prior art.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: SimpliVity Corporation
    Inventors: Michael W. HEALEY, JR., David Cordella, Arthur J. Beaverson, Steven Bagby
  • Patent number: 8448256
    Abstract: According to an embodiment, a programmable logic device includes a plurality of logic blocks, memory and a logic unit. The logic blocks are grouped into one or more partitions. The memory stores authentication and partition information uploaded to the programmable logic device prior to partition programming. The logic unit authenticates programming access to the one or more partitions based on the authentication information and controls programming of the one or more partitions based on the partition information.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: May 21, 2013
    Assignee: Infineon Technologies AG
    Inventors: Joerg Borchert, Jurijus Cizas, Shrinath Eswarahally, Mark Stafford, Rajagopalan Krishnamurthy
  • Patent number: 8448018
    Abstract: The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 21, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Patent number: 8448044
    Abstract: A method begins by a processing module determining a retrieval threshold for retrieving a set of encoded data slices from a dispersed storage network (DSN), wherein the set of encoded data slices represents data encoded using a dispersed storage error encoding function having a pillar width of “n”, a decode threshold of “k”, and an encoding ratio of n?k>k and wherein the retrieval threshold is in accordance with the encoding ratio. The method continues with the processing module issuing data retrieval requests to the DSN for the set of encoded data slices and receiving encoded data slices of the set of encoded data slices to produce received encoded data slices. The method continues with the processing module decoding the received encoded data slices to recapture the data when a number of received encoded data slices compares favorably to the retrieval threshold.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: May 21, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Greg Dhuse, Ilya Volvovski, Andrew Baptist, Sebastien Vas, Zachary J. Mark
  • Patent number: 8433976
    Abstract: Interleaver designs and interleaving methods that perform block-wise interleaving by reading blocks into and out of memories, where a block can be written to the memory before another block has finished being read out of the memory, without data clashes, are provided. Corresponding deinterleavers and deinterleaving methods are disclosed.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: April 30, 2013
    Assignee: Altera Corporation
    Inventor: Suleyman Sirri Demirsoy
  • Patent number: 8429499
    Abstract: A disk drive for encrypting user data. A motor configured to rotate a disk which stores encoded user data and an encryption flag which has not been encoded. An encoder/decoder processor configured to encode the user data that is written into the disk without encoding the encryption flag, and decodes the user data that is read out from the disk without decoding the encryption flag that is read out from the disk. An encryption processor configured to encrypt the user data at the encryption flag, wherein the encryption flag indicates encryption before the encoder/decoder processor starts encoding, and wherein the encryption processor obtains an encryption flag read out from the disk before the encoder/decoder processor completes decoding of the user data read out from the disk, commencing decryption of decoded data where the encryption flag indicates encryption before decoding of the user data is complete.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 23, 2013
    Assignee: HGST Netherlands B.V.
    Inventors: Kei Akiyama, Yasuhiro Takase, Noritoshi Shinto
  • Patent number: 8429489
    Abstract: One or more methods and systems of effectively retrieving data stored in a media of a storage device are presented. The one or more methods and systems are implemented by way of correcting and detecting errors using a multi-stage decoding process. In one embodiment, the storage device comprises a magnetic hard drive. In one embodiment, the system and method applies an encoding/decoding technique that allows error correction and detection to be performed over a number of successive decode stages or processing stages. Use of the system and method increases the maximum number of symbol errors that may be corrected in an encoded codeword, providing an improvement in data recovery.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: April 23, 2013
    Assignee: Broadcom Corporation
    Inventor: Andrei Vityaev
  • Patent number: 8423875
    Abstract: Methods and apparatus for error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Arthur J. O'Neill, Patrick J. Meaney
  • Patent number: 8413014
    Abstract: A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: April 2, 2013
    Assignee: Oracle America, Inc.
    Inventors: Jin Lu, Keith G. Boyer
  • Patent number: 8407563
    Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such reliability information may be used to identify particular symbols with a higher likelihood of error such that these symbols may be changed in an attempt to reduce the total number of errors in the data. In an embodiment, a soft-decision ECC decoding path may include a reliability checker operable to receive bits of data read from a data store and operable to associate a reliability factor with each bit of data. Then, an update module may iteratively change bits or groups of bits based upon an ordering of the reliability factors.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: March 26, 2013
    Assignee: STMicroelectronics, Inc.
    Inventors: Razmik Karabed, Hakan C. Ozdemir, Vincent Brendan Ashe, Richard Barndt
  • Patent number: 8397135
    Abstract: A recording apparatus includes a first operation unit that calculates an EDC intermediate value from first data in a first region at least including data to be read after an EDC when reading data in a second sequence in a first sector from a data buffer that stores a block, a data memory that stores at least part of the first data used for operation by the first operation unit, a second operation unit that reads data excluding the first data from the block as second data from the data buffer and calculates the EDC based on the second data and the EDC intermediate value, and an integration unit that integrates the first data, the second data and the EDC, wherein the integration unit receives the EDC and the second data from the second operation unit, receives the first data from the data memory, and integrates and outputs them.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: March 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takeo Ariyama
  • Patent number: 8386888
    Abstract: An error correcting circuit includes a marker decoder for sampling 2-bit markers from a data string and, from sample values of the 2-bit markers, determine whether there is an occurrence of an error on the 2-bit markers, of an insertion error, or of a deletion error. The circuit also includes an error corrector for performing an error correction on the data string received from the marker decoder by using an error correcting code in the data string. When either one of the insertion error and the deletion error is determined to have occurred, the marker decoder can perform another error correction on the either one of the insertion error and the deletion error, and output the data string from which the 2-bit markers are removed.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: February 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshio Ito
  • Patent number: 8381076
    Abstract: Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code. This averages any possible bit errors over a larger data area and allows a greater number of errors to be corrected by a combining the ECC codes in the coverage area without substantially changing the overall size of ECC codes being stored over a single sector approach. In one embodiment of the present invention, the size of the data block utilized for ECC coverage is variable and can be selected such that differing areas of the memory array or data types can have a differing ECC data coverage sizes. It is also noted that the ECC algorithm, math base or encoding scheme can also be varied between these differing areas of the memory array.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: February 19, 2013
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • Publication number: 20130042163
    Abstract: The invention is directed to a method for reading information from an optical data storage medium, operating by: obtaining at least one coding/decoding unit of the optical data storage medium wherein the coding/decoding unit comprises a plurality of codewords; checking if the coding/decoding unit is reliable; and when the coding/decoding unit is not reliable; selecting at least one spec-defined codeword from the plurality of codewords. The spec-defined codeword includes a plurality of spec-defined fields defined by the specification of the coding/decoding unit; checking whether the spec-defined codeword is reliable; and when the spec-defined codeword is reliable, retrieving information from the spec-defined codeword.
    Type: Application
    Filed: October 15, 2012
    Publication date: February 14, 2013
    Applicant: MediaTek Inc.
    Inventor: MediaTek Inc.