Dynamic Data Storage Patents (Class 714/769)
  • Patent number: 8091009
    Abstract: Symbol by symbol MAP detection for signals corrupted by colored and/or signal dependent noise. A novel means is presented for recursive calculation of forward metrics (?), backward metrics (?), and corresponding soft information (e.g., which can be provided as LLRs (log likelihood ratios)) within communication systems in which a trellis can be employed to perform demodulation of a received signal sequence. For signals that have been corrupted by colored and/or signal dependent noise, this means provides for the ability to perform novel soft information calculation for subsequent use in iterative decoding processing. Many types of communication channels can benefit from this novel means of detection including communication channels within hard disk drives (HDDs).
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: January 3, 2012
    Assignee: Broadcom Corporation
    Inventor: Ravi Motwani
  • Patent number: 8086914
    Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: December 27, 2011
    Assignee: NetApp. Inc.
    Inventors: Jeffrey S. Kimmel, Rajesh Sundaram, George Totolos, Jr., Michael W. J. Hordijk
  • Patent number: 8086938
    Abstract: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a data type if there is any error and returning back to error state detecting step if there is no any error, detecting whether the FIS is a ATAPI packet command CDB (Command Descriptor Block) when the FIS is the data format, and writing a special tag to the CDB and returning back to the error detecting step.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: December 27, 2011
    Assignee: Mediatek Inc.
    Inventors: Pao-Ching Tseng, Shu-Fang Tsai, Chuan Liu
  • Patent number: 8086937
    Abstract: An efficient method to apply an erasure encoding and decoding scheme across dispersed data stores that receive constant updates. A data store is a persistent memory for storing a data block. Such data stores include, without limitation, a group of disks, a group of disk arrays, or the like. An encoding process applies a sequencing method to assign a sequence number to each data and checksum block as they are modified and updated onto their data stores. The method preferably uses the sequence number to identify data set consistency. The sequencing method allows for self-healing of each individual data store, and it maintains data consistency and correctness within a data block and among a group of data blocks. The inventive technique can be applied on many forms of distributed persistent data stores to provide failure resiliency and to maintain data consistency and correctness.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: December 27, 2011
    Assignee: Quest Software, Inc.
    Inventors: Siew Yong Sim-Tang, Semen Alexandrovich Ustimenko
  • Patent number: 8086935
    Abstract: An apparatus and method are disclosed for correcting errors in data obtained from read operations on a storage medium. Errors that occur in a minority of read operations for the data are corrected by a voting technique. The data may then be processed with error correcting code to correct errors that occur in a majority of read operations.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: December 27, 2011
    Assignee: Marvell International Ltd.
    Inventor: Joseph Sheredy
  • Patent number: 8055978
    Abstract: A buffer memory includes a memory cell array, a flag cell array, and a error correction block. The memory cell array has a plurality of word lines. Each of the plurality of word lines are electrically connected to a plurality of memory cells storing data. The flag cell array has a plurality of flag cells. Each of the plurality of flag cells is connected to each of the word lines and stores information that indicates whether error correction of the data has been performed. The error correction block performs error correction on the data output from the memory cell array in response to a command received through a host interface and flag data output from the flag cell array.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun Kwon Kim, Byeong Hoon Lee, Ki Hong Kim, Seung Won Lee
  • Patent number: 8051361
    Abstract: The present invention provides a distributed clustering method to allow multiple active instances of consistency management processes that apply the same encoding scheme to be cooperative and function collectively. The techniques described herein facilitate an efficient method to apply an erasure encoding and decoding scheme across dispersed data stores that receive constant updates. The technique can be applied on many forms of distributed persistent data stores to provide failure resiliency and to maintain data consistency and correctness.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: November 1, 2011
    Assignee: Quest Software, Inc.
    Inventors: Siew Yong Sim-Tang, Semen Alexandrovich Ustimenko
  • Patent number: 8032816
    Abstract: An apparatus and method for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ operation is generated during normal operation. A comparison module compares an error location indicator with a stored error location indicator. The error location indicator includes a memory location of the correctable bit error. The stored error location indicator corresponds to a previously stored error location indicator of a previous correctable bit error. A storage module stores the error location indicator if the comparison module determines that the error location indicator differs from a stored error location indicator. An error counter module increases an error counter corresponding to the error location indicator if the comparison module determines that the error location indicator matches a stored error location indicator.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Carol Spanel, Andrew Dale Walls
  • Patent number: 8032802
    Abstract: In a storage device, a bad-sector detecting unit detects a bad sector, and a process determining unit determines whether rescue process is performed for the bad sector. Upon determining to perform the rescue process, the process determining unit controls a damping ratio. A table-updating control unit records various information in an alternating-process control table, and a controller records and reproduces data with respect to a rescue sector based on the alternating-process control table.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Limited
    Inventor: Yasuaki Morimoto
  • Patent number: 8020073
    Abstract: Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: September 13, 2011
    Assignee: International Business Machines Corporation
    Inventors: Philip George Emma, Robert Kevin Montoye, William Robert Reohr
  • Patent number: 8006167
    Abstract: A system for decoding coded data printed in ink on a surface is provided. The coded data has a registration structure which has at least two clock tracks indicative of a position of the coded data in the direction perpendicular to an alignment direction and two alignment lines for each clock track. The two alignment lines are indicative of the position of the respective clock track. The system has a decoder for determining, using an alignment phase-locked loop (PLL), a position of the alignment lines for a respective clock track, determining, using the position of the alignment lines, the position of each respective track, and updating the alignment PLL.
    Type: Grant
    Filed: February 21, 2010
    Date of Patent: August 23, 2011
    Assignee: Silverbrook Research Pty Ltd
    Inventors: Paul Lapstun, Kia Silverbrook
  • Patent number: 8001450
    Abstract: The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side parity generation circuit that generates parities from read data, and a syndrome generation circuit that generates a syndrome bit that indicates an error bit from the read parity bits and generated parity bits are constituted so as to be capable of switching, according to the plurality of ECC code lengths.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: August 16, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yasuhiro Onishi, Toshiya Miyo
  • Patent number: 7979776
    Abstract: An error correction block having an extended format compatible with a standardized format of a conventional error correction block, a method and apparatus for generating the error correction block, and a method of correcting an error using the error correction block. The method of generating an error correction block includes adding extra parity information for error correction to input data which is of a smaller size than main data of a standardized reference format, thereby generating an extra error correction block which is the same size as the main data, and generating an error correction block complying with the reference format using the extra error correction block as the main data.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: July 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hee Hwang, In-sik Park
  • Patent number: 7975207
    Abstract: A data recording and/or reproducing apparatus and method for an information recording medium includes: an extra ECC encoder; and an extra ECC controller determining whether extra ECC is applied to the information recording medium, and controlling the extra ECC encoder to generate an extra parity data block corresponding to data that is to be recorded on the information storage medium. The extra ECC encoder includes: an extra parity generator generating an extra ECC data block based on data that is to be recorded on the information recording medium, performing ECC on the extra ECC data block, and generating at least one extra parity. An extra parity interleaver interleaves the at least one extra parity and generating the extra parity data block.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hee Hwang, Hyun-kwon Chung, Joon-hwan Kwon, Hyun-jeong Park
  • Patent number: 7975208
    Abstract: An optical storage medium recording apparatus is provided a data preparing and ECC encoding circuit that both prepares the data by combining different categories of data into data sequences in accordance with a data layout on the optical storage medium and encodes the combined data. The encoded data is temporarily stored in a data buffer, and subsequently successively read out by a recording circuit for recording onto the optical storage medium according to the data layout. For a Blu-ray disc recording apparatus, the data preparing and ECC encoding circuit includes a LDC/BIS encoder for generating long distance error correction codes (LDC) and burst indicator subcodes (BIS) from the combined data to form LDC and BIS encoded data, which is temporarily stored in the data buffer. The recording circuit includes an interleave circuit for interleaving the LDC and BIS data to form physical clusters for recording on the disc.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: July 5, 2011
    Assignee: Mediatek Inc.
    Inventors: Ming-Yang Chao, Ching-Wen Hsueh
  • Patent number: 7975206
    Abstract: An ECC block is constituted by RS(248,216,33). Of a data length of 216 bytes (symbols), only 16 bytes are allocated to BCA data and the remaining 200 bytes are used for fixed data having a predetermined value. Using the fixed data of 200 bytes and the BCA data of 16 bytes, parities of 32 bytes (symbols) are calculated. Only the BCA data of 16 bytes and the parities of the former 16 bytes of the 32-byte parities, that is, a total of 32 bytes only, are recorded in a burst cutting area of an optical disc. In decoding, error correction processing is carried out by using the fixed data of 200 bytes. The unrecorded parities of 16 bytes are processed as having been erased. Thus, the error correction capability in a burst cutting area of an optical disc can be improved.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: July 5, 2011
    Assignees: Sony Corporation, Panasonic Corporation, Koninklijke Philips Electronics, N.V.
    Inventors: Shoei Kobayashi, Susumu Senshu, Tamotsu Yamagami, Makoto Usui, Hideshi Ishihara, Mitsurou Moriya, Cornelis Marinus Schep, Jakob Gerrit Nijboer, Aalbert Stek
  • Patent number: 7971125
    Abstract: Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: June 28, 2011
    Assignee: Agere Systems Inc.
    Inventors: Nils Graef, Erich F. Haratsch
  • Publication number: 20110145680
    Abstract: A disk drive for encrypting user data. A motor configured to rotate a disk which stores encoded user data and an encryption flag which has not been encoded. An encoder/decoder processor configured to encode the user data that is written into the disk without encoding the encryption flag, and decodes the user data that is read out from the disk without decoding the encryption flag that is read out from the disk. An encryption processor configured to encrypt the user data at the encryption flag, wherein the encryption flag indicates encryption before the encoder/decoder processor starts encoding, and wherein the encryption processor obtains an encryption flag read out from the disk before the encoder/decoder processor completes decoding of the user data read out from the disk, commencing decryption of decoded data where the encryption flag indicates encryption before decoding of the user data is complete.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 16, 2011
    Inventors: Kei AKIYAMA, Yasuhiro TAKASE, Noritoshi SHINTO
  • Patent number: 7962833
    Abstract: An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data in a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: June 14, 2011
    Assignee: LSI Corporation
    Inventors: Rajesh Juluri, Cheng Qian
  • Patent number: 7953907
    Abstract: A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: May 31, 2011
    Assignee: Marvell International Ltd.
    Inventors: Huy Tu Nguyen, William C. Wong, Kha Nguyen
  • Patent number: 7949929
    Abstract: A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first inverting circuit electrically connected to the error-correcting module for inverting data and error-correcting codes corresponding to the data. When the controller both writes all 0xFF data in the data area and writes all 0xFF error-correcting codes in the error-correcting code area, the first inverting circuit inverts the all 0xFF data and the all 0xFF error-correcting codes into all 0x00 data and all 0x00 error-correcting codes, respectively.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: May 24, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Ming-Jen Liang, Wee-Kuan Gan, Chih-Jen Hsu
  • Patent number: 7945845
    Abstract: A method and system decode a sequence of symbols received via a channel to a codeword of an error-correcting code. Log-likelihood ratios are determined from a sequence of symbols received via a channel. A set of constraints is initialized according to the log-likelihood ratios. An adaptive linear programming decoder is applied to the set of constraints and the log- likelihood ratios according to an error-correcting code to produce an estimate of the codeword and an updated set of constraints. If the estimate of the codeword is a non-integer pseudo codeword, further update the set of updated constraints with a set of integer constraints if the estimate of the codeword is the non-integer pseudo codeword, and proceeding with the applying step, and otherwise producing the estimate of the codeword as the final codeword.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: May 17, 2011
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Stark C. Draper, Jonathan S. Yedidia
  • Patent number: 7945837
    Abstract: A recording medium on which a recording/reproducing unit block is recorded, an apparatus to record and/or reproduce data on/from the recording medium, and a method of recording/reproducing the data on/from the recording medium. The recording/reproducing unit block comprises invalid data used in disc certification, and an identifier to indicate that the invalid data is included in the recording/reproducing unit block, the invalid data being used during the disc certification on a portion of the recording medium or the entire recording medium.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: May 17, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hee Hwang, Jung-wan Ko
  • Publication number: 20110107186
    Abstract: A method is provided for correcting a write defect in a data storage apparatus comprising a storage medium. The method comprises reading information from a track of the storage medium in which a write defect occurs, calculating a number of error-corrected error correction code symbols in sectors of the track based on the read information, determining a number of sectors on which write defect correction is to be performed by comparing the calculated number of error-corrected error correction code symbols with a threshold, and performing a rewrite operation on the track, beginning at a starting sector determined by the number of sectors on which write defect correction is to be performed.
    Type: Application
    Filed: November 3, 2010
    Publication date: May 5, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-jin KIM, Jae-hyuk YU
  • Patent number: 7934143
    Abstract: A coding system for digital data includes a constrained encoder module that generates encoded data based on a first constrained code, a bit insertion module that inserts at least one bit location in the encoded data, an error correcting code (ECC) encoder module that generates ECC parity bits based on the at least one bit location and the encoded data, and an inner encoding module that generates inner-code parity bits based on the encoded data and programs the inner-code parity bits into the at least one bit location.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: April 26, 2011
    Assignee: Marvell International Ltd.
    Inventors: Zining Wu, Panu Chaichanavong, Gregory Burd
  • Patent number: 7933876
    Abstract: A system and method for data storage by shredding and deshredding of the data allows for various combinations of processing of the data to provide various resultant storage of the data. Data storage and retrieval functions include various combinations of data redundancy generation, data compression and decompression, data encryption and decryption, and data integrity by signature generation and verification. Data shredding is performed by shredders and data deshredding is performed by deshredders that have some implementations that allocate processing internally in the shredder and deshredder either in parallel to multiple processors or sequentially to a single processor. Other implementations use multiple processing through multi-level shredders and deshredders. Redundancy generation includes implementations using non-systematic encoding, systematic encoding, or a hybrid combination.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: April 26, 2011
    Assignee: Peerify Technologies, LLC
    Inventors: Douglas R. de la Torre, David W. Young
  • Patent number: 7930614
    Abstract: A test apparatus is provided for testing memory under test which stores a data string including an error correction code in the form of additional data. The test apparatus comprises: a logic comparator which compares each of the data sets included in a data string read out from the memory under test with a corresponding anticipated value created beforehand; a data error count unit which counts the number of data sets that do not match the respective anticipated values; and a defect detection unit which provides a function whereby, in a case that the count value counted by the error count unit exceeds a predetermined upper limit number which is equal to or greater than 1, determination is made that the memory under test is defective.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: April 19, 2011
    Assignee: Advantest Corporation
    Inventor: Shinya Sato
  • Patent number: 7907362
    Abstract: Among other disclosed subject matter, a magnetic disk controller can include an index detecting unit to detect an index of the magnetic disk, an error check code generating unit to, after the index detecting unit detects the index, generate a first error check code for first write data based on the first write data and a first physical address of a first sector subsequent to the detected index, and a writing control unit to cause the first error check code generated by the error check code generating unit, the first write data and the first physical address to be written into a second sector subsequent to the first sector.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: March 15, 2011
    Assignee: Marvell International Ltd.
    Inventors: Soichi Isono, Minoru Tsukada, Tomoki Oura, Koji Takahashi
  • Patent number: 7904791
    Abstract: An information recording medium to which data extra ECC is applied, and a method and apparatus for managing the information storage medium is provided. The method includes: determining whether extra ECC is applied with respect to data that is to be recorded on the information recording medium, and deciding an extra ECC application rate; assigning an area for recording a data block including an extra parity generated by applying the extra ECC to the data that is to be recorded on the information recording medium, to the information recording medium; assigning an extra ECC management information area for recording extra ECC management information for managing the extra ECC, to the information recording medium; and recording or updating the extra ECC management information in the extra ECC management information area. Therefore, it is possible to improve reproduction reliability while maintaining reproduction compatibility with conventional apparatuses.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: March 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hee Hwang, Jung-wan Ko
  • Publication number: 20110055665
    Abstract: A data modulation method and a data error correction method are provided. The data modulation method includes generating a channel sequence for an input sequence, determining whether or not the channel sequence violates a Run Length Limit (RLL) constraint, and performing, when the channel sequence violates the RLL constraint, bit flip at a position prior to a position at which the RLL constraint is violated among positions of bits included in the channel sequence. The data error correction method includes detecting an error bit of received data using a parity check matrix, determining whether or not the error bit is an error caused by bit flip, and correcting the error bit when the error bit is an error caused by bit flip for applying an RLL constraint.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 3, 2011
    Applicant: LG ELECTRONICS INC.
    Inventor: Jun Lee
  • Publication number: 20110035634
    Abstract: A method for adaptively applying an error-correcting code to a storage device is disclosed. A determination is made that a system is in an idle state of input/output requests. First data symbols are copied into a first location within a buffer. First data symbol errors corrected using a first error-correcting code. Second data symbols including corrected bits are written in a second location on the recording media with a second error-correcting code. An error number for the second data symbols in the second location is determined. If the error number is below a first threshold error number, the first data symbols are deleted. If the error number is above the first threshold error number, the second data symbols are deleted.
    Type: Application
    Filed: August 10, 2009
    Publication date: February 10, 2011
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Mario Blaum, Kurt A. Rubin, Manfred E. Schabes
  • Patent number: 7876652
    Abstract: First data representing user data and third data use the same error correction codes. The first data has a first error correction block structure and the third data has a second error correction block structure. That is to say, the first data and the third data have their respective error correction block structures proper for them. In particular, the recording density of the third data is made less dense than the recording density of the first data, and the number of correction codes in the first error-correction block is set at a multiple of m whereas the number of correction codes in the second error-correction block is set at n/m times the number of correction codes in the first error-correction block so that a data-piece count in the second error-correction block is also n/m times a data-piece count in the first error-correction block. As a result, it is possible to provide a good technique of recording shipping-time information onto a high-recording-density disc.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: January 25, 2011
    Assignee: Sony Corporation
    Inventor: Susumu Senshu
  • Patent number: 7877667
    Abstract: In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: January 25, 2011
    Assignee: Panasonic Corporation
    Inventors: Kenichi Origasa, Kiyoto Ohta
  • Patent number: 7873896
    Abstract: The application discloses storage circuitry with a pulse generator used to control switches on two inputs to the storage circuitry thereby connecting either operational data or diagnostic data to the storage circuitry. Thus, the pulse generator selects the data paths by outputting pulses to a diagnostic output or to a functional output, and these pulses controlling the switches on the two inputs to the storage circuitry.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: January 18, 2011
    Assignee: ARM Limited
    Inventors: Chih-Wei Huang, Marlin Wayne Frederick, Jr., Stephen Andrew Kvinta, Kerry Karl Nick
  • Patent number: 7870463
    Abstract: A DSP of a DVD recorder includes: a gain setting portion determining appropriate values of a first gain ? and a second gain ? when playback of an optical disc is performed, recording the first gain ? and the second gain ? thus determined in a gain storing portion, and setting them in a main differential amplifier and a sub differential amplifier, respectively; and a correction performing portion reading, when recording on the optical disc is performed, the first gain ? and the second gain ? stored in the gain storing portion, correcting at least one of them, and setting them in the main differential amplifier and the sub differential amplifier, respectively.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: January 11, 2011
    Assignee: Funai Electric Co., Ltd.
    Inventors: Shunsuke Sehara, Yasunori Kuwayama
  • Publication number: 20100332892
    Abstract: A hard disk drive with a disk that has a plurality of data bits. The drive includes a circuit that reads each data bit n times and selects a value for the bit based on a reliability factor. The circuit may select a bit based at least in part on the most frequent occurrence of one of a plurality of values. For example, if more 0s occurred than 1s the bit would be set to 0. The reliability factor may be a ratio of the occurrence of 0s to the occurrence of 1s. A bit can be not selected or deselected if the reliability factor exceeds a threshold value.
    Type: Application
    Filed: June 29, 2009
    Publication date: December 30, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Yawshing Tang
  • Patent number: 7861141
    Abstract: A method and device for error analysis particularly adoptable for a recording medium such as an optical disc are disclosed. The present invention executes an encoding-like operation such as an interleaving operation to error flags during reproducing data from the optical disc, so as to obtain number and distribution of the errors on the disc.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: December 28, 2010
    Assignee: MEDIATEK Inc.
    Inventors: Hsin-cheng Chen, Ching-wen Hsueh
  • Patent number: 7861142
    Abstract: Four ECC blocks are recorded in a burst cutting area of an optical disc. Each ECC block is constituted by a BCA content code of 1 byte, content data length of 1 byte, and content data of 14 bytes. Of the BCA content data, the leading 6 bits are used for application ID and the remaining 2 bits are used for block number. Disc ID is stored in the content data. Since the four ECC blocks exist, the optical disc can be managed individually by four applications at the maximum. Thus it becomes possible to manage the same optical disc by a plurality of applications.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: December 28, 2010
    Assignees: Sony Corporation, Panasonic Corporation, Koninklijke Philips Electronics N.V.
    Inventors: Shoei Kobayashi, Susumu Senshu, Tamotsu Yamagami, Makoto Usui, Hideshi Ishihara, Mitsurou Moriya, Cornelis Marinus Schep, Jakob Gerrit Nijboer, Aalbert Stek
  • Patent number: 7861143
    Abstract: A method is provided of data storage by encoding a bit stream on a surface. The method involves printing coded data on the surface which encodes the bit stream, and printing alignment data on the surface which is indicative of a position of the coded data on the surface. The alignment data has a first registration structure indicative of a plurality of reference points indicative of a position of the coded data in an alignment direction, and a second registration structure indicative of a plurality of reference points indicative of a position of the coded data in a direction perpendicular to the alignment direction.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: December 28, 2010
    Assignee: Silverbrook Research Pty Ltd
    Inventors: Paul Lapstun, Kia Silverbrook
  • Publication number: 20100306624
    Abstract: A recording and/or reproducing method, a recording and/or reproducing apparatus, and a computer readable recording medium storing a program for performing the method. A recording unit block in which invalid data is partially padded is written on an information storage medium along with padding information indicating that the invalid data is included in the recording unit block. The padding information is useful in determining whether the recording unit block includes the padding data. Accordingly, unnecessary retrial processes of a drive system are reduced such that the performance of the drive system is improved and error correction capability is enhanced.
    Type: Application
    Filed: June 14, 2010
    Publication date: December 2, 2010
    Inventors: Sung-hee Hwang, Jung-wan Ko
  • Patent number: 7843660
    Abstract: A disk drive is disclosed comprising a disk having a plurality of data tracks, wherein each data track comprises a plurality of data sectors. A head is actuated radially over the disk in order to read one of the data sectors from a target data track on the disk. The data sector is stored in a buffer and decoded with an error correction code (ECC) decoder. When the decode fails, an erasure window is adjusted based on a number of non-read data sectors recorded in the target data track, wherein the erasure window comprises a length spanning at least one ECC symbol in the data sector. The data sector is read from the buffer and decoded with the ECC decoder using the erasure window.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: November 30, 2010
    Assignee: Western Digital Technologies, Inc.
    Inventor: Teik Ee Yeo
  • Patent number: 7840878
    Abstract: A system includes a host first-in first-out (FIFO) module, a first encoder module, a control module, a disk FIFO module, and a second encoder module. The host FIFO module receives a block having data and selectively receives a host logical block address (HLBA). The first encoder module generates a first checksum based on the data and the HLBA and generates a first encoded block. The control module appends the HLBA to the first encoded block and generates an appended block. The disk FIFO module receives the block from the host FIFO module. The second encoder module selectively generates a second checksum based on the HLBA and the data in the block received by the disk FIFO module. The second encoder module compares the block received by the disk FIFO module to the block received by the host FIFO module based on the first and second checksums.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: November 23, 2010
    Assignee: Marvell International Ltd.
    Inventors: Heng Tang, Gregory Burd, Soichi Isono, Son Hong Ho, Vincent Wong, Zining Wu
  • Patent number: 7836379
    Abstract: A system includes a receive module, a control module and a read module. The receive module receives a first block that includes first data, a first cyclic redundancy check (CRC) checksum, and a first error-correcting code (ECC) value. The first CRC checksum and the first ECC value include a logical block address (LBA). The control module generates a first derived CRC checksum based on the first data. The first derived CRC checksum does not include the LBA. The read module reads a second block from a parity disk. The second block includes parity data, a second CRC checksum, and a second ECC value. The second CRC checksum and the second ECC value include the LBA.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: November 16, 2010
    Assignee: Marvell International Ltd.
    Inventors: Paul B. Ricci, Mohammad M. Negahban, Yujun Si
  • Patent number: 7827469
    Abstract: An interpretive script language that provides an abstraction layer between redundant array of independent disks (RAID) algorithms and RAID hardware architecture. The interpretive script language provides greater flexibility and performance over conventional RAID processors. The interpretive script language may be used with any RAID hardware architecture, is not dependent on a specific RAID algorithm, and enables efficient communication to a RAID processor from any entity that desires RAID services. The entity requesting RAID services sends a command to a RAID processor, which includes pointers to a script entry point for scripts stored in a table memory in the RAID processor, and pointers to the data and parity (for example, in a buffer memory) on which to perform exclusive OR (XOR) operations.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: November 2, 2010
    Assignee: ADPT Corporation
    Inventor: Sanjay Subbarao
  • Patent number: 7823042
    Abstract: A recording medium on which a recording/reproducing unit block is recorded, an apparatus to record and/or reproduce data on/from the recording medium, and a method of recording/reproducing the data on/from the recording medium. The recording/reproducing unit block comprises invalid data used in disc certification, and an identifier to indicate that the invalid data is included in the recording/reproducing unit block, the invalid data being used during the disc certification on a portion of the recording medium or the entire recording medium.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: October 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hee Hwang, Jung-wan Ko
  • Publication number: 20100269023
    Abstract: Various embodiments of the present invention provide systems and methods for deriving data from a defective media region. As an example, a method for deriving data from a defective media region is disclosed that includes providing a storage medium and performing a media defect detection that indicates a defective region on the storage medium. A first data decode is performed on data corresponding to the defective region. The first data decode yields a first output. It is determined that the first output failed to converge and based at least in part on the failure of the first output to converge, a second data decode is performed on the data corresponding to the defective region. The second data decode includes zeroing out any soft data corresponding to the defective region and providing a second output.
    Type: Application
    Filed: April 17, 2009
    Publication date: October 21, 2010
    Inventors: Shaohua Yang, Weijun Tan, Yuan Xing Lee
  • Patent number: 7810017
    Abstract: Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code. This averages any possible bit errors over a larger data area and allows a greater number of errors to be corrected by a combining the ECC codes in the coverage area without substantially changing the overall size of ECC codes being stored over a single sector approach. In one embodiment of the present invention, the size of the data block utilized for ECC coverage is variable and can be selected such that differing areas of the memory array or data types can have a differing ECC data coverage sizes. It is also noted that the ECC algorithm, math base or encoding scheme can also be varied between these differing areas of the memory array.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: October 5, 2010
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • Patent number: 7805659
    Abstract: A method of controlling a RAID system including a plurality of disk devices is provided. The method allows for reading data recorded onto an area adjacent to an area where a write error occurs when the write error is detected while data is written into the disk device. When an error is detected from the data read from the adjacent area, the data recorded onto the adjacent area is restored by using a RAID function and the restored data is written into the adjacent area.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: September 28, 2010
    Assignee: Fujitsu Limited
    Inventor: Eisaku Takahashi
  • Publication number: 20100241930
    Abstract: An error correction device is provided. The error correction device includes a code storage unit where a plurality of error correction codes are stored, a first error correction unit to correct a data error detected from input data by using one of a plurality of error correction codes and to output correction data, a buffer to store the correction data, and a second error correction unit to generate a new correction code from the correction data, to compare another of a plurality of error correction codes with the new correction code and to output a comparison result.
    Type: Application
    Filed: March 10, 2010
    Publication date: September 23, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sil Wan CHANG, Bum Seok Yu, Sang Kyoo Jeong, Dong Gi Lee
  • Patent number: RE42962
    Abstract: An optical disk having a diameter less than 140 mm and, a thickness of 1.2 mm±0.1 mm, with a plurality of record tracks having data recorded thereon as embossed pits representing information and exhibiting a track pitch in the range between 0.646 ?m and 1.05 ?m; with the tracks being divided into a lead-in area, a program area and a lead-out area. The data includes table of contents (TOC) information recorded in a plurality of sectors in at least one TOC track and user information recorded in a plurality of sectors in user tracks; with the TOC information including addresses of start sectors recorded in the user tracks. The data (both user and TOC information) is encoded in a long distance error correction code having at least eight parity symbols, and is run length limited (RLL) modulated.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: November 22, 2011
    Assignee: Sony Corporation
    Inventors: Jun Yonemitsu, Ryuichi Iwamura, Shunji Yoshimura, Makoto Kawamura