Abstract: The disclosure discloses a method and apparatus for decoding and checking a tail-biting convolutional code, so as to solve the problem of reducing a processing time delay in decoding and checking the tail-biting convolutional code in the prior art. The disclosure fully utilizes structural features of the tail-biting convolutional code to re-sort Log-Likelihood Ratio (LLR) values input into a decoder, and by reconstructing a derivative generator polynomial of a convolutional code, allows the decoder to output in serial according to a normal ordering of information bits during backtracking, that is, a first bit of an information sequence is first decoded successfully. Thus, CRC checking may be activated as soon as possible, so that part of the backtracking process and the CRC checking may be performed in parallel, thereby achieving the objective of reducing a processing time delay in decoding and checking the tail-biting convolutional code.

Abstract: A method for decoding a plurality of flash memory cells which are error correction-coded, the method may include: comparing physical values residing in the plurality of flash memory cells to a first set of decision thresholds thereby to provide a first item of comparison information for each of the plurality of cells; comparing physical values residing the plurality of flash memory cells to a second set of decision thresholds, thereby to provide a second item of comparison information for each of the plurality of cells, wherein neither of the first and second sets of decision thresholds is a subset of the other; and determining logical values for the plurality of flash memory cells by combining said first and second items of comparison information.

Abstract: A multistage difference cyclic permutation unit (106) for performing multistage cyclic permutation, an address administration unit (104) for administering addresses of the cumulative LLR memory (101), a received value arrangement unit (103) for generating records during writing of received values to the cumulative LLR memory (101), and a control unit (110) for generating parameters to control each unit from information of a parity check matrix and the current cyclic permutation size are prepared. The address administration unit (104) controls reading/writing addresses of the cumulative LLR memory (101) based on a reading start address from the cumulative LLR memory (101) corresponding to the column block. After the start of reading of a column block, the control unit (110) generates a reading start address in the next decoding of the column block and stores it into the address administration unit (104).

Abstract: A method and apparatus for performing demapping in a wireless communication system utilizing a modulo operation are disclosed. The demapping method of a receiver in a wireless communication system includes receiving an input signal and first information indicating whether a first modulo operation is performed on the input signal from a transmitter; if the first information indicates execution of the first modulo operation, performing a second modulo operation of the input signal, and acquiring a reception signal; generating a maximum function value having a highest probability that the reception signal corresponds to a candidate constellation point of an extended constellation; and generating a log-likelihood ratio (LLR) using the generated maximum function value.

Abstract: A Viterbi decoder which is based on a special instruction set implemented in the processor, enabling it to handle the Viterbi processing with a much lower CPU loading without significantly increasing the hardware complexity. By careful application of appropriate design constraints specific to the SV navigation and analysis of the Viterbi algorithm an optimised architecture can be realized for embedding Viterbi acceleration logic efficiently into a GNSS chipset.

Abstract: A method and apparatus of selecting N metrics among M metrics is provided. The apparatus determines M metrics P(i), where i=1, . . . , M. Each P(i) is represented by B bits. The apparatus determines N metrics among M metrics. The complexity for configuring the circuit is decreased, and the length of the critical path is reduced.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: An encoder and decoder using LDPC-CC (Low Density Parity Check-Convolutional Codes). An encoding rate setting unit sets an encoding rate (s?1)/s (s=z), and an information creating unit sets information including from information Xs,i to information Xz?1,i to zero. A first information computing unit receives information X1,i at time point i to compute the X1(D) term of a formula. A second information computing unit receives information X2,i at time point i to compute the X2(D) term of the formula. A third information computing unit receives information X3,i at time point i to compute the X3(D) term of the formula. A parity computing unit receives parity Pi?1 at time point i?1 to compute the P(D) of the formula. The exclusive OR of the results of the computation is obtained as parity Pi at time i.

Abstract: A method for reducing a number of bits for representing a value is disclosed. A first value represented with a first number of bits is transformed to a second value represented with a second number of bits, wherein the first number of bits is greater than the second number of bits. The transformed second value is scaled by a scale factor to a third value. Transforming includes selecting a target window with a width of a third number of bits, wherein the third number of bits is smaller than the first number of bits. Transforming further includes saturating the first value to a most significant bit (MSB) within the selected target window and extracting bits within the selected target window from the saturated value.

Abstract: A method and system for a sequence estimation in a receiver, such as for use when receiving a sample of a received inter-symbol correlated (ISC) signal corresponding to a transmitted vector of L symbols, with L being a integer greater than 1, and with symbol L being a most-recent symbol and symbol 1 being least recent symbol of the vector. A plurality of candidate vectors may be generated, wherein element L-m of each candidate vector holding one of a plurality of possible values of the symbol L-m, with m is an integer greater than or equal to 1, and elements L-m+1 through L of each candidate vectors holding determined filler values. A plurality of metrics may be generated based on the plurality of candidate vectors, and based on the generated plurality of metrics, a best one of the possible values of the symbol L-m may be selected.

Abstract: A method includes accepting a definition of a mother Error Correction Code (ECC) that is represented by a set of parity check equations and includes first code words, and a definition of a punctured ECC that includes second code words and is derived from the mother ECC by removal of one or more of the parity check equations and removal of one or more punctured check symbols selected from among check symbols of the first code words. A mother decoder, which is designed to decode the mother ECC by exchanging messages between symbol nodes and check nodes in accordance with a predefined interconnection scheme that represents the mother ECC, is provided. An input code word of the punctured ECC is decoded using the mother decoder by initializing one or more of the symbol nodes and controlling one or more of the messages, and while retaining the interconnection scheme.

Abstract: This invention relates to methods for obtaining a bin number of path metrics. When performing such methods, a histogram is provided, which composes a bin number of values, a maximum value and a tail region left or right of the maximum value. A bin number of path metrics is obtained from said values. According to an embodiment a local extremum is removed from said tail region. According to another embodiment the tail region is forced to be convex. According to a further embodiment a maximum metric difference between neighboring metrics is ensured.

Abstract: This invention relates to a method and a circuit for estimating the bit error rate in a data transmission system. Symbols are detected (u) by a maximum likelihood detector (1), which provides path metrics of the decoded path and the best competitor at predetermined symbol positions. Absolute path metric differences (2) are calculated between the decoded path and the best competitor at said predetermined symbol positions. Events (5) are counted when an absolute path metric difference (2) is equal to one of a set of difference values. The bit error rate is estimated based on the number of counted (4) events (5). The invention further comprises a method and a circuit in which a function is applied onto said absolute path metric difference. The function maps quantized logarithms of probabilities to probabilities.

Abstract: Systems and methods for encoding and decoding check-irregular non-systematic IRA codes of messages in any communication or electronic system where capacity achieving coding is desired. According to these systems and methods, IRA coding strategies, including ones that employ capacity-approaching non-systematic IRA codes that are irregular and that exhibit a low error floor, are employed. These non-systematic IRA codes are particularly advantageous in scenarios in which up to half of coded bits could be lost due to channel impairments and/or where complementary coded bits are desired to transmit over two or more communications sub-channels. An encoder includes information bit repeaters and encoders, one or more interleavers, check node combiners, a check node by-pass and an accumulator. A decoder includes a demapper, one or more check node processors, an accumulator decoder, a bit decoder, and one or more interleavers/deinterleavers.

Abstract: A MAP decoder may be implemented in parallel. In one implementation, a device may receive an input array that represents received encoded data and calculate, in parallel, a series of transition matrices from the input array. The device may further calculate, in parallel, products of the cumulative products of the series of transition matrices and an initialization vector. The device may further calculate, in parallel and based on the products of the cumulative products of the series of transition matrices and the initialization vector, an output array that corresponds to a decoded version of the received encoded data in the input array.

Abstract: Systems and methods for intelligently reducing the number of log-likelihood ratios (LLRs) stored in memory of a wireless communication device are described herein. In one aspect, the systems and methods described herein relate to selecting LLRs for storage based on a quality metric. In another aspect, the systems and methods described herein relate to improving communication quality in response to available memory capacity.

Abstract: A disk drive is disclosed comprising a head actuated over a disk comprising a plurality of data tracks. A read signal emanating from the head is sampled to generate read samples, and first log-likelihood ratios (LLRs) are generated in response to the read samples. The first LLRs are biased to generate biased LLRs, and the biased LLRs are decoded into a data sequence, wherein the biased LLRs increase an error rate of the data sequence.

Abstract: There is provided a communication apparatus, including a transmission pattern generation unit that generates a transmission pattern according to a modulation method, a metric calculation unit that calculates an inter-signal distance between a received signal vector of received signals and an estimation vector, which is a product of channel information and the transmission pattern, a maximum likelihood pattern determination unit that determines a maximum likelihood signal pattern from the inter-signal distance calculated by the metric calculation unit, and an error estimation unit that estimates a phase error component and an amplitude error component contained in the received signal vector. The metric calculation unit calculates the inter-signal distance between the received signal vector and the estimation vector by using the phase error component and/or the amplitude error component estimated by the error estimation unit.

Abstract: The various embodiments provide circuitry and methods for packing Log Likelihood Ratio (“LLR”) values into a buffer memory in a compressed format which reduces the amount of buffer memory required. Various embodiments use a type of quantization which reduces the bit width of the LLR values that are stored, with the particular level of quantization depending upon the code rate of the data. The degree, pattern, and periodicity of bit width compression employed may depend upon the code rate of the received transmission. Bit width patterns use for LLR value quantization may be generated by a shift register circuit which provides an efficient mechanism for controlling an LLR packer circuit based upon the code rate of the received signal.

Abstract: A sequence estimator is described. In one embodiment, the sequence estimator includes a plurality of maximum a posteriori probability (MAP) decoding engines each arranged to process a series of windows of a transmitted signal where state metrics produced for an end of one window by one decoding engine are re-used for the initialization of a state metric calculation process performed by another decoding engine on another window of the signal.

Abstract: Systems and methods are provided for generating error events for decoded bits using a Soft output Viterbi algorithm (SOVA). A winning path through a trellis can be determined and decoded information can be generated. Path metric differences can be computed within the trellis based on the winning path. A plurality of error event masks and error event metrics can be generated based on the decoded information and the path metric differences.

Abstract: The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (?) values and check edge message (?) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.

Abstract: A memory efficient, accelerated implementation architecture for BCJR based forward error correction algorithms. In this architecture, a memory efficiency storage scheme is adopted for the metrics and channel information to achieve high processing speed with a low memory requirement. Thus, BCJR based algorithms can be accelerated, and the implementation complexity can be 5 reduced. This scheme can be used in the BCJR based turbo decoder and LDPC decoder implementations.

Abstract: Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

Abstract: A communication system includes: a decoding-probability module for calculating a decoding likelihood with a control unit for characterizing an alternative hypothesis regarding an arriving communication; a null-probability module, coupled to the decoding-probability module, for calculating a null likelihood for characterizing a null hypothesis regarding the arriving communication; a weight-calculation module, coupled to the decoding-probability module, for generating a decision weight corresponding to the decoding likelihood, the null likelihood, or a combination thereof; a reliability calculation module, coupled to the decoding-probability module, for calculating a decoding reliability with the decision weight, the decoding likelihood, and the null likelihood, the decoding reliability corresponding to a decoded-result; and a decoding module, coupled to the reliability calculation module, for decoding the arriving communication with a decoding parameter based on the decoding reliability for communicating with

Abstract: A receiver receives an inter-symbol correlated (ISC) signal with information symbols and a corresponding parity symbol. Values of information symbols are estimated utilizing parity samples that are generated from the parity symbols. One or more maximum likelihood (ML) decoding metrics are generated for the information symbols. One or more estimations are generated for the information symbols based on the one or more ML decoding metrics. A parity metric is generated for each of the one or more generated estimations of the information symbols. The parity metric is generated by summing a plurality of values of one of the generated estimations to generate a sum, and wrapping the sum to obtain a parity check value that is within the boundaries of a symbol constellation utilized in generating the information symbols.

Abstract: A system including a detection module, a reconstruction module, and a correlation module. The detection module receives first signals from a medium and detects data bits from the first signals. The reconstruction module reconstructs the data bits and generates second signals. The correlation module generates first correlation values by correlating the first and second signals and generates second correlation values by self-correlating the second signals. In response to at least one of the first and second signals including a floating number having a plurality of bits and a sign bit, the correlation module generates at least one of the first and second correlation values based on a plurality of most significant bits of the floating number and the sign bit of the floating number. The first and second correlation values indicate whether the data bits detected from the first signals include errors due to defects in the medium.

Abstract: Techniques for decoding levels in non-volatile memory. A level of a cell in a multi-bit non-volatile memory is read. A minimum of Log-Likelihood Ratio (LLR) and a modified LLR to decode the level, wherein the modified LLR is a function of a misplacement probability is used. A value corresponding the decoded level is written to a volatile memory.

Abstract: A receiver apparatus comprises a LDPC decoder that can apply an accelerated belief propagation method for iteratively decoding each code block. When the number of iterations reaches a certain threshold value, the accelerated belief propagation method can adjust the initial condition used in each iteration. The initial condition is adjusted so as to enhance the likelihood of convergence in the iterative method. As a result, performance of the decoder and receiver apparatus can be improved.

Abstract: A low complexity List Viterbi algorithm (LVA) for decoding tail biting convolutional codes (TBCCs) has lower complexity than a solution of running the LVA algorithm for all states. In one aspect, a low complexity LVA-TBCC process includes finding a list of states from a single Viterbi algorithm and finding a list of potential codewords for each state in the state list using the LVA. A cyclic redundancy check may prune out false solutions. The disclosed method may be applied to many communication systems to improve error performance similar to LTE downlink PBCH decoding enhancements.

Abstract: Techniques for sending signaling information using hierarchical coding are described. With hierarchical coding, individual messages for users are encoded using multiple interconnected encoders such that (1) the message for each user is sent at a data rate suitable for that user and (2) a single multicast message is generated for the messages for all users. A base station determines data rates supported by the users and the code rates to achieve these data rates. Each data rate is determined by one or more code rates. Signaling information for the users is mapped to data blocks to be sent at different data rates. Each data block is then encoded in accordance with the code rate(s) associated with the data rate for that data block. A final coded block is generated for all users and transmitted. Each user performs the complementary decoding to recover the message sent to that user.

Abstract: Monitors, architectures, systems and methods for determining one or more quality characteristics of a storage channel. The monitor generally includes an iterative decoder configured to decode data from the storage channel and generate information relating to a quality metric of the storage channel and/or the iterative decoder, a memory configured to store a threshold value for the quality metric, and a comparator configured to compare the threshold value with a measured value of the quality metric. The monitor enables accurate determination of storage channel quality without use of conventional Reed-Solomon metrics.

Abstract: The claimed subject matter relates to encoding and decoding information in a wireless communication system using soft-demodulation and interleaving of concatenated code received in a strip channel. A set of symbols is received containing a plurality of information bits, dividing the received set of symbols into a plurality of subsets of symbols, each subset corresponding to the input of an inner code demodulation selecting a set of initial a priori values of the inner code demodulation for each subset of symbols, and demodulating each subset of symbols, using the initial a priori values of the subset of symbols and an inner code generator matrix, to generate a plurality of first soft information values as the output of the inner code demodulation.

Abstract: In a symbol mapping method, transmission data is encoded to generate information bits and redundancy bits. An average LLR value of bits on which the information bits are mapped is different from an average LLR value of bits on which the redundancy bits are mapped.

Abstract: When coding user data, it may be desirable to mark user data as invalid. This may arise, by way of example, in applications in which a stored data item needs to be updated by virtue of an updated data item additionally being stored and the old stored data item being marked as invalid. In order to mark the invalidity of a stored data item by means of the value of the data item and to be able to apply an error-recognizing or error-correcting coding dependably, the user data are extended by supplementary data and the coding is applied to the extended user data.

Abstract: A method and apparatus for generating soft-decision output values for a set of transmitted spatial streams in a multiple-input multiple-output (MIMO) communication system are described. The apparatus includes a processor and memory with executable instructions. A plurality of constellation points for respective transmitted spatial streams are looped over to estimate values for other transmitted streams based at least in part on Reduced List Detection (RLD). The plurality of constellation points is a subset of all possible constellation points determined around a spatial stream where more constellation points are assigned to spatial streams with a weaker signal strength than for spatial streams with a stronger signal strength. A set of distance metrics as values of the plurality of constellation points for the respective transmitted spatial streams are determined. Soft-decision outputs for the respective transmitted streams based at least in part on the set of distance metrics are generated.

Abstract: An error correction decoder (101) counts the number of times of iterative decoding executed in the process of a predetermined error correcting operation, and outputs the iterative decoding count to an averaging circuit (102). The averaging circuit (102) calculates the average value of the iterative decoding counts input from the error correction decoder (101), and outputs the calculated average value of the iterative decoding counts to a comparator (103). The comparator (103) determines whether the iterative decoding count average value is larger than a predetermined threshold value. When determining that the average value is larger than the predetermined threshold value, the comparator (103) determines that a channel switching condition is met, and outputs a channel switching signal to a channel switching circuit (405).

Abstract: In an electronic apparatus, a soft decision likelihood value is generated and subject to a decoding process supporting a convolutional code; and a data series is interleaved, subjected to an error correction process, and decoded data is generated. A detecting unit, based on information concerning the position of a symbol for which an error has been corrected successfully by the error correction process, estimates whether an error occurs in a symbol for which the error correction process failed and detects the position of a symbol estimated to have an error. A setting unit sets based on the decoded data and information concerning the position of the symbol estimated to have an error, a correction value of the soft decision likelihood value. The electronic device interleaves the order of a correction value series of the soft decision likelihood value and feeds the resulting correction value series back to the decoding process.

Abstract: Techniques are provided for transmitting and receiving a mother code in an incremental redundancy hybrid automatic repeat-request protocol. Each bit position of the mother code may be mapped to an output symbol, and each output symbol may be mapped to an antenna for transmission. One or more transmissions of symbols contained in the output symbols may be performed, where each transmission may include puncturing the mother code by selecting one or more symbols from the of output symbols, and transmitting each symbol in the one or more symbols on an antenna corresponding to that symbol. The mother code may be decoded, in part, by determining combinable bits contained within a set of received symbols, and computing one or more log-likelihood ratio values corresponding to each symbol in the set of received symbols.

Abstract: In a multicarrier wireless communication system adopting forward error correction codes, a reception method adapted to a receiver 1 receiving wireless signals is constituted of an interference band detection process for selecting a sub-carrier having low reliability among a plurality of sub-carriers of desired waves as a specific sub-carrier, a weight coefficient generation process for generating weight coefficients for reducing reliability in sub-carriers with respect to the selected specific sub-carrier, a demodulation process for demodulating received wireless signals of sub-carriers, a weighted calculation process for performing weighted calculation applying weight coefficients to demodulated values of sub-carriers of wireless signals, and a decoding process for performing a decoding process for error correction on values calculated of sub-carriers.

Abstract: The device is used for decoding convolution-encoded reception symbols. In this context, transmission data are modulated with a modulation scheme to form symbols, which are encoded with a transmission filter to form convolution-encoded transmission symbols. A convolution-encoded transmission symbol contains components of several symbols arranged in time succession. These transmission symbols are transmitted via a transmission channel and received as reception symbols. The Viterbi decoder decodes the reception symbols by use of a modified Viterbi algorithm. Before running through the Viterbi decoder, the reception symbols are processed by a state-reduction device, which determines additional items of information relating to possible consequential states of the decoding independently of the decoding through the Viterbi decoder in every state of the decoding. The state-reduction device uses the additional items of information to restrict the decoding through the Viterbi decoder to given consequential states.

Abstract: A method of detecting received data in a communication system includes the steps of: performing a QR decomposition on a received input vector as a function of one or more characteristics of a communication channel over which the input vector was transmitted; generating a subset of best symbol candidates from a symbol constellation by comparing an input sample (corresponding to an element of the input vector) with one or more prescribed thresholds; identifying at least one symbol satisfying prescribed minimum Euclidian distance criteria among multiple ambiguity symbols in the subset of best symbol candidates; and generating a subset of best symbols including a prescribed number of symbols from the symbol constellation determined to be closest to the input sample. The subset of best symbols is used in a subsequent iteration of the steps of generating the subset of best symbol candidates and identifying at least one symbol satisfying the prescribed minimum Euclidian distance criteria.

Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.

Abstract: Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses this dynamic characterization of the channel fidelity to adapt the receiver processing and to affect an improvement in the performance of the receiver. For example, in this embodiment, the method increases the accuracy of the estimation of the transmitted information, or similarly, increases the probability of making the correct estimates of the transmitted information, even in the presence of temporary severe levels of impairment. The channel fidelity history may also be stored and catalogued for use in, for example, future optimization of the transmit waveform.

Abstract: A controller for a communications device, comprising: a receiver arranged for receiving a first data block and a second data block, each data block comprising a plurality of analogue signals; a digitizer arranged for converting each analogue signal into a digital value and marking each digital value as saturated when the digital value exceeds a digital range; and a processor arranged for modifying at least one digital value of the first block by combination with a corresponding digital value of the second block except where the digital value of the first block is marked as saturated and marking each modified value as saturated when the modified value is outside a defined range.

Abstract: A defect detection and correction system includes a decoder module configured to decode data received from a data storage device and output the data and a plurality of confidence indicators associated with respective bits of the data. A digital defect detection module is configured to compare each of the confidence indicators in a window of W bits of the data to a confidence threshold, identify a number of bits in the window of W bits as defective based on the comparison, mark all of the bits in the window of W bits as defective if the number of bits is greater than a bit threshold, and generate a defect indicator identifying the window of W bits as defective.

Abstract: A method of estimating signal-to-noise ratio in a Viterbi decoder comprising: setting a threshold SNR value; determining a dependence on SNR of the average decoding path length; filling branch metrics matrix, minimal path metrics matrix, path metrics matrix and paths matrix with initial values; receiving packets from a communication channel; calculating the matrices that contains paths stored during operation of Viterbi algorithm in its rows, and a minimal path metrics matrix, including calculating an estimate of a decoding path length, where all the paths converge, based on the paths matrix; calculating current SNR estimate using an estimate of a decoding path length, based on results of previous steps; setting a decoder control signal to an active state if the current estimated SNR does not exceed the threshold, and to an inactive state otherwise; if the decoder control signal is in active state, the branch metrics matrix, the minimal path metrics matrix, the paths metrics matrix and the paths matrix are fi

Abstract: Methods, apparatuses, systems, and architectures for providing fast, independent, and reliable retrieval of system data (e.g., metadata) from a storage system, which enables minimal degradation in the reliability of user data. Methods generally include encoding the system data at least twice, at least once independently and at least once jointly along with user data. Methods can also include decoding the system data first, and upon a decoding failure, jointly decoding the system data and the user data.

Abstract: In a communication device that is operative to perform decoding, a log-likelihood ratio (LLR) circuitry operates to calculate LLRs corresponding to every bit location within a received bit sequence. This received bit sequence may include a header and a data portion (both of which may be included within a frame that also includes a preamble). The header is composed of information bits, a duplicate of those information bits (such as may be generated in accordance with repetition encoding), and redundancy bits. The header includes information corresponding to frame or data including frame length, a code type by which the data are encoded, a code rate by which the data are encoded, and a modulation by which symbols of the data are modulated. Once the header has been decoded, then the data corresponding thereto is decoded by a block decoder circuitry to make estimates of that data.

Abstract: A method for recovering transmission errors, comprising: receiving a data packet comprising an error detection code associated to data contained in the packet, wherein the data associated to the error detection code comprises primary data and secondary data, checking the error detection code of the received packet to detect an erroneous state of the associated data, when the erroneous state is detected, determining a finite set of candidate values for the primary data and, for each values of the set: determining a marginal likelihood of the candidate value as a function of the error detection code of the received packet, determining a first correlation between the primary data of the received packet and the candidate value, and selecting a corrected value for the primary data among the set of candidate values as a function of said marginal likelihoods and said first correlations.