Abstract: A receiver includes a seed recovery module and a pseudo-random binary sequence generator. The seed recovery module is configured to receive a pseudo-random binary sequence and a signal including a seed value, recover the seed value from the signal using the pseudo-random binary sequence, and determine a likelihood that a bit of the seed value was recovered accurately. The pseudo-random binary sequence generator is configured to generate the pseudo-random binary sequence, and adjust the pseudo-random binary sequence based on the likelihood until the likelihood is greater than a threshold.

Abstract: An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) coded message. The coded message is modulated according to a high order modulation scheme that has a signal constellation representing more than two symbols per signaling point—e.g., 8-PSK (Phase Shift Keying) and 16-QAM (Quadrature Amplitude Modulation). The system includes a transmitter configured to propagate the modulated signal over the satellite. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates.

Abstract: Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing.

Abstract: A soft symbol decoder for use in a multiple input multiple output (MIMO) and OFDM (orthogonal frequency division multiplexing) system. The decoder generates soft symbol values for a digital signal that represents a number of source bits. The source bits are transmitted as symbols in corresponding to points in a signaling constellation. Soft metrics are determined by searching for all possible multi-dimensional symbols that could have been transmitted. The method includes transmitting a sample of the multi-dimensional symbol using K transmit antennas. The multi-dimensional symbol is represent-able as a complex, K-dimensional vector x. Each vector component of vector x represents a signal transmitted with one of the K transmit antennas. After transmission through a communication channel, a sample corresponding to the transmitted sample is received. The received sample is represented by a complex, N-dimensional vector y, where N is the number of receive antennas in the MIMO system.

Abstract: A reception apparatus including: a detection unit detecting extrinsic information based on a tentative symbol decision signal, a channel estimation signal, a noise variance estimation signal, and a received signal that are obtained from a previous iteration process; a Cyclic Redundancy Check (CRC) aided channel decoding unit outputting an interleaved bit or a posteriori information thereof based on the extrinsic information; a tentative symbol decision unit determining a tentative transmission symbol based on an output of the CRC aided channel decoding unit; a channel estimation unit estimating a channel based on an output of the tentative symbol decision unit; and a noise variance estimation unit estimating a noise variance based on the output of the tentative symbol decision unit and an output of the channel estimation unit is provided.

Abstract: A method for communication includes receiving a communication signal conveying multiple encoded bits of an Error Correction Code (ECC). Respective N-bit soft decoding metrics are computed with respect to the bits of the ECC. A scaling factor is computed based on at least one characteristic of the N-bit soft decoding metrics and on at least one property of the received communication signal. The N-bit soft decoding metrics are scaled by the scaling factor. The scaled N-bit soft decoding metrics are quantized to produce respective K-bit metrics, K<N. The ECC is decoded using the scaled and quantized soft decoding metrics.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. Anticipatory address generation is employed using an index function , that is based on an address mapping , which corresponds to an interleave inverse order of decoding processing (??1). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index function , that is based on an mapping and the interleave (?) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index function also allows for the interleave (?) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.

Abstract: A system and method is provided for decoding a set of bits using a plurality of hypotheses, for example, each independently tested on-the-fly. Initial bit states and associated reliability metrics may be received for the set of bits. A current hypothesis may be decoded for correcting the set of bits, wherein the current hypothesis defines different bit states and associated reliability metrics for the set of bits. If decoding the current hypothesis is not successful, a subsequently ordered hypothesis may be decoded, wherein the hypotheses are ordered such that their associated reliability metric is a monotonically non-decreasing sequence. Decoding may proceed iteratively until the current hypothesis is successful.

Abstract: Apparatus and methods for generating checksums may process two or more segments of a message in parallel, and may be used with a communications channel having time slots. An apparatus may include a cumulative checksum generator to generate a cumulative checksum for a message, a partial checksum generator to generate one or more partial checksums from one or more respective message segments, and a speculative checksum generator to generate a speculative checksum for each of one or more time slots. In one aspect, a partial checksum corresponding with an initial segment of the message may be generated from at least an initialization vector. A speculative checksum selector may select a first speculative checksum for use in determining whether the message was transmitted without error. The generating of partial and speculative checksums results in a maximally pipe-lined architecture with speed limited only by a minimal cumulative CRC calculation that is fundamentally unavoidable.

Abstract: A method for a decoding device to decode a codeword matrix of a product code includes: generating a first extended parity check matrix for a vertical code; decoding a horizontal codeword of a plurality of rows in the codeword matrix to thus perform a first decoding process; generating a second extended parity check matrix by removing a column corresponding to a row of the first decoding-succeeded horizontal codeword from the first extended parity check matrix; and decoding the first decoding-failed horizontal codeword by using the second extended parity check matrix to thus perform a second decoding process. Therefore, the simple and reliable product code decoding method is provided.

Abstract: A filtering method, system, and equipment applied in digital communication technologies are disclosed in the embodiments of the present invention. The filtering method of the present embodiments includes: acquiring filtering coefficients of a part of all subcarriers according to data transmission errors; acquiring filtering coefficients of remaining subcarriers through an interpolation algorithm according to the filtering coefficients of the part of subcarriers; and finally, filtering the data corresponding to the multiple subcarriers according to the filtering coefficients of the part of subcarriers and the filtering coefficients of the remaining subcarriers. The part of subcarriers may be selected at a regular interval, or may be subcarriers which are located at a motion value away from the part of subcarriers selected in the previous update of the filtering coefficients. The method of the present embodiments reduces the amount of operation and hardware expenditure, and saves the cost.

Abstract: According to an example embodiment, a method of generating a soft decision value using an Analog-to-Digital Converter (ADC) having a given resolution may include receiving metric values calculated based on levels of a transmission signal and output levels of the ADC. Metric values corresponding to a level of a received signal may be selected from among the received metric values. A first maximum metric value may be detected from among the selected metric values when a transmission bit is a first level, and a second maximum metric value may be detected from among the selected metric values when the transmission bit is a second level. The soft decision value may be generated based on a difference between the first maximum metric value and the second maximum metric value.

Abstract: A method and apparatus for performing calculations relating to the derivation of log-likelihood ratio (LLR) is provided. Coefficients in the use of deriving LLRs are calculated the calculation being applicable to any one of a plurality of constellation diagrams (PAM, QAM, PSK). The coefficients may be stored in a table of coefficients, the table corresponding to a particular constellation diagram and modulation scheme. A number of tables may be stored, each table corresponding to a particular modulation scheme. The coefficients are related to a symbol estimated to be closest to the received sample and the closest symbol to the estimated symbol having a complementary value for a bit for which the LLR is to be calculated. Certain coefficients or parts of coefficients may be omitted where the corresponding constellation diagram has symmetries.

Abstract: Embodiments of the present invention provide a read channel including a front end to receive an optical image, convert the optical image into multi-bit soft information, and to serially transmit the multi-bit soft information to other components of the read channel. Other embodiments may be described and claimed.

Abstract: A radio communication apparatus includes a receiving unit configured to receive signals, an obtaining unit configured to obtain a reference amplitude that depends on a modulation scheme for a received signal received by the receiving unit, and on amplitude fluctuations of the received signal in a propagation path, a demodulating unit configured to demodulate the received signal to obtain an in-phase component and a quadrature component of each received symbol included in the received signal, a calculating unit configured to calculate a likelihood ratio for each of bits mapped to each received symbol using the reference amplitude and the in-phase or quadrature component, and a decoding unit configured to perform error correction decoding on the received signal using the calculated likelihood ratios.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data transfer system is disclosed that includes a data detector, a defect detector and a gating circuit. The data detector provides a soft output, and the defect detector is operable to receive the soft output and the data signal, and to assert a defect indication based at least in part on the soft output and the data signal. The gating circuit is operable to modify the soft output of the detector whenever the defect indication is asserted.

Abstract: A decoding device allowing a high-speed decoding operation. In a decoding section (215), if a degree of a check equation by a check matrix is D and the relationship between the check equation of the j+first row of the check matrix and the cheek equation of the jth row is shifted by n-bit, row processing operation sections (405#1 to 405#3) and column processing operation sections (410#1 to 410#3) perform the operation of a protograph in which the columns of the check matrix are delimited for each “(D+1)×N (N: natural number),” and the rows of the check matrix are delimited for each “(D+1)×N/n,” and formed as the processing unit of the row processing operation and column processing operation.

Abstract: An improved mapping policy, signal mapper, transmitter, receiver, and communication system are introduced. The improved signal mapping policy alternates between standard and inverted bit mapping functions at selected phase states to reduce the error coefficient of MSK and other types of CPFSK signals. The proposed policy can more generally be applied to other types of signals with memory as well. Simulations show that the mapping policy can significantly improve performance particularly at lower to moderate SNR values.

Abstract: Various embodiments of the present invention provide systems and methods for selecting between pre-coding and non-pre-coding. As an example, a data processing circuit is disclosed that includes: a first data detector circuit, a second data detector circuit, a first comparator circuit, a second comparator circuit, and a pre-code selection circuit. The first data detector circuit is selectably configurable to operate in a pre-coded state, and operable to apply a data detection algorithm on a data input to yield a first detected output. The second data detector circuit operable to apply the data detection algorithm to the data input to yield a second detected output without compensating for pre-coding. The first comparator circuit operable to compare the first detected output against a known input to yield a first comparison value, and the second comparator circuit operable to compare the second detected output against the known input to yield a second comparison value.

Abstract: An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding system. The data decoding system includes a data decoder circuit and a simplified maximum likelihood value modification circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a first decoded output and an indication of at least one point of failure of the first decoded output. The simplified maximum likelihood value modification circuit is operable to identify a symbol of the first decoded output associated with the point of failure, and to modify a subset of values associated with the identified symbol to yield a modified decoded output.

Abstract: A network controller receives data substantially simultaneously from multiple client nodes. The network controller assigns to each client node one or more sub-carriers of an orthogonal frequency-division multiplexing access frequency spectrum. The client nodes transmit substantially simultaneously M LDPC codewords that are encoded in a parity check matrix so that the number of rows m? depend on the code rate and are mapped on its assigned sub-carriers. The network controller computes a bit log-likelihood ratio for each received bit of the codewords and arranges the bit LLR by codeword to align with an equivalent parity check matrix. The network controller decodes the codewords with the equivalent parity check matrix.

Abstract: Two decoding algorithms are introduced for the decoding of multi-level coded modulation and other types of coded modulation involving component codes and interleaving operations. An improved hard iterative decoding (IHID) algorithm is presented that improves upon a hard iteration decoding technique by adding a stopping criterion. Also, a list Viterbi hard iteration decoding (LV-IHID) algorithm is presented that employs list decoding in conjunction with the IHID algorithm. Both of these decoding algorithms improve upon conventional multi-stage decoding by reducing the effective error multiplicity that is observed at the lowest coding level. It is demonstrated that the LV-IHID algorithm performs close to soft iterative decoding. The computational and delay complexity of the proposed decoding algorithms compare favorably with soft iterative decoding strategies. Also, a novel labeling strategy for MLC design is presented.

Abstract: Methods, software, circuits and systems involving a low complexity, tailbiting decoder. In various embodiments, the method relates to concatenating an initial and/or terminal subblock of the serial data block and outputting decoded data from an internal block of the modified data block. The circuitry generally includes a buffer, logic configured to concatenate an initial and/or terminal subblock to the serial data block, and a decoder configured to decode the data block, estimate starting and ending states for the data block, and output an internal portion of the serial data block and the one or more sequences as decoded data. The invention advantageously reduces the complexity of a suboptimal convolutional decoder, ensures smooth transitions at the beginning and end of the serial data block during decoding, and increases the reliability of the starting and ending states, without adding overhead to the transmitted data block.

Abstract: According to one embodiment, a data detection system includes a coefficient-and-variance engine for selecting which infinite impulse response (IIR) filter and prediction error variance to process and store at any time, and a maximum-likelihood sequence detector. The coefficient-and-variance engine comprises a filter bank storing a plurality of IIR filters that represent a plurality of data-dependent noise whitening or noise prediction filters; a least-mean square (LMS) engine for adapting each IIR filter to actual noise conditions: a variance hank storing a plurality of prediction error variance values; and a data-dependent prediction error variance computation unit which updates the plurality of prediction error variance values. The maximum-likelihood sequence detector includes a metric computation unit that employs the plurality of IIR filters in the filter bank and the plurality of prediction error variances in the variance bank to adaptively compute detector branch metrics.

Abstract: Low latency and computationally efficient techniques may be employed to account for errors in data such as low bit-width, oversampled data. In some aspects these techniques may be employed to mitigate audio artifacts associated with sigma-delta modulated audio data. In some aspects an error may be detected in a set of encoded data based on an outcome of a channel decoding process. Upon determining that a set of data may contain at least one error, the set of data may be replaced with another set of data that is based on one or more neighboring data sets. For example, in some aspects a set of data including at least one bit in error may be replaced with data that is generated by applying a cross-fading operation to neighboring data sets. In some aspects a given data bit may be flipped as a result of a linear prediction operation that is applied to PCM equivalent data that is associated with the given data bit and its neighboring data bits.

Abstract: A channel decoder including an amplifier configured to amplify a signal; a first summer configured to generate an output signal based on the signal amplified by the amplifier; and a Viterbi detector module configured to, based on the output signal, generate a first estimate signal and a second estimate signal, wherein the first estimate signal and the second estimate signal respectively indicate an estimate of data in the signal. The channel decoder further includes a second summer configured to generate a first error signal indicating a first gradient based on the first estimate signal; and a third summer configured to generate a second error signal indicating a second error gradient based on the second estimate signal. The first summer is configured to generate the output signal based on (i) the first error signal and (ii) the second error signal.

Abstract: The error correction capability for wireless communication carried out involving propagation path fluctuation in time and frequency selectivity can be improved. A soft decision likelihood value inputted to an error correction decoder is multiplied by a weight determined according to the distance between the data symbol and pilot symbol corresponding to the soft decision likelihood value. Namely, the soft decision bit likelihood value corresponding to the data symbol is weighted according to the distances in time or frequency between the pilot symbol and data symbol. The weight is made smaller when the distance in time or frequency is larger.

Abstract: Techniques for generating soft values for parity bits in a convolutional decoding process are disclosed. An exemplary method comprises, for each of at least one iteration in at least one soft-input soft-output decoder, calculating intermediate probability values for each possible transition between a first plurality of candidate decoder states at a first time and a second plurality of candidate decoder states at a second time. Two or more partial sums are then computed from the intermediate probability values, wherein the partial sums correspond to possible combinations of two or more systematic bits, two or more parity bits, or at least one systematic bit and at least one parity bit. Soft values, such as log-likelihood values, are then estimated for each of at least one systematic bit and at least one parity bit of the received communications data corresponding to the interval between the first and second times, based on the partial sums.

Abstract: Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.

Abstract: Schemes for creating a surplus of decoding iterations in a decoder are described. The surplus can be used to augment the decoding of signal blocks. The option of using an idle decoder to decode blocks marked as unproductive for decoding is also described.

Abstract: Demodulation and/or demapping of a signal (e.g., based on a constellation whose points have a corresponding mapping with associated labels) is performed such that each dimension is processed separately without accounting for influences from the other dimension. For example, the demapping process operates on each respective dimension separately and independently. In some instances, the processing operates iteratively, in that, information identified from processing one of the dimensions is employed in directing the processing in another of the dimensions. Such operation may be performed iteratively by updating/modified information associated with one or more of the dimensions as well. Moreover, decoding may operate in accordance with iterative demapping (e.g., error correction code (ECC) and/or forward error correction (FEC) code by which information bits are encoded) to make estimates of bits within a signal sequence, and those estimates may be used in a subsequent iteration of demapping.

Abstract: Provided is a method and apparatus for receiving a signal for a MIMO system. The receiving apparatus includes: a QR decomposer for calculating a unitary matrix Q, an upper triangle matrix R, and a vector size for a received signal; a multiple dimension detector for calculating a first LLR for an output of the QR decomposer through multiple dimension detection; an inverse matrix and weight calculator for calculating an inverse matrix for the upper triangle matrix R and a weight; an interference remover for regenerating a symbol for a demodulated data stream using the fist LLR and removing interference from an output vector of the QR decomposer using the regenerated symbol; and a weight zero forcing unit for performing zero forcing on the interference removed output vector from the interference remover using the inverse matrix of the upper triangle matrix R and the weight and calculating a second LLR.

Abstract: A receiver for a mobile communication device comprises an primary detector for generating an initial sequence estimate comprising a plurality of initial symbol estimates from a received symbol sequence corrupted by intersymbol interference, and a secondary detector to receive said initial sequence estimate and to output a final sequence estimate comprising a plurality of final symbol estimates. The secondary detector comprises a sequence generator configured to generate one or more revised sequence estimates by replacing at least one initial symbol estimate in said initial sequence estimate with a corresponding nearest neighbor symbol in each of said revised symbol estimates; an error calculator to compute error metrics for said revised sequence estimates; and a selection circuit to compare error metrics for said initial and revised sequence estimates and to output one of said initial or revised sequence estimates as said final sequence estimate based on said error metrics.

Abstract: Circuitry and methods can be provided to correct errors in decision bits. A plurality of error event syndromes can be computed for a first plurality of error events. For each of a plurality of error event syndromes, two best error events can be selected. A cross-syndrome second best error event can be selected from among the first plurality of error events. A global second best error event can be selected from among the cross-syndrome second best error event and the second best per-syndrome error events. A second plurality of error events can be selected from among the global second best error event and the best per-syndrome error events. The second plurality of error events can be used for data post-processing.

Abstract: A device and method of determining candidates to decode by receiving a message, selecting m, identifying m voltages in message near zero volts, generating binary version of message, generating candidates that are variations of the binary message by varying the m positions, multiplying a modified binary message by the parity check matrix of the message, generating a matrix of the rows of the parity check matrix corresponding to the m positions, determining a rank v of the matrix, eliminating rows that are not linearly independent, determining if the sixth step result is in a span of the ninth step result, if so then there are 2m-1-2m-v(m?1) candidates, where the candidates can multiply the seventh step result to get the sixth step result and candidates with odd weights more than one Hamming distance from the candidates, otherwise there are 2m-1 candidates having odd weight.

Abstract: This invention relates to methods for obtaining a bin number of path metrics. When performing such methods, a histogram is provided, which comprises a bin number of values, a maximum value and a tail region left or right of the maximum value. A bin number of path metrics is obtained from said values. According to an embodiment a local extremum is removed from said tail region. According to another embodiment the tail region is forced to be convex. According to a further embodiment a maximum metric difference between neighboring metrics is ensured.

Abstract: A chunk of branch metric computation bits is generated including bits that correspond to transition bits of a possible chunk of transition bits that could have been generated by a state transition of a convolutional encoder of a transmitter. The bits of the chunk of branch metric computation bits are scrambled. A branch metric for the received chunk of soft scrambled code bits is calculated as a function of the scrambled bits of the chunk of branch metric computation bits and the soft scrambled code bits of the received chunk of soft scrambled code bits. The branch metric is indicative of the probability that the received chunk of soft scrambled code bits was originally generated by the convolutional encoder as the chunk of transition bits corresponding to the generated chunk of branch metric computation bits.

Abstract: An encoder and decoder using LDPC-CC (Low Density Parity Check-Convolutional Codes) is disclosed. The encoder exhibits encoding rates realized with a small circuit-scale and a high data reception quality. In the encoder (200), an encoding rate setting unit (250) sets an encoding rate (s?1)/s (s=z), and an information creating unit (210) sets information including from information Xs,i to information Xz?1,i to zero. A first information computing unit (220-1) receives information X1,i at time point i to compute the X1(D) term of formula (1). A second information computing unit (220-2) receives information X2,i at time point i to compute the X2(D) term of formula (1). A third information computing unit (220-3) receives information X3,i at time point i to compute the X3(D) term of formula (1). A parity computing unit (230) receives parity Pi?1 at time point i?1 to compute the P(D) of formula (1). The exclusive OR of the results of the computation is obtained as parity Pi at time i. Ax.

Abstract: A decoding method and apparatus of a retransmission communication system are provided. In the decoding method and apparatus, weights are applied to error data and retransmitted data, and the resulting error data and the resulting retransmitted data are chase-combined. Therefore, it is possible to reduce the coding rate of combined data and enhance the reliability of decoding.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.

Abstract: A method and apparatus for decoding encoded data bits of a wireless communication transmission are provided. A set of a-priori bit values corresponding to known bit values of the encoded data bits may be generated. Decoding paths that correspond to decoded data bits that are inconsistent with the a-priori bit values may be removed from the possible decoding paths to consider, and decoding the encoded data bits by selecting a decoding path from remaining decoding paths of the possible decoding paths that were not removed. A-priori bit values may be extracted from various messages, such as DL-MAP, UL-MAP, RNG-REQ, and BW-REQ messages.

Abstract: Aspects of a method and system for UMTS HSDPA Shared Control Channel processing may include calculating at a receiver, for each one of a plurality of control channels, a quality metric based at least one Viterbi Decoder state metric. A control channel may be selected on the basis of the quality metrics, where the quality metric is selected that provides maximum confidence. The selected control channel may be chosen if its corresponding 3GPP metric is greater than a specified threshold, where the threshold is a design parameter. A validity of a selected control channel may be determined based on consistency and a CRC, where the CRC may be derived from decoding a sub-frame. The calculating and selecting may be done for a first slot of a sub-frame for High-Speed Shared Control Channels.

Abstract: A receiving apparatus and method of a Maximum Likelihood (ML) scheme in a Single-Carrier (SC) system are provided. The apparatus includes at least two antennas, at least two Orthogonal Frequency Division Multiplexing (OFDM) demodulators, at least two subcarrier mappers, at least two OFDM modulators, and a detector. The antennas receive signals. The OFDM demodulators convert the signals into frequency domain signals. The subcarrier mappers confirm signals mapped to frequency domain subcarriers. The OFDM modulators convert the signals into time domain signals. The detector constructs at least one set for candidate transmission symbols and detects receive signals through ML detection using the set.

Abstract: An apparatus, and an associated method, for correcting errors in decoded data, decoded by a convolutional decoder, such as an SOVA (Soft Output Viterbi Algorithm). A CRC check is performed upon the decoded data. If the CRC check fails, a conclusion is made that the decoded data contains errors. Portions of the decoded data indicated to exhibit low levels of reliability are toggled with values of most-likely error events. A corrected sequence of the decoded data is formed that corrects for the errors in the decoded data.

Abstract: Systems and methods enabling ultra-high-speed optical transport The systems and methods include receiving a modulated, encoded input stream. Channel impairments are removed using MAP equalization. Symbols are detected in the input stream to produce a stream of encoded data. The stream of encoded data is decoded with one or more low density parity check (LDPC) decoders that use an LDPC code built by modified progressive edge growth. The LDPC code is built by iteratively expanding trees from each variable node until all check nodes are connected to the respective variable node, while controlling both the local girth and the global girth of the code.

Abstract: The invention which relates to a method and to an arrangement for generating soft bit information in a receiver of a multiple antenna system is based on the object of reducing the calculation complexity for generating the soft bit information.

Abstract: To provide a receiving device and a receiving method which achieve iterative decoding regarding concatenated codes containing a convolutional code while suppressing increase in circuit scale, a decoder and an error correcting part iteratively perform decoding and error correction corresponding to a convolutional code on soft-decision inputs corresponding to the received signal sequence. Depending on whether a decoding result matches error corrected decoded data obtained in previous processing or not, penalties are calculated corresponding to branches transiting with the respective decoded results, and a branch metric is calculated by reflecting the calculated penalties as to decrease likelihood ratio of each of the branches to which the penalties are to be added. The obtained branch metric is input to a decoder, thereby reflecting the penalty corresponding to the decoding result.