Abstract: The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

Abstract: A method for near maximum-likelihood sequential decoding is provided. According to the method, paths unlikely to become the maximum-likely path are deleted during decoding through a level threshold to reduce decoding complexity. Besides, the method performs maximum-likelihood decoding through sequential decoding by adopting a metric, so that a received signal does not have to go through a hard decision procedure.

Abstract: Embodiments of the present invention provide methods and apparatus for wireless communication using codeword with high-rate codes. Other embodiments may be described and claimed.

Abstract: An apparatus is provided for decoding a Low-Density Parity Check (LDPC) code in a communication system. In the LDPC decoding apparatus, an edge memory stores a message delivered through an edge between a variable node and a check node. A node memory stores a node value. A node processor performs a node processing operation using information stored in at least one of the node memory and the edge memory, stores a check node value generated by performing the node processing operation in the node memory, and stores a message generated by performing the node processing operation in the edge memory. A switch switches outputs of the node memory and the node processor through a permutation operation. A parity check verifier parity-checks an output from the node memory. A controller provides a control signal for controlling the node processor.

Abstract: Methods and apparatus to compensate for I/Q mismatch in quadrature receivers are disclosed. An example apparatus disclosed herein comprises a correction engine using first filter coefficients to compensate for I/Q mismatch present in a received quadrature signal; an adaptation engine to adapt second filter coefficients based on I/Q mismatch present in the received quadrature signal; and coefficient controller to occasionally adjust the first filter coefficients based on the second filter coefficients.

Abstract: A method of broadcasting an AM compatible digital audio broadcasting signal includes: producing an analog modulated carrier signal centrally positioned in a radio channel, wherein the analog modulated carrier signal is modulated by an analog signal, producing a plurality of digitally modulated subcarrier signals in the radio channel, wherein the digitally modulated subcarrier signals are modulated using complementary pattern-mapped trellis code modulation (CPTCM) including a code mapped to overlapping partitions including an upper main partition, a lower main partition, an upper backup partition and a lower backup partition, and a non-overlapping tertiary partition, and transmitting the analog modulated carrier signal and the plurality of digitally modulated subcarrier signals. Transmitters that broadcast the signal and receivers that receive the signal, and the reception method are also included.

Abstract: Systems and techniques to interpret signals on a channel. In general, in one implementation, the technique includes: obtaining an output signal sequence from a partial response channel, determining an input sequence of the partial response channel by maximizing a correlation metric of an estimated output sequence with the obtained output sequence, the estimated output sequence being estimated based on the partial response channel, and providing an output corresponding to the determined input sequence. An apparatus can include a branch metric generator that generates branch metrics comprising a correlation of obtained output sequences and estimated output sequences for a partial response channel.

Abstract: Provided is a turbo decoder with a variable scaling factor. The decoding convergence degree of the turbo decoder is evaluated using a sign difference ratio (SDR) value, the iterative-decoding number is limited, a variable scaling factor is calculated and applied in each decoding convergence area based on the SDR value, and the average number of decoding iterations is reduced.

Abstract: An add-compare-select (ACS) unit generates first path metrics having a first bit-pair and a most significant bit-pair (MSB) each including a high bit and a low bit. A first ACS circuit produces the first bit-pair and a first carry. A limiting circuit generates the MSB based on the first carry, and limits the MSB to a first predetermined value. A MSB maximum select (MS) unit receives an MSB of second path metrics from another ACS unit, and compares the MSBs of the first and the second path metrics to determine MSB decision signals based on maximum likelihood selection. A MSB storage unit stores the MSB of the first path metrics. A reset unit resets the high bit of the MSB of the first path metrics to a second predetermined value when the high bits of the MSBs of the first and the second path metrics reach the first predetermined value.

Abstract: A path metric computing method applied in a high-speed Viterbi detector and related apparatus thereof are disclosed. The path metric computing apparatus includes a comparator for generating a control signal according a plurality of previous path metrics, a combining circuit for generating a plurality of first output values according to the previous path metrics and branch costs of a plurality of branches of a current state, and a multiplexer, electrically connected to the comparator and the combining circuit, for determining a first path metric of the current state according to the control signal and the output values.

Abstract: Device, system, and method of multi-level feedback. In some embodiments, an apparatus includes: an estimator to estimate a likelihood of correctly decoding an incoming encoded Hybrid Automatic Repeat Request packet of an incoming wireless communication signal by one or more decoders of the apparatus; and a transmitter to transmit a multiple-bit representation of the likelihood of correctly decoding the incoming encoded Hybrid Automatic Repeat Request to a device that transmitted the incoming encoded Hybrid Automatic Repeat Request packet.

Abstract: An evaluation value calculating apparatus includes the following elements. A difference metric selecting unit selects a difference metric for a specific recorded sequence in recorded sequences obtained in a maximum likelihood decoding process when information expressed with marks and spaces on a recording medium is played back, the difference metric being obtained in the maximum likelihood decoding process. A difference metric error value calculating unit determines a difference metric error value for the selected difference metric using a calculation method that is selected according to an edge shift direction of each of the marks on a time axis, the difference metric error value representing an error from an ideal difference metric and the edge shift direction on the time axis. A statistical processing unit performs statistical processing on the determined difference metric error value on the basis of each of states of path meeting points to generate an evaluation value.

Abstract: One embodiment of the invention features a programmable gain stage in analog update circuitry to overcome the accuracy limitation of the circuit gain and the maintenance of small finite number of possible sequence estimates.

Abstract: There is provided an addressing architecture for parallel processing of recursive data. A basic idea is to store a calculated new path metric at the memory location used by the old path metric, which old metric was employed to calculate the new metric. If m metric values are read and m metric values are simultaneously calculated in parallel, it is possible to store the new, calculated metrics in the memory position where the old metrics were held. This is advantageous, since the size of the storage area for the path metrics is reduced to half compared to the storage area employed in prior art Viterbi decoders for the same performance with regard to path metric computations.

Abstract: Aspects of a method and system for UMTS HSDPA Shared Control Channel processing may include calculating at a receiver, for each one of a plurality of control channels, a quality metric derived from at least one Viterbi Decoder state metric. A control channel may be selected on the basis of the quality metrics, where the quality metric is selected that provides maximum confidence. The selected control channel may be chosen if its corresponding 3GPP metric is greater than a specified threshold, where the threshold is a design parameter. A validity of a selected control channel may be determined based on consistency and a CRC, where the CRC may be derived from decoding a sub-frame. The calculating and selecting may be done for a first slot of a sub-frame for High-Speed Shared Control Channels.

Abstract: A device and method for effectively judging a communication quality in a communication system and a program used for the judgment. A communication device generates a four-value FSK symbol by adding a redundant bit to a bit of the most important part of encoded audio data. The symbol containing the redundant bit is set so that the symbol value is the maximum value of the minimum value of the four values which may be obtained. A reception device R receives the FSK modulation wave, restores the symbol, counts the number of redundant bits contained in the restored symbol and having incorrect values, decides whether to perform a bad frame masking process and what kind of bad frame masking process is to be performed, and executes the decided process. Thus, it is possible to accurately or rapidly judge the communication quality with a simple configuration.

Abstract: Systems and methods for generating likelihood metrics for trellis-based detection and/or decoding are described. In some embodiments, likelihood metrics for a first subset of bit locations in an error pattern (e.g., bit locations that fall within the error event update window) are updated based on a first metric, such as the path metric difference, associated with an alternate path that converges to the same trellis state as the decoded sequence. In some embodiments, likelihood metrics for a second subset of bit locations in the error patterns (e.g., bit locations that do not fall within the error event update window) are updated based on a second metric, such as a predetermined value of zero, a small metric, or the path metric difference for a path that does not converge into the same winning state as the decoded sequence for the particular error update window of interest.

Abstract: A soft decision value output detector includes a plurality of maximum a posteriori (MAP) detectors. The MAP detectors are configured to simultaneously generate state metrics for portions of a sampled data sequence, and to generate soft decision values based on the generated state metrics. Each of the MAP detectors includes a first MAP unit that generates state metrics by a reverse iteration using first and second reverse Viterbi operators and a forward iteration using a first forward Viterbi operator through portions of the sampled data sequence, and a second MAP unit that generates state metrics by a reverse iteration using third and fourth reverse Viterbi operators and a forward iteration using a second forward Viterbi operator through portions of the sampled data sequence.

Abstract: Encoded symbols of a concatenated convolutional-encoded and block encoded signal are presented to a conventional first stage of a concatenated decoder, comprising in sequence a soft metric generator, a Viterbi decoder, a first de-interleaver and a first block decoder such as a Reed-Solomon decoder. The encoded symbols are also presented to a delay chain to produce progressively delayed encoded symbols. Where an output block of the conventional decoder is indicated as being a valid codeword by the first block decoder, the bytes in this block are marked as being correct. These bytes that are known to be correct are then used after interleaving and serialization as known bits input to a second stage of the decoder process operating on the delayed encoded symbols and incorporating a modified soft metric generator constrained by the known bits. This process can be extended to further iterations as required.

Abstract: An ACS circuit includes: a basic DPM retaining section (11) for retaining basic DPMs (differential path metrics); a basic DPM calculating section (12) for calculating the basic DPMs; a reference DPM calculating section (13) for calculating reference DPMs, which are DPMs other than the basic DPMs; a basic DBM calculating section (14) for calculating basic DBMs (differential branch metrics), which are DBMs necessary for calculating the basic DPMs; and a path selecting section (15) for selecting the most likely paths for Viterbi decoding in accordance with the basic DPMs, the reference DPMs and the basic DBMs. The basic DPM calculating section (12) calculates new basic DPMs in accordance with the basic DPMs, the reference DPMs, the basic DBMs, and the results of the most likely path selection by the path selecting section (15).

Abstract: In a digital system using a turbo code, a method for performing iterative decoding in accordance with a Log-MAP Algorithm comprises the steps of:—generating a look-up table comprising a plurality of values representative of a correcting factor;—performing a first calculation to obtain a forward metric;—performing a second calculation to obtain a backward metric;—performing a third calculation to obtain a log-likelihood ratio for every information bit to be decoded. In accordance with the method, at least one and no more than two of such calculations are performed by the use of said look-up table for implementing the Log-MAP decoding algorithm and the remaining calculations are performed implementing a Max-Log-MAP decoding algorithm.

Abstract: When a convolution code is decoded, electric power consumption is suppressed keeping error correction capability. In a Viterbi decoder which decodes received signal, a convolution code, having plural series with a soft decision Viterbi decoding method, an estimation control unit estimates quality of the received signal and outputs a control signal according to the quality to a branch metric calculation data obtaining unit. The branch metric calculation data obtaining unit performs logical combination operation between digital multi-value data expressing amplitude of the received signal and the control signal, and thereby, outputs the digital multi-value data directly to a decoding execution unit if the quality of the received signal is lower than a prescribed level, and outputs the digital multi-value data reduced by series each as branch metric calculation data to the decoding execution unit if the quality of the received signal is no less than the prescribed level.

Abstract: A digital broadcast transmitting system and a signal processing method thereof that improves the receiving performance of the system. A digital broadcast transmitter includes a randomizer to receive and randomize a transport stream into a specified position of which stuff bytes are inserted, a replacement sequence generator to generate known data including a predefined sequence, a stuff-byte exchange unit to insert the known data into the specified position of the transport stream into which stuff bytes are inserted, an encoder to encode the transport stream output from the stuff-byte exchange unit for an error correction, and a transmission unit to modulate the encoded transport stream, RF-convert the modulated transport stream and transmit the RF-converted data. The digital broadcast receiving performance is improved even in an inferior multi-path channel by detecting the known data from the received transmission and using the known data for synchronization and equalization.

Abstract: A circular Viterbi decoder is capable of improving a data decoding speed without being limited by a sampling speed of a sampling and holding circuit. An analog Viterbi decoder includes: a clock divider which generates a plurality of clock signals by dividing a clock frequency of an externally-input clock signal, a plurality of sampling and holding units which sample and hold input analog data according to the clock signals generated from the clock divider, and a multiplexer which sequentially and alternately outputs the analog data sampled and held by the sampling and holding units.

Abstract: A MIMO receiver implements a method for the soft bit metric calculation with linear MIMO detection for LDPC codes, after linear matrix inversion MIMO detection. In the receiver, a detector detects the estimated symbol and the noise variance. Further, a soft metric calculation unit computes the distance between the estimated symbol and the constellation point, and then divides the distance by the noise variance to determine the soft bit metrics.

Abstract: The disclosed technology provides a less resource intensive way to decode a parity check code using a modified min-sum algorithm. For a particular parity check constraint that includes n variable nodes, an LDPC decoder can compute soft information for one of the variable nodes based on combinations of soft information from other variable nodes, wherein each combination includes soft information from at most a number d of other variable nodes. In one embodiment, soft information from one of the other variable nodes is used in a combination only if it corresponds to a non-most-likely value for the other variable node.

Abstract: A detector includes a Viterbi based detector and an erasure detector that detects as erasures one or more bits associated with a decoding window in which survivor paths do not merge within the decoding window.

Abstract: An improved Viterbi detector is disclosed in which each branch metric is calculated based on noise statistics that depend on the signal hypothesis corresponding to the branch. Also disclosed is a method of reducing the complexity of the branch metric calculations by clustering branches corresponding to signals with similar signal-dependent noise statistics. A feature of this architecture is that the branch metrics (and their corresponding square difference operators) are clustered into multiple groups, where all the members of each group draw input from a single, shared noise predictive filter corresponding to the group. In recording technologies as practiced today, physical imperfections in the representation of recorded user data in the recording medium itself are becoming the dominate source of noise in the read back data. This noise is highly dependent on what was (intended to be) written in the medium. The disclosed Viterbi detector exploits this statistical dependence of the noise on the signal.

Abstract: ACS (Add Compare Select) implementation for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. During each processing iteration, an ACS module generates a hard decision for each of two trellis stages, as well as a corresponding reliability for each of the two hard decisions. Also, the ACS module is operative to generate the updated state metric for the state at the current trellis stage. Multiple operations are performed simultaneously and in parallel, and control logic circuitry and/or operations employed to select which of the multiple simultaneously-generated resultants is to be employed for each of the hard decisions, reliabilities, and next state metric for the current trellis stage.

Abstract: Register exchange network for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within an REX (Register Exchange) module are implemented using a radix-4 architecture to increase data throughput. Any one or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) are implemented in accordance with the principles of radix-4 decoding processing.

Abstract: A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback in magnetic recording systems. A read channel signal is processed in a magnetic recording device by precomputing branch metrics, intersymbol interference estimates or intersymbol interference-free signal estimates for speculative sequences of one or more channel symbols; selecting one of the precomputed values based on at least one decision from at least one corresponding state; and selecting a path having a best path metric for a given state.

Abstract: Minimal hardware implementation of non-parity and parity trellis. More than one type of trellis can be represented using a minimal amount of hardware. In magnetic recording systems and other communication systems types, there is oftentimes a need to switch between trellises which support parity and ones which do not. Rules are presented herein which will ensure joint representation of more than one trellis while requiring minimal additional hardware when compared to representing only one trellis. To represent the non-parity trellis, emanating states, resultant states, and one or more expansion states (if needed) are all that is required. Any expansion states may also need to have its path metric and path memory corresponded to one of the resultant states to ensure proper detection according to the non-parity trellis.

Abstract: A space-time block decoder for a wireless communications system includes a demodulator that generates a demodulated symbol sequence by derotating a signal constellation of a received symbol sequence. A dimension demultiplexer communicates with the demodulator and generates in-phase and quadrature components of the demodulated symbol sequence. A branch metric computation module communicates with the dimension demultiplexer and generates branch metrics based on the in-phase and quadrature components. A Viterbi decoder communicates with the branch metric computation module and generates a user data sequence based on the branch metrics. The in-phase and quadrature components comprise Gray coded data that is bit-interleaved. The branch metric computation module implements bit-by-bit piecewise linear approximation to generate the branch metrics. A deinterleaver that communicates with the branch metric computation module generates deinterleaved metrics based on the branch metrics.

Abstract: True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

Abstract: Coding apparatus, and an associated method, for forming punctured binary convolutional codes for use in a multi-band OFDM ultra wide band radio communication system. Input data to be communicated is provided to a convolutional coder that forms a ? rate code forming first-stage codes. The ? rate code is punctured by a puncture matrix to form resultant code words. The puncture matrix is of values that optimize code performance at various code rates.

Abstract: The invention presents a combinational fuzzy-decision Viterbi decoder, which combines the modified ? and S-membership functions, to further improve the performance of the dedicated short-range communications (DSRC) system operated in the time-varying fading channel. The combinational fuzzy-decision Viterbi decoder includes parallel-to-serial converter, fuzzy-decision constellation decoder and analog Viterbi decoder. The coding gain of the DSRC system using the proposed combinational fuzzy-decision Viterbi decoder is compared with both the hard-decision and soft-decision Viterbi decoder for the BPSK, QPSK, 16-QAM and 64-QAM OFDM DSRC systems. The improvement in performance of the DSRC system achieved by replacing the hard decision and soft decision Viterbi decoder with the proposed combinational fuzzy-decision Viterbi decoder will be validated with simulations.

Abstract: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).

Abstract: A digital signal processor performs turbo and Virterbi channel decoding in wireless systems. The computation block of the digital signal processor is provided with an accelerator for executing instructions associated with trellis computations. An ACS instruction performs trellis computations of alpha and beta metrics. Multiple butterfly calculations can be performed in response to a single instruction. A TMAX instruction is used to calculate the log likelihood ratio of the trellis.

Abstract: A method for decoding is provided. The method comprises the step of: using information known to a channel decoder to determine a path between two data points, whereby reducing error or bad data effects.

Abstract: In the method for termination of turbo decoding, a plurality of first LLR values (Lai(k)) of a-priori information and a plurality of second LLR values (Lei(k)) of extrinsic information are called up. A value is determined for a decision variable which is characteristic of the number of mathematical sign discrepancies between the first Lai(k)) and the second Lei(k)) values. The turbo decoding is terminated if the number of mathematical sign discrepancies is less than or at least equal to a first number or if the number is greater than or at least equal to a second number.

Abstract: A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.

Abstract: A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback. The maximum data rate that may be achieved by the disclosed reduced-state Viterbi detectors is improved by precomputing a number of candidate intersymbol interference estimates and performing pipelined selection of an appropriate intersymbol interference estimate. A reduced-state Viterbi detector is thus disclosed that precomputes intersymbol interference estimates for speculative sequences of one or more channel symbols; selects one of said precomputed intersymbol interference estimates based on at least one decision from at least one corresponding state using at least two pipeline registers; and selects a path having a best path metric for a given state. In an alternative implementation, intersymbol interference estimate-free signal estimates are selected among precomputed ones.

Abstract: A method and apparatus are disclosed for improving the maximum data rate of reduced-state Viterbi detectors with local feedback. The maximum data rate that may be achieved by the disclosed reduced state Viterbi detectors is improved by precomputing a number of candidate branch metrics and performing pipelined selection of an appropriate branch metric. A reduced state Viterbi detector is thus disclosed that precomputes branch metrics for speculative sequences of one or more channel symbols; selects one of said precomputed branch metrics based on at least one decision from at least one corresponding state using at least two pipeline registers; and selects a path having a best path metric for a given state.

Abstract: A MAP detector system operates in a parallel mode for on-the-fly operations and in a serial mode for error recovery operations. In the parallel mode, a plurality of Viterbi operators process a block of input sampled data in parallel. In the serial mode a selected forward Viterbi operator and two associated reverse Viterbi operators process the entire block of data, in order, to produce soft decision data.

Abstract: A method and an apparatus is provided for producing branch metrics in a LogMAP turbo decoding operation. During a forward recursion of a trellis, a set of primary branch metrics is generated. The primary branch metrics are stored in receiver form in a relatively small memory cache module and corresponding secondary branch metrics are produced by negating the primary branch metrics. The primary branch metrics and the secondary branch metrics constitute all possible branch metrics for a given state in the trellis. During a backwards recursion of the trellis, the stored primary branch metrics are retrieved from the memory cache module and the secondary branch metrics are regenerated by negating the retrieved primary branch metrics.

Abstract: A method of assessing an encoded signal to determine whether a candidate format was used to arrange the signal into blocks before the encoding was done, the method comprising: using the Viterbi algorithm to determine trellis metrics for a point in said signal that would be an end point of a candidate block according to the candidate format; determining from said metrics the likelihood of occupation at said point of an end state of an encoding scheme used to create the encoded signal; decoding a part of said signal ending at said point; and performing a check using said decoded part to determine whether the candidate block satisfies an error protection scheme of the candidate format.

Abstract: A method for decoding tail-biting convolutional codes is disclosed. In the method, all beginning states of a trellis diagram are initialized. Forward Viterbi metrics are calculated for the trellis diagram. A trace-back process is performed from an ending state of the trellis diagram at a first time instance to a first state where all surviving paths converge at a second time instance. Backward Viterbi metrics are calculated for a predetermined period of time from the first state at the second time instance to a second state at a third time instance. A trace-back process is performed from a designated state, which is equal to the second state, at the first time instance to determine a most likely path for the convolutional codes in the trellis diagram.

Abstract: Apparatus, and an associated method, for recovering the informational content of data in an MIMO-OFDM communication system. Different data sets are communicated upon different subcarriers to a receiving station. Apparatus at the receiving station performs data value estimations based upon the communication conditions on the different subcarriers upon which the data is communicated. Separate path length estimations are performed upon the data communicated upon the different subcarriers, at complexity levels responsive to the communication conditions of the subcarriers.

Abstract: According to one embodiment, a maximum likelihood decoder includes a branch metric calculator, a processor configured to perform addition, comparison, and selection of an output from the branch metric calculator and a path metric memory, and outputs a selection signal for identifying a selection result, a path memory configured to store a time variation of the selection signal, and a path detection module configured to detect a decoding signal based on the time variation of the stored selection signal. A decoding method includes selecting operation modes of at least one of the branch metric calculator, the processor, and the path memory between a first operation mode in which an operation is performed at a channel rate frequency and a second operation mode in which an operation is performed at a specific frequency lower than the channel rate frequency.

Abstract: An error correction decoder possessing a decoding method with high error correction performance and capable of operating at a low operating frequency and on a reduced circuit scale. A decoding method based on the SOVA method for improving error correction performance and boosting reliability of the soft decision output by allowing branching of paths other than the survival path at trace-back is achieved by preparing a trace-back circuit for each state, and selecting an output from that output and survival state (survival state+difference of likelihood).