Majority Decision/voter Circuit Patents (Class 714/797)
  • Patent number: 8086944
    Abstract: A hard disk drive with a disk that has a plurality of data bits. The drive includes a circuit that reads each data bit n times and selects a value for the bit based on a reliability factor. The circuit may select a bit based at least in part on the most frequent occurrence of one of a plurality of values. For example, if more 0s occurred than 1s the bit would be set to 0. The reliability factor may be a ratio of the occurrence of 0s to the occurrence of 1s. A bit can be not selected or deselected if the reliability factor exceeds a threshold value.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: December 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yawshing Tang
  • Patent number: 8078920
    Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: December 13, 2011
    Assignee: Fujitsu Limited
    Inventors: Atsushi Morosawa, Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Yuka Hosokawa, Takeshi Owaki, Takashi Yamamoto, Daisuke Itou
  • Patent number: 8020081
    Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: September 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Jin Kong, Sung Chung Park, Yun Tae Lee, Young Hwan Lee, Si Hoon Hong, Jae Woong Hyun, Dong Ku Kang
  • Publication number: 20110214039
    Abstract: A system and method for decoding data. Multi-dimensional encoded data may be received that potentially has errors. The multi-dimensional encoded data may encode each input bit in a set of input bits multiple times in multiple different dimensions to generate encoded bits. The encoded bits may be decoded in at least one of the multiple dimensions. If one or more errors are detected in a plurality of encoded bits in the at least one of the multiple dimensions, an intersection sub-set of the encoded data may be decoded that includes data encoding the same input bits encoded by the plurality of encoded bits in at least a second dimension of the multiple dimensions. The values of the input bits by decoding the intersection sub-set may be changed.
    Type: Application
    Filed: February 28, 2011
    Publication date: September 1, 2011
    Inventors: Avi Steiner, Hanan Weingarten
  • Patent number: 8006157
    Abstract: Outlier detection methods and apparatus have light computational resources requirement, especially on the storage requirement, and yet achieve a state-of-the-art predictive performance. The outlier detection problem is first reduced to that of a classification learning problem, and then selective sampling based on uncertainty of prediction is applied to further reduce the amount of data required for data analysis, resulting in enhanced predictive performance. The reduction to classification essentially consists in using the unlabeled normal data as positive examples, and randomly generated synthesized examples as negative examples. Application of selective sampling makes use of an underlying, arbitrary classification learning algorithm, the data labeled by the above procedure, and proceeds iteratively.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: August 23, 2011
    Assignee: International Business Machines Corporation
    Inventors: Naoki Abe, John Langford
  • Patent number: 8001452
    Abstract: Methods and apparatus are provided for soft decision decoding using reliability values based on a log base two function. A signal is processed to determine one or more reliability values for a soft decision decoder by computing one or more log-likelihood ratio (LLR) values using a log base two function. The soft decision decoder may employ, for example, a belief propagation algorithm. The soft decision decoder can decode, for example, Low-Density Parity Check codes or turbo codes.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: August 16, 2011
    Assignee: Agere Systems Inc.
    Inventor: Kameran Azadet
  • Publication number: 20110185248
    Abstract: In general, techniques are described for performing majority vote error correction techniques. In operation, a communication device comprising a control unit implements the majority vote error correction techniques. The control unit includes a link management module to request a first retransmission of a first communication received over a wireless communication medium in response to detecting a first uncorrectable error in the first communication, requests a second retransmission of the first communication in response to detecting a second uncorrectable error in a second communication received in response to the first retransmission request and receives a third communication in response to the second retransmission. The control unit also includes a majority vote module to, in response to detecting a third uncorrectable error in the third communication, perform a bit-wise majority vote on corresponding bits of the first, second and third communications to generate an error-corrected communication.
    Type: Application
    Filed: January 25, 2010
    Publication date: July 28, 2011
    Applicant: QUAL COMM Incorporated
    Inventors: Joel Linskey, Sang-Uk Ryu
  • Publication number: 20110161787
    Abstract: Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.
    Type: Application
    Filed: December 28, 2009
    Publication date: June 30, 2011
    Applicant: NXP B.V.
    Inventors: Andries Pieter Hekstra, Weihua Tang
  • Patent number: 7962841
    Abstract: A majority voting Viterbi decoder includes a branch metric calculator (BMC) for measuring a difference between a received symbol and a reference symbol and outputting branch metrics from the difference; an add-compare-selection (ACS) unit for determining an optimal path using the branch metrics; a survival path memory unit for outputting decoded symbols by performing decoding based on the optimal path; and a majority voting unit for determining a final decoded symbol by performing majority voting for the decoded symbols output from the survival path memory unit. Accordingly, by adding the majority voting unit, a decoding depth can be reduced without the loss of an encoding gain required in a system, and by reducing the decoding depth, miniaturization is possible, power consumption can be reduced, and a processing delay in a memory can be minimized.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: June 14, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shi-Chang Rho, Jun Jin Kong
  • Publication number: 20110138254
    Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. An associated memory device and the controller thereof are further provided.
    Type: Application
    Filed: May 6, 2010
    Publication date: June 9, 2011
    Inventor: Tsung-Chieh Yang
  • Patent number: 7949841
    Abstract: Typical computer programs may incur costly memory errors that result in corrupted data. A new memory model is presented wherein it may be determined that certain data is critical and critical data may be stored and protected during computer application execution. Critical Memory allows that data determined to be critical may be stored and retrieved using functions enabled to increase the reliability of the data. Functions are presented enabling allocation of redundant computer memory; functions are presented enabling consistently writing critical data to redundant locations; and functions are presented enabling reading critical data while ensuring that the data read is consistent with the most recent write of critical data and enabled to repair inconsistent data. The memory model and functions presented are designed to be compatible with existing third-party libraries.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: May 24, 2011
    Assignee: Microsoft Corporation
    Inventors: Karthik Pattabiraman, Vinod K. Grover, Benjamin G. Zorn
  • Patent number: 7900125
    Abstract: One or more techniques provide majority detection in error recovery. Accordingly, a device retries reading an ECC codeword having one or more bits for a plurality of retries, and stores each retry. The device (“hard” majority detection) votes on a value of each bit of the codeword based on a majority of corresponding retry values in the plurality of corresponding retries. Also, the device (“soft” majority detection) may determine reliability information for a value of each bit of the codeword based on a reoccurrence ratio of corresponding retry values in the plurality of retries. The device may declare erasures based on the reliability information and a (dynamically adjusted) threshold of uncertainty, e.g., where an “uncertain” bit based on the threshold or any symbol with an “uncertain” bit is declared as an erasure.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: March 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Jingfeng Liu, Bernardo Rub, Peihui Zheng
  • Patent number: 7890706
    Abstract: In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate for the processors.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: February 15, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David J. Garcia, Michael Knowles, Tom A. Heynemann, Jeffrey A. Sprouse
  • Patent number: 7870472
    Abstract: Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redundant configuration arrays. The configuration arrays may each be adapted to be programmed with identical configuration information associated with operation of the data array. Majority voting logic with an output coupled to configuration inputs of the data array and inputs coupled to each of the redundant configuration arrays may be employed. The majority voting logic may be adapted to determine a configuration for the data array based upon an outcome of a majority vote function applied to the configuration information stored in the configuration arrays. Numerous other aspects are disclosed.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: January 11, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Tyler Thorp, Brent Haukness
  • Patent number: 7870471
    Abstract: Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redundant configuration arrays. The configuration arrays may each be adapted to be programmed with identical configuration information associated with operation of the data array. Majority voting logic with an output coupled to configuration inputs of the data array and inputs coupled to each of the redundant configuration arrays may be employed. The majority voting logic may be adapted to determine a configuration for the data array based upon an outcome of a majority vote function applied to the configuration information stored in the configuration arrays. Numerous other aspects are disclosed.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: January 11, 2011
    Assignee: SanDisk 3D LLC
    Inventors: Tyler Thorp, Brent Haukness
  • Patent number: 7859292
    Abstract: A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: December 28, 2010
    Assignee: United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: Robert L. Shuler, Jr.
  • Patent number: 7836386
    Abstract: Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have respective phase shifts relative to the clock signal. An error detection code is calculated from first and second received data carried by the transmitted signals. The error detection code is transmitted from the receiving device to the sending device. An estimated first received data is calculated from the error detection code, wherein the estimated first received data are calculated under the assumption that the second received data are identical to the second test data. The first phase shift is adjusted on the basis of a comparison of the estimated first received data and the first test data.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 16, 2010
    Assignee: Qimonda AG
    Inventors: Otto Schumacher, Martin Maier, Thomas Hein, Aaron John Nygren
  • Publication number: 20100251074
    Abstract: A decoding method for booting from a NAND Flash including a booting page storing a plurality of copies of NAND booting information and a plurality of corresponding parities, each parity generated by an predetermined error correction code (ECC) bit number. The decoding method includes reading the booting page, for obtaining a plurality of configuration data and a plurality of ECC data, and performing a voting scheme and an ECC decoding process on the plurality of configuration data and the plurality of ECC data, for obtaining the NAND booting information. Besides, an encoding method for encoding such booting information is disclosed the same.
    Type: Application
    Filed: March 26, 2009
    Publication date: September 30, 2010
    Inventors: Chin-Huo Chu, Horng-Yi Chang, Jia-Horng Shieh
  • Patent number: 7702992
    Abstract: A semiconductor integrated circuit includes a plurality of flip-flop sets, and a logic circuit configured to consolidate error-detection signals output from the flip-flop sets into one output signal, wherein each of the flip-flop sets includes one or more flip-flops configured to latch input data in synchronization with a common clock signal, and an error detection-&-correction circuit configured to detect and correct an error in data stored in the flip-flops, and to produce one of the error-detection signals indicative of the detection of the error upon the detection of the error.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: April 20, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Toshio Ogawa
  • Publication number: 20100095190
    Abstract: According to one embodiment, a data reading method of a storage device for reading data from a storage module, includes: reading data from the storage module; detecting an error in the data; reading, when the error is detected, the data several times; storing each data read several times in a buffer; calculating correlation between the data stored in the buffer; selecting data stored in the buffer with strong correlation so as to exclude data with low correlation from the selection; performing majority decision on the selected data or averaging the selected data; and outputting a result of the majority decision or the averaging as read data.
    Type: Application
    Filed: September 18, 2009
    Publication date: April 15, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Kanaya
  • Patent number: 7676725
    Abstract: A method of generating a code that minimizes error propagation by selecting integers m, n, mrl, and a range of fractions od, where m represents the number of bits in an unencoded sequence, where n represents the number of bits in an encoded sequence, where mrl represents the maximum run length of an encoded sequence, and where od represents a range of ones densities of an encoded sequence. Next, generating an encoding map M that maps each unencoded sequence to an n-bit encoded sequence that satisfies od and mrl. Next, generating a decoding map N that maps each n-bit sequence to an m-bit sequence. Next, determining an error-propagation score for M and N. Then, returning to the step of generating M if a user requires a lower error-propagation score.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: March 9, 2010
    Assignee: The United States of America as represented by the Director, National Security Agency
    Inventors: Leslie Newton McAdoo, Jr., Dean M. Evasius
  • Publication number: 20100005373
    Abstract: A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.
    Type: Application
    Filed: July 1, 2008
    Publication date: January 7, 2010
    Inventors: Omprakash Bisen, Karthikeyan Ramamurthi, Hima Bindu
  • Publication number: 20100005367
    Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.
    Type: Application
    Filed: March 11, 2009
    Publication date: January 7, 2010
    Applicant: Ramot At Tel Aviv University Ltd.
    Inventors: Simon LITSYN, Idan Alrod, Eran Sharon, Mark Murin, Menahem Lasser
  • Patent number: 7620883
    Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: November 17, 2009
    Assignee: XILINX, Inc.
    Inventors: Carl H. Carmichael, Phil Edward Brinkley, Jr.
  • Patent number: 7577012
    Abstract: A ferroelectric memory device includes: an odd number of memory regions, the odd number being at least three or higher; a readout circuit that reads data of 0 or 1 stored in the odd number of memory regions; a comparison circuit that compares readout data at corresponding addresses of the odd number of memory regions, and decides comparison data of 0 or 1 according to voting; and a write circuit that writes the comparison data in one region in the odd number of memory regions.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: August 18, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Yasuhiko Murakami
  • Patent number: 7539931
    Abstract: In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output from a logic circuit are applied to a triple redundant memory element. The delay of the first delayed clock signal is equal to or greater than the pulse width of a soft error event occurring in the logic circuit. The delay of the second delayed clock signal is equal to or greater than half the pulse width of a soft error event occurring in the logic circuit.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: May 26, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Larry J. Thayer
  • Patent number: 7539920
    Abstract: Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: May 26, 2009
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eun-A Choi, Nae-Soo Kim, Deock-Gil Oh, Ji-Won Jung
  • Patent number: 7536631
    Abstract: A communication circuit for verified communication comprising a transmitter having input terminals to receive a data word, an encoder configured to encode the data word to create an encoded word different from the data word, and output terminals configured to transmit the data word and the encoded word. A receiver is coupled to the transmitter and includes input terminals to receive the data word as a received word and the encoded word, a decoder configured to decode the encoded word to create a decoded word, and a comparator configured to compare the received word and the decoded word to create a select signal, and a selector responsive to the select signal and configured to select the received data word or the decoded word based at least in part on the select signal. Advantages of the invention include the ability to verify redundant received data without decreasing bandwidth or increasing latency.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: May 19, 2009
    Assignee: RMI Corporation
    Inventors: Brian Hang Wai Yang, Kai-Yeung Siu, Mizanur M. Rahman, Ken Yeung, Hsi-Tung Huang
  • Patent number: 7530004
    Abstract: An error detection and correction apparatus includes three threshold logic units which make decisions based on current and previous bit values in a bit stream of block-coded data. One of the threshold logic units decodes the data stream based on an advancing time stream of data. Another threshold logic unit decodes the data stream based on a time-reversed stream of data, and the last threshold logic unit decodes the data stream based on a time-reversed input stream of data and a time-reversed set of decisions made by the first threshold logic unit. Each threshold logic unit generates decisions and a parity check of those decisions Error identification information is compared between the three streams of decisions and parity checks on those decisions, thereby producing error information, which is processed by a circuit which determines which is the most likely data transmitted.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: May 5, 2009
    Assignee: Neural Systems Corp.
    Inventors: Charles Sinclair Weaver, Constance Dell Chittenden, A. Brit Conner
  • Patent number: 7526037
    Abstract: A reduced-complexity maximum-likelihood detector is disclosed that provides a high degree of signal detection accuracy while maintaining high processing speeds. The detector processes the received symbols to obtain initial estimates of the transmitted symbols and then uses the initial estimates to generate a plurality of reduced search sets. The reduced search sets are then used to generate decisions for detecting the transmitted symbols.
    Type: Grant
    Filed: December 31, 2004
    Date of Patent: April 28, 2009
    Assignee: Broadcom Corporation
    Inventor: Min Chuin Hoo
  • Patent number: 7512871
    Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: March 31, 2009
    Assignee: XILINX, Inc.
    Inventors: Carl H. Carmichael, Phil Edward Brinkley, Jr.
  • Patent number: 7509567
    Abstract: A system and method for an election and data majority mechanism that solves problems such as bit flipping, mistracking, miscaching, and I/O status errors during real-time operations. Multiple copies of data are stored on various storage media of a data processing system. Errors that occur on the storage media or on other components of the data processing system are resolved by selecting the data with the highest frequency as the data majority. The data majority is propagated throughout the storage media to correct errors.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: March 24, 2009
    Assignee: Symantec Operating Corporation
    Inventors: Oleg Kiselev, Ron Karr, John Colgrove
  • Publication number: 20090037798
    Abstract: A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).
    Type: Application
    Filed: July 6, 2008
    Publication date: February 5, 2009
    Inventors: Alan J. Drake, AJ Klein Osowski, Adrew K. Martin
  • Patent number: 7451384
    Abstract: A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: November 11, 2008
    Assignee: Honeywell International Inc.
    Inventors: David O. Erstad, Roy M. Carlson
  • Patent number: 7444565
    Abstract: A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output from each programmable logic component to a fixed logic component, examining the outputs, and determining a validated output from among the outputs. An architecture for mitigating logic upsets includes an input, a plurality of programmable logic components, and a fixed logic component. The input is provided to each of the programmable logic components. Each programmable logic components includes an encryption algorithm and a first majority voting logic, and processes the respective input to determine a respective output. The fixed logic component includes a second majority voting logic. The fixed logic component receives each respective output from the programmable logic components, examines the outputs, and determines a validated output.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: October 28, 2008
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventor: Charles Francis Haight
  • Publication number: 20080244365
    Abstract: A decoding apparatus includes a decoder register for receiving data having a codeword including null data bits, and decoding the received data while shifting Bit Under Decoding (BUD) by one bit. A connection unit outputs a check result by applying a predetermined check equation to the data output from the decoder register. A majority logic unit for determines if an error is detected according to the check result output from the connection unit, and outputs the determination result. An error information unit determines if there is an error in the received data and if there is an uncorrectable error in the decoded data.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 2, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Vasily PRIBYLOV
  • Patent number: 7428473
    Abstract: A system comprises at least one non-hardened processor configured to run a plurality of mission related processes; at least one threat detector configured to detect one or more conditions which indicate the onset of a threat to the operation of the at least one non-hardened processor; and at least one hardened processor configured to elevate at least one health monitoring process of the at least one non-hardened processor from a background process to a foreground process when the at least one threat detector detects a condition indicating the onset of a threat, wherein the at least one hardened processor manages the operation of the at least one non-hardened processor based on the results of the at least one health monitoring process.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: September 23, 2008
    Assignee: Honeywell International Inc.
    Inventors: Manuel I. Rodriguez, James E. Lafferty, Edward R. Prado, Jamal Haque, Keith A. Souders
  • Patent number: 7424642
    Abstract: A system and method for reintegration of a redundant controller after occurrence of a fault is provided, comprising synchronizing outputs of a primary controller with outputs of secondary controllers. The controller is placed in a different mode of operation in which its output is not used in system control. A meta-controller is activated to drive the primary controller to the same states at which the secondary or redundant controllers operate. A voting mechanism is used to determine a fault in an output to a controlled device. Control of the device using the secondary outputs is effected. The primary controller recalculates the primary output, based upon the primary output; a feedback signal; and, the secondary outputs. Control using the primary output is permitted when the primary output is within an allowable range of the secondary outputs.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: September 9, 2008
    Assignee: GM Global Technology Operations, Inc.
    Inventors: Mark N. Howell, Pradyumna K. Mishra
  • Patent number: 7418641
    Abstract: A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: August 26, 2008
    Assignee: International Business Machines Corporation
    Inventors: Alan J. Drake, Aj KleinOsowski, Andrew K. Martin
  • Patent number: 7350136
    Abstract: A system is presented that provides real-time performance for iterative multi-user detectors, such as Turbo MUDs, which are used to separate simultaneous transmissions on the same frequency, by permitting the MUD to use a less computationally intense, fast-processing algorithm and to correct for errors caused by the fast processing. In order to reduce the errors, a voting system is coupled to the output of the multi-user detector within the iterative system. The voting system provides confidence values on a bit-by-bit basis for the estimates made by the multi-user detector, with the confidence values then being utilized as soft inputs to a bank of conventional single-user decoders.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: March 25, 2008
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Diane G. Mills
  • Publication number: 20080052608
    Abstract: A method including transmitting a binary vector from a source node to a relay node and receiving a signal vector at the relay node. The method also includes compressing the signal at the relay node by multiplying the signal with a matrix using probabilities and converting output probabilities from the multiplying into retransmission signal amplitudes, the signal amplitude depending not only on a probability of a bit but on a transmission power constraint at the relay node. The method also includes transmitting, by the relay node, estimates of information from the source node to a destination node.
    Type: Application
    Filed: August 3, 2006
    Publication date: February 28, 2008
    Inventors: Arnab Chakrabarti, Alexandre de Baynast, Ashutosh Sabharwal, Behnaam Aazhang
  • Patent number: 7318175
    Abstract: A memory modeling circuit with fault toleration includes a compare circuit, a control circuit and a test circuit. The compare circuit receives the data stored in the same address of memories and compares data with each other to produce the correct reading data. The control circuit connects with the control signals of the memories and detects that control signals. The control circuit has data output/input ports. When the control signal of the memories is to write, the control circuit enters a writing mode and writes the writing data received from the data output/input ports in the same address of the memories. When the control signal of the memories is to read, the control circuit enters a reading mode, receiving the reading data generated by the compare circuit and outputs it through the data output/input ports. The test circuit receives the data stored in the same address of the memories and the reading data generated by the compare circuit to generate a testing result.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: January 8, 2008
    Assignee: Via Technologies, Inc.
    Inventor: Chin Lee
  • Patent number: 7308605
    Abstract: In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors maintained as erroneous data. The data maintained in the memory regions is compared to detect a latent processing error in a first memory region. The latent processing error is resolved by copying data from a second memory region into the first memory region where the data maintained in the second memory region is determined to be identical to data maintained in at least a third memory region.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: December 11, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert L. Jardine, David L. Bernick, Thomas A. Heynemann, James R. Smullen
  • Patent number: 7280468
    Abstract: A constant amplitude coded bi-orthogonal demodulator demodulates the received constant amplitude bi-orthogonal modulated data, cancels the parity bits to generate the serial data, detects the occurrence of an error by dividing the demodulated data into a plurality of groups of data, outputs the serial data as demodulated data if an error does not occur, sequentially converts bit polarities of data of groups in which an error occurs if the error detector detects the error, compares distances between the received bi-orthogonal modulated data and the constant amplitude coded bi-orthogonal modulated data, and selects, as demodulated data, data of which corresponding bit polarities are changed according to the comparison results. According to the present invention, power consumption is reduced, a power amplifier can be manufactured at an inexpensive cost, interference robustness can be ensured, and data can be transmitted at a high transmission rate and a variable transmission rate.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: October 9, 2007
    Assignee: Korea Electronics Technology Institute
    Inventors: Sung-Jin Kang, Jin-Woong Cho, Cheol-Hee Park, Min-Chul Ju, Dae-Ki Hong, Kyeung-Hak Seo, Myoung-Jin Kim
  • Patent number: 7269780
    Abstract: An integrated circuit device includes at least one functional module which outputs save data in synchronism with a saving clock signal, a power supply control unit which selects one of the functional modules, and controls stop and resumption of power supply to the selected functional module, a save data storage unit which stores save data output from a functional module selected by the power supply control unit, and an error checking and correction unit which performs error checking and correction for the save data stored in the save data storage unit when the save data is to be restored to the functional module in synchronism with a restoration clock signal.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: September 11, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukio Arima, Koichiro Ishibashi, Takahiro Yamashita
  • Patent number: 7246297
    Abstract: An iterative decoder for receiving a sequence of samples representing a series of symbols, and for decoding the received sequence to the series. The decoder includes a plurality of variable-nodes. Each node receives and stores a sample from the sequence, iteratively passes messages to, and receives messages from, at least two connected check-nodes in a plurality of check-nodes, sends each connected check-node a message determined in accordance with the stored sample and message received from the at least one other check-node segment, and provides as output a decoded symbol determined in accordance with the received messages from the connected check-nodes and the stored sample.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: July 17, 2007
    Inventors: Pirouz Zarrinkhat, Sayed Amirhossein Banihashemi
  • Patent number: 7225394
    Abstract: A circuit for correcting errors in an N times duplicated signal is described. The circuit comprises a plurality of AND gates, wherein each of the AND gates comprises a plurality of inputs for receiving a copy of the N times duplicated signal; and an OR gate having a plurality of inputs, wherein each input of the OR gate is connected to an output of one of the AND gates, wherein an output of the OR gate comprises the corrected signal.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: May 29, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Tyler James Johnson
  • Patent number: 7215581
    Abstract: In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the third settable memory element. The propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: May 8, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jonathan P Lotz, Daniel W. Krueger, Manuel Cabanas-Holmen
  • Patent number: 7185263
    Abstract: A method of decoding possibly mutilated code words (r) of a code (C) includes decoding the differences (D) of a number (L?1) of pairs of possibly mutilated code words (rib, ri+1) to obtain estimates (u, v) for the differences of the corresponding pairs of code words (ci, ci+1), combining the estimates (u, v) to obtain a number (L) of at least two corrupted versions (wj) of a particular code word (c), forming a code vector (z) from the number (L) of corrupted versions (wj) of the particular code word (c) in each coordinate, decoding the code vector (z) to a decoded code word (c?) in the code (C), and using the generator matrix (G) to obtain the information word (m) and the address word (a) embedded in the decoded code word (c?).
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: February 27, 2007
    Assignee: Koninklijke Philip Electronics N. V.
    Inventors: Andries Pieter Hekstra, Constant Paul Marie Jozef Baggen, Ludovicus Marinus Gerardus Maria Tolhuizen
  • Patent number: 7107515
    Abstract: A radiation hard logic device such as a divider is disclosed. The logic device includes a voter module to determine an error free logic device output, a feedback module to generate a correction signal and provide the signal to a logic correction module to correct the erroneous device output at substantially the same time that the erroneous logic device is presented to the logic correction module.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: September 12, 2006
    Assignee: The Boeing Company
    Inventor: Rahul S. Majumdar