Abstract: Fault tolerance is provided in a computing system using a technique referred to as indirect instrumentation. In one embodiment, a number of different copies of a given target program are executed on different machines in the system. Each of the machines includes a controller for controlling the execution of the copy of the target program on that machine. The controllers communicate with a user interface of an instrumentation tool on another machine. A user specifies variables to be monitored, breakpoints, voting and recovery parameters and other information using the user interface of the instrumentation tool, and the tool communicates corresponding commands to each of the controllers for use in executing the copies. A fault is detected in one of the copies by comparing values of a user-specified variable generated by the different copies at the designated breakpoints.

Abstract: A method, circuit and apparatus is provided for preserving and/or correcting product engineering information. Non-volatile storage devices reserved for receiving product engineering bits can either be contained in at least three separate storage locations spaced from each other across the integrated circuit or, alternatively, be contained in a single storage location area with error correction bits and/or words added to that location. In the first instance, redundant product engineering bits are written to each storage location. Product engineering bits read from a majority of those locations which have identical values are deemed valid. The addition of extra bits and/or words can be combined with the possibly defective product engineering bits to correct errors in those bits.

Abstract: A detector system employing a Viterbi algorithm includes an apparatus and method which constructs a double-state trellis structure for determining a most likely received symbol sequence with respect to an observed sequence of channel output samples. In the double state trellis, pairs of states are identified having equivalent branch metric values which also have a same decision during a path select, thus allowing these pairs of states to share a compare operation of a previous state metric. Consequently, to calculate an updated or current state metric value, an add, compare and select (ACS) circuit may compare only the previous state metric values to determine a minimum value for a transition between two states while combining each previous state metric value with its corresponding branch metric to provide an updated or current state metric value.

Abstract: A computer system uses redundant voting at the hardware clock level to detect and to correct single event upsets (SEU) and other random failures. In one preferred embodiment, the computer includes four or more commercial processing units (CPUs) operating in strict "lock-step" and whose outputs (33, 37) to system memory and system bus are voted by a gate array which may be implemented in a custom integrated circuit. A custom memory controller interfaces to the system memory and system bus. The data and address (35, 37) at each write to and read from memory within the computer are voted at each CPU clock cycle. A vote status and control circuit "reads" the status of the vote and controls the state of the CPUs using hardware and software. The majority voted signals are used by the agreeing CPUs 32 to continue processing operations without interruption.

Abstract: A voting circuit (34) comprises a first variable delay (60) operable to receive a first set of signals in a clock signal and to determine a first delay based on the first set of signals. The first variable delay (60) generates a first delayed output in response to the first delay of the clock signal. A second variable delay (62) is operable to receive a second set of signals and a clock signal and to determine a second delay based on the second set of signals. The second variable delay (62) generates a second delayed output in response to the second delay of the clock signal. A latch (64) is connected to the first and second variable delays. The latch (64) is operable to receive the first and second delayed outputs and to generate a latched voting output in response to at least one of the first and second delayed outputs.

Abstract: Communications between an RFID interrogator and an RFID transponder require that no more than one transponder be present in the reading range of the interrogator and transmitting into motion at any given time. If multiple transponders are in the field, then a collision between the return signals of the transponders occurs, rendering the signals unreadable. A method to resolve the collisions and allow for accurate transmission of each transponder's data is given. This method is especially effective over other methods when the transponder is a read-only type of device, whereby there is no communications interrogator on board the read-only transponder.

Abstract: An single event upset (SEU) tolerant system for detecting and correcting an SEU includes a decision element (200) for receiving a plurality of outputs (120) from a plurality of signal generators (105) and producing an output (130) therefrom. The decision element includes voters which provide two levels of voting for the plurality of redundant outputs (120). First-level voters (300) provide intermediate voted outputs (315) which are received by a second-level voter to determine an output (130). An output disabler (400) determines when an output is provided external to the decision element. A plurality of comparators (210) receive intermediate voted outputs (315) from first-level voters and compare with a plurality of outputs from a plurality of signal generators to determine upset detected signals (125). An upset detected signal controls the selection of feedback for an element having experienced an SEU.

Abstract: The present invention uses an acoustic modem embedded in a remote device enhanced with automatic repeat request and forward error correction routines to provide reliable transfer of electronic messages from the messaging server to the remote device. This may provide significantly better error correction than standard PC modems. Also the present invention, may provide a fast, reliable connection sequence by use of a preamble frame. According to an embodiment of the present invention, a method of communicating messages between a messaging server and a remote device is provided. The method includes a variety of steps such as establishing a connection between the messaging server and the remote communication device by transmitting a preamble frame, exchanging data frames between the remote device and the messaging server, detecting and correcting errors in received frames, and re-transmitting received frames, if errors are uncorrectable.

Abstract: A data recovery scheme is disclosed wherein a majority voting scheme arrives at the correct data and resolves ties with a minimum number of reads. The method includes reading at least one instance of data including a first set of ECC checkbytes from a media, each instance of data and ECC checkbytes comprising a string of bits, forming a voting data string from a majority value for each bit position in the string of bits, generating a second set of ECC checkbytes using the voted data string and returning the voted data sting to a host if the second set of ECC checkbytes is equal to the first set of ECC checkbytes.

Abstract: A method and device for error-correcting a plurality of bits transmitted over RF channels in a cellular communication system are provided. The present invention applies principles of majority voting to error-correct a plurality of bits in a message word simultaneously. Further, the present invention applies its error-correction capability to virtually any number of repeat transmissions over forward and reverse control/voice channels. Following synchronization of the transmit and receive stations, a message word having n-bits is transmitted repeatedly. The repeat bits are separated and analyzed whereafter the true logical state of the original n-bits is determined. The originally transmitted message word is then reconstructed based upon the determined true logical state of the n-bits.

Abstract: A method for handling different of types of data bit errors in a computer system. In one embodiment, the method comprises the step of storing a data line in a first storage location. The method also includes the step of retrieving the data line from the first storage location. Data bit errors in the data line are detected and the data line is marked as containing a data bit error and stored in a storage location if the data line is not to be used immediately by a requesting process; otherwise error handling is performed by halting the requesting process.

Abstract: At a signal transmission rate of 1 Gb/s, the "bit time" is 1 ns. This corresponds to a bit length in an optical fibre of 0.2 m. In view of the fact that skew shall not exceed one-tenth of a bit length, this means that length differences between different conductors in a transmission line may not exceed 2 cm. With the intention of minimizing the skew that would thus otherwise occur in a transmission line, the transmission line (1) and its conductors (2) have been joined to form a ribbon cable or flat cable where the length difference (5) between different conductors (2) in the transmission line does not exceed 2 cm. By providing transmission lines, such as rolled-up flat ribbon cables for instance, which have been previously cut to precise and appropriate lengths, such as lengths of 10, 20, 30 m for instance, with a largest length deviation between different conductors of .+-.1 cm, skew can be minimized when using the cables.

Abstract: Communications between an RFID interrogator and an RFID transponder require that no more than one transponder be present in the reading range of the interrogator and transmitting into motion at any given time. If multiple transponders are in the field, then a collision between the return signals of the transponders occurs, rendering the signals unreadable. A method to resolve the collisions and allow for accurate transmission of each transponder's data is given. This method is especially effective over other methods when the transponder is a read-only type of device, whereby there is no communications interrogator on board the read-only transponder.

Abstract: The present invention recovers data utilizing information from previously received data packets to reconstruct a data packet with an ever increasing probability of reconstructing the actually transmitted data packet. With each new reception, the accumulated information brings the receiver closer to obtaining the actually transmitted data packet. This use of information which might otherwise be discarded permits highly efficient and effective bit error correction particularly useful in hostile communications environments by transceivers with limited data processing and/or memory resources.

Abstract: A corrected digital response signal is generated from a corrupted transponder response signal by receiving the response signal an odd number of times, greater than one, and sampling each received response signal a predetermined number of times. Then, the sample values from each transponder response signal are compared to one another and a majority sample value is obtained. The majority sample value is the value ordained by the majority and therefore represents the corrected response signal value. Alternatively, if time does not permit reception of more than one transponder response signal, additional response signals may be generated from the originally received response signal by shifting the received response by a predetermined number of samples to the right and by shifting the received response by a predetermined number of samples to the left to generate second and third response signals.

Abstract: Computing modules can cooperate to tolerate faults among their members. In a preferred embodiment, computing modules couple with dual-ported memories and interface with a dynamically reconfigurable Field-Programmable Gate Array ("FPGA"). The FPGA serves as a computational engine to provide direct hardware support for flexible fault tolerance between unconstrained combinations of the computing modules. In addition to supporting traditional fault tolerance functions that require bit-for-bit exactness, the FPGA engine is programmed to tolerate faults that cannot be detected through direct comparison of module outputs. Combating these faults requires more complex algorithmic or heuristic approaches that check whether outputs meet user-defined reasonableness criteria. For example, forming a majority from outputs that are not identical but may nonetheless be correct requires taking an inexact vote.