Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors, including if the die has a defective component. An indication of the defective functional component identification is received. A determination is made if the defective functional component is one of a plurality of similar functional components that can provide the same functionality. The other similar components can be examined to determine if they are parallel components to the defective functional component. The defective functional component is disabled if it is one of the plurality of similar functional components and another component can handle the workflow that would otherwise be assigned to the defective component. Workflow is diverted from the disabled component to other similar functional components.
Type:
Grant
Filed:
December 18, 2003
Date of Patent:
October 28, 2014
Assignee:
Nvidia Corporation
Inventors:
James M. Van Dyke, John S. Montrym, Michael B. Nagy, Sean J. Treichler
Abstract: A data storage system configured to perform prioritized memory scanning for memory errors is disclosed. In one embodiment, the data storage system prioritizes scanning for memory errors based on a quality attribute of pages or zones of a non-volatile memory array. Pages or zones having quality attributes that reflect a lower level of reliability or endurance than other pages or zones are scanned more frequently for memory errors. When memory errors are discovered, the quality attribute of pages or zones can be adjusted to reflect a lower level of reliability or endurance. In addition, stored data can be recovered before it may become permanently lost and before a host system reads the stored data. Improved performance of the data storage system is thereby attained.
Abstract: Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links. An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.
Type:
Grant
Filed:
June 24, 2010
Date of Patent:
October 14, 2014
Assignee:
International Business Machines Corporation
Inventors:
John S. Dodson, Frank D. Ferraiolo, Michele M. Franceschini, Ashish Jagmohan, Luis A. Lastras-Montano, Kenneth L. Wright, Lisa C. Gower
Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.
Type:
Grant
Filed:
July 27, 2012
Date of Patent:
October 14, 2014
Assignee:
LSI Corporation
Inventors:
Weijun Tan, Shaohua Yang, Kelly K. Fitzpatrick, Xuebin Wu, Fan Zhang
Abstract: A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.
Type:
Grant
Filed:
April 19, 2012
Date of Patent:
October 14, 2014
Assignee:
Sandisk Technologies Inc.
Inventors:
Deepak Pancholi, Manuel Antonio D'Abreu, Radhakrishnan Nair, Stephen Skala
Abstract: A wireless device couples an electronic device employing a wired-link protocol to, for example, a wireless personal area network (WPAN). The wireless device comprises a wired interface configured for coupling to the electronic device, a wired transceiver coupled to the wired interface, the at least one wired transceiver configured for functioning as a terminus of a wired link coupled to the electronic device, and a wireless transmitter or transceiver coupled to the wired transceiver and configured for functioning as a terminus of a wireless link in the WPAN. The wireless device may be configured for coupling a plurality of dissimilar wired devices together via a wireless link.
Abstract: The invention relates to a method for protecting a sensitive operation by checking the integrity of at least a subset of the data manipulated by the sensitive operation. Data to be checked are divided into blocks, an intermediate integrity check value being computed for each block, the intermediate integrity check values being computed in random order. The invention also relates to a cryptographic device wherein at least one sensitive operation of the cryptographic device is protected by a method according to the invention.
Type:
Grant
Filed:
April 22, 2013
Date of Patent:
September 30, 2014
Assignee:
Gemalto SA
Inventors:
Stephanie Salgado, David Vigilant, Guillaume Fumaroli
Abstract: Biometric data relating to a biological part are processed by obtaining, on the one hand, a first set of transformed biometric data (f(B1)) by applying at least one irreversible transformation to a first set of biometric data (B1), and, on the other hand, a second set of transformed biometric data (f(B2)) by applying said transformation to a second set of biometric data (B2). Thereafter, a decision is made as to whether the second biometric data set corresponds to the first biometric data set on the basis of a comparison between the first transformed biometric data set and the second transformed biometric data set, said comparison being performed at the bit level of a digital representation of said first and second transformed biometric data sets as a function of an error corrector code word.
Abstract: A non-volatile memory array storing data and ECCs includes error correcting logic. A data set can be read by performing iterations including sensing data using a read bias, and producing an indication of errors in the sensed data. A first iteration uses a first read bias. In each iteration, if the indication in a current iteration is less than a threshold, then the data is output from the selected cells sensed in the present iteration. If the indication in the current iteration exceeds the threshold, then another iteration is performed using a moved read bias, unless the indication in the current iteration shows an increase in errors relative to a previous iteration, in which case then sensed data from the previous iteration is output. Double buffering logic can be used to store sensed data during a current and a previous iteration.
Abstract: An apparatus, system, and method are disclosed for accessing non-volatile cells. An interface module is configured to receive data for storage on a non-volatile memory medium. The non-volatile memory medium includes an array of cells, and each cell encodes a non-power-of-two number of states, or abodes per cell. A base conversion module is configured to convert the data from a binary representation to a representation in a non-binary base. The non-binary base uses a number of unique digits equal to the non-power-of-two number of abodes per cell. A write module is configured to store the converted data to the array of cells.
Type:
Application
Filed:
March 14, 2013
Publication date:
September 18, 2014
Applicant:
FUSION-IO, INC.
Inventors:
Robert Wood, David Flynn, Jeremy Fillingim, Warner Losh
Abstract: Embodiments of the present invention provide a system for secure error detection and synchronous data tagging for high-speed data transfer (e.g., utilizing a set of SSD memory disk units). Specifically, in a typical embodiment, the system comprises a SSD memory disk unit in communication with a device driver. A first encoded communication stream will be generated with the device driver and sent via PCI-based channel (e.g., full duplex) to the SSD memory disk unit. The stream is received, synchronized, and decoded on the SSD memory disk unit. In turn, the SSD memory disk unit can generate and send a second encoded communication steam to the device driver.
Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.
Abstract: According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count.
Type:
Grant
Filed:
January 20, 2012
Date of Patent:
September 9, 2014
Assignee:
International Business Machines Corporation
Abstract: An information management apparatus for managing data includes a rewritable nonvolatile memory, and a memory controller configured to control inputting information into and outputting information from the nonvolatile memory. The memory controller overwrites a data, which includes a first validity check information, a first data body, a second validity check information, a second data body having the same data as the first data body and a third validity check information arranged in this order, in a designated address area in the nonvolatile memory when the memory controller performs a writing control in which the memory controller writes data in the nonvolatile memory.
Abstract: Provided are a method of decoding an LDPC code for producing several different decoders using a parity-check matrix of the LDPC code, and an LDPC code system including the same. The system includes: an LDPC encoder outputting an LDPC codeword through a channel; a first LDPC decoder decoding the LDPC codeword received through the channel, and when the decoding has failed in a second LDPC decoder, decoding the LDPC codeword according to original parity check matrix of the LDPC codeword, using soft information newly generated after the decoding is ended in the second LDPC decoder; and the second LDPC decoder, when the decoding has failed in the first LDPC decoder, receiving the soft information on each bit from the first LDPC, and decoding the LDPC codeword according to a new parity-check matrix produced from the parity-check matrix of the LDPC codeword using the received soft information on each bit.
Type:
Grant
Filed:
May 17, 2012
Date of Patent:
September 2, 2014
Assignee:
Korea Advanced Institute of Science and Technology
Abstract: The present inventions are related to systems and methods for information divergence based data processing. As an example, a system is disclosed that includes a scheduling circuit operable to calculate a first quality metric using a first information divergence value calculated based at least in part on the first detected output, and to calculate a second quality metric using a second information divergence value calculated based at least in part on the second detected output. A decoder input is selected based at least in part on the first quality metric and the second quality metric.
Abstract: Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding data in a mixed domain FFT-based non-binary LDPC decoder. For example, in one embodiment an apparatus includes a message processing circuit operable to process variable node messages and check node messages in a log domain, and a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain. The message processing circuit and the check node calculation circuit perform iterative layer decoding.
Type:
Grant
Filed:
December 30, 2011
Date of Patent:
August 26, 2014
Assignee:
LSI Corporation
Inventors:
Lei Chen, Zongwang Li, Johnson Yen, Shaohua Yang
Abstract: Embodiments of the present invention provide a method for testing a network under an IPsec mechanism, and relate to the field of wireless communications, so as to correct an error generated by a disorder of service data packet receiving during network testing under the IPsec mechanism. The method for testing a network under the IPsec mechanism includes: receiving a session request message, where the session request message contains information about a quantity of IPsec data packets and a sending time interval of the IPsec data packets; after a session is established with a sending end, receiving an IPsec data packet that carries testing information; and performing error detection for the received IPsec data packet according to the received testing information as well as the information about the quantity of IPsec data packets and the sending time interval of the IPsec data packets in the session request message.
Abstract: A memory device is configured to generate a signal having a temperature compensation function. The device includes a mode register configured to store error detection and correction (EDC) mode data, and an EDC pattern generator configured to receive pattern information and period information included in the mode data and to generate an EDC pattern signal based on the pattern information and the period information. The EDC pattern signal is a periodic signal obtained by repeating a signal pattern based on the pattern information at a periodic rate corresponding to a signal period based on the period information. In some cases, the EDC pattern signal may be disabled during a portion of the signal period.
Abstract: A memory system includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and configured to provide the nonvolatile memory device with error flag information including error location information of an error of data read from the nonvolatile memory device.
Type:
Grant
Filed:
April 18, 2012
Date of Patent:
August 19, 2014
Assignee:
SAMSUNG Electronics Co., Ltd.
Inventors:
Sang-Hyun Joo, Kitae Park, Sangyong Yoon, Jinman Han
Abstract: A calculation, prediction and validation method can include receiving a portion of a data packet in a data buffer, computing, in a processor, information related to the checksum of the data packet based on the portion of the data packet and processing the data packet in the processor.
Type:
Grant
Filed:
October 31, 2013
Date of Patent:
August 12, 2014
Assignee:
International Business Machines Corporation
Inventors:
Carl A. Bender, Michael J. Cadigan, Jr., Nihad Hadzic, Howard M Haynie, Jeffrey M. Turner, Raymond Wong
Abstract: Systems and methods are disclosed herein for identifying an anomaly in a signal, where samples in the signal correspond to an amount of data flow in a network within a time interval, and an anomaly corresponds to at least one sample in the discrete signal having a likelihood value below a likelihood threshold. A historical probability distribution of the discrete signal is generated based on previously received samples. For each sample in a plurality of samples in the discrete signal, a likelihood is computed based at least in part on the historical probability distribution. A likelihood threshold is selected, and a set of consecutive samples is identified as an anomaly when each sample in the set has a computed likelihood below the likelihood threshold.
Abstract: A detection signal transmitting unit 123 of a first component 110 transmits a plurality of detection signals having different frequency spectrums to a second component 210. Upon receiving the detection signals, a detection signal returning unit 233 of the second component 210 returns, as return signals, respective signal waveforms of the received detection signals to the first component 110. A detection signal judging unit 126 of the first component 110 judges authenticity of the received return signals based on the transmitted detection signals. When the judging unit judges that the received return signals are not authentic, a tamper-resistance control unit 127 adds a restriction to the communication performed between the first component 110 and the second component 210.
Abstract: Embodiments of systems and methods for detecting errors that occur in association with an access to a memory and providing an associated error status are presented herein. According to one embodiment, an access to a memory may be received, where the access comprises a request tag. A request parity is determined based on the request tag and a stored tag and a stored parity associated with the request tag are also determined. An error correction status is determined based on the stored tag and the stored parity associated with the request tag. Additionally, a parity hotness is determined by comparing the request parity and the stored parity and a tag hotness is determined by comparing the request tag and the stored tag. An error status associated with the access is determined based on the parity hotness, the tag hotness and the error correction status.
Abstract: A controller of a storage control apparatus creates a fixed value, which is one or higher values conforming to a prescribed data pattern, with respect to first data, which is smaller than the size of a storage area of a storage device, creates a guarantee code related to a data area comprising the first data and the fixed value, and writes the data group comprising the data area and the guarantee code to the storage area. The controller reads a data group from the storage area, and determines whether or not more errors than the number of errors correctable by the guarantee code are included in this data group. In a case where the result of this determination is affirmative, the controller determines whether or not an error exists in the fixed value inside the data group.
Abstract: A method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. In one embodiment of the invention, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction.
Type:
Grant
Filed:
July 12, 2013
Date of Patent:
July 29, 2014
Assignee:
Intel Corporation
Inventors:
Steven R. King, Frank L. Berry, Michael E. Kounavis
Abstract: An apparatus and method for reducing power consumption of a receiver by performing a Hybrid Automatic Repeat reQuest (HARQ) according to a detected decoding error are provided. The apparatus includes a decoding reliability metric generator for setting a decoding result as a decoding reliability metric, which is a reference value for determining a code block having a decoding error, based on a decoding result, a decoding reliability metric buffer for storing the decoding reliability metric set by the decoding reliability metric generator and a code block controller for, when the decoding error occurs, identifying code blocks having the decoding error by checking the decoding reliability metric and for controlling to decode the identified code blocks.
Abstract: A method is for processing transmission errors during contactless communication of information between a device and a reader. The information may be transmitted in the form of frames sent to a send/receive module of the reader in contactless coupling with the device and controlled by a control module coupled to the send/receive module. The information may be extracted from the frames within the send/receive module so as to be delivered to the control module. The method may include a detection of transmission errors that are to be ignored.
Type:
Application
Filed:
January 14, 2014
Publication date:
July 24, 2014
Applicants:
MELEXIS TECHNOLOGIES NV, STMICROELECTRONICS (ROUSSET) SAS
Abstract: A method for decoding a channel signal in a signal reception apparatus is provided. The method includes performing a block decoding operation on a channel signal block, and if the block decoding for the channel signal block fails, re-performing a block decoding operation on the channel signal block using a preset pattern.
Abstract: A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.
Type:
Application
Filed:
January 15, 2013
Publication date:
July 17, 2014
Applicant:
INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventors:
William V. Huott, Kevin W. Kark, John G. Massey, K. Paul Muller, David L. Rude, David S. Wolpert
Abstract: An apparatus and method for transmitting and receiving data in a wireless communication is provided. The method includes determining a number of zero-padding bits, determining a number (Npad) of bit groups in which all bits are padded with zeros, padding the all bits within 0th to (Npad?1)th bit groups indicated by a shortening pattern with zeros, mapping information bits to bit positions which are not padded in Bose Chaudhuri Hocquenghem (BCH) information bits, BCH encoding the BCH information bits to generate Low Density Parity Check (LDPC) information bits, and LDPC encoding the LDPC information bits to generate a zero-padded codeword, wherein the shortening pattern is defined as an order of bit groups defined as 6, 5, 4, 9, 3, 2, 1, 8, 0, 7, 10 and 11.
Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.
Type:
Grant
Filed:
April 18, 2012
Date of Patent:
July 15, 2014
Assignee:
LSI Corporation
Inventors:
Shaohua Yang, Yang Han, Chung-Li Wang, Mikhail I. Grinchuk, Anatoli A. Bolotov, Lav D. Ivanovic
Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.
Type:
Grant
Filed:
April 11, 2012
Date of Patent:
July 15, 2014
Assignee:
LSI Corporation
Inventors:
Santosh Narayanan, Benzeer Bava Arackal Pazhayakath, Vishal Deep Ajmera, Sandesh Kadirudyavara Ven Gowda
Abstract: An error correction data processing apparatus includes a noise predictive calibration circuit operable to calibrate a first set of filter coefficients based on a first data set and a second set of filter coefficients based on a second data set, and includes a first noise predictive detector operable to receive the first set of filter coefficients. The apparatus further includes a decoder operable to perform a first global iteration with the first noise predictive detector and determine a violation check count value, and a second noise predictive detector operable to receive the second set of filter coefficients if the violation check count value is less than a predetermined value or receive the first set of filter coefficients if the violation check count value is greater than the predetermined value.
Type:
Grant
Filed:
June 26, 2012
Date of Patent:
July 15, 2014
Assignee:
LSI Corporation
Inventors:
Yang Han, Shaohua Yang, Fan Zhang, Zongwang Li
Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include: a data decoder circuit, a decoder log, a mis-correction detection circuit, and a controller circuit.
Abstract: Disclosed herein is a semiconductor integrated circuit capable of detecting an abnormality that can cause a malfunction in signal transmission via an isolation element and of issuing a stop signal to the target to be controlled. The semiconductor integrated circuit includes a transmission circuit generating and outputting a transmission signal reflecting transmission data supplied from outside, a reception circuit reproducing the transmission data based on a reception signal, an isolation element isolating the transmission circuit from the reception circuit and transmitting the transmission signal as the reception signal, an abnormality detection part detecting an abnormality that can cause a malfunction in signal transmission via the isolation element, and a control part outputting a stop signal if the abnormality detection part detects the abnormality, regardless of the transmission data supplied to the transmission circuit from outside.
Abstract: The present invention is directed to a method of estimating a motor rotation angle that does not affect precision of a detected angle of a crank angle sensor, which is an alternative sensor, when abnormality occurs in a resolver and a peripheral circuit, and performing a motor control without failure of an inverter or peripheral device. A vehicle system includes a motor, a resolver detecting a rotor rotation angle of the motor, a motor control circuit controlling the motor based on information on rotor rotation angle and torque command value, an engine connected to the motor through a crankshaft, and a crankshaft sensor detecting revolutions of the crankshaft, in which the motor control circuit estimates rotor rotation angle based on a variation rate of the number of revolutions of the crankshaft when abnormality of the resolver is detected, and performs a weak field control based on estimated rotor rotation angle.
Abstract: Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors.
Type:
Grant
Filed:
May 7, 2012
Date of Patent:
July 8, 2014
Assignee:
LSI Corporation
Inventors:
Chung-Li Wang, Lei Chen, Fan Zhang, Shaohua Yang, Johnson Yen
Abstract: An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a plurality data bits by a plurality of minimal polynomials of an encoding along a first path and (ii) generate a plurality of parity bits by multiplying the intermediate bits by the minimal polynomials along a second path. A number of the parity bits may be variable based on a configuration signal. The second circuit may be configured to (i) delay the data bits and (ii) generate a plurality of code bits by appending the parity bits to a last of the data bits.
Type:
Grant
Filed:
January 17, 2012
Date of Patent:
July 8, 2014
Assignee:
LSI Corporation
Inventors:
Pavel A. Panteleev, Elyar E. Gasanov, Ilya V. Neznanov, Andrey P. Sokolov, Yurii S. Shutkin
Abstract: Techniques are provided for receiving a transmitted first packet that was formatted using a known scrambling algorithm with an unknown scrambling seed. An encoded packet payload is extracted from the first packet header. The encoded packet payload header is decoded to obtain a first scrambled packet payload header. For each potential value of the unknown seed, the first scrambled packet payload header is descrambled to produce a first set of descrambled packet payload headers and for each potential value of initial register values associated with a cyclic redundancy check, the cyclic redundancy check is executed comprising polynomial division on each of the descrambled packet payload headers such that when the polynomial division results in a zero remainder, a potential unscrambled payload header for the first packet is obtained. Information about the first packet is obtained from the potential unscrambled payload header.
Type:
Grant
Filed:
January 3, 2012
Date of Patent:
July 8, 2014
Assignee:
Cisco Technology, Inc.
Inventors:
Raghuram Rangarajan, David Kloper, Yohannes Tesfai
Abstract: A method includes detecting a failure condition relating to a first distributed mobile architecture (dMA) gateway (dMAG) at a dMAG management system. The dMAG management system is in communication with at least the first dMAG, a second dMAG, and dMA nodes. The method also includes determining that the first dMAG is offline based on the failure condition, selecting the second dMAG, sending a first notification from the dMAG management system to the second dMAG, and sending a second notification from the dMAG management system to an external system. The external system is configured to connect calls to a mobile station via the first dMAG. The first notification instructs the second dMAG to take over operations from the first dMAG. The second notification indicates that the external system is to connect subsequent calls to the mobile station via the second dMAG.
Abstract: A method and an apparatus for data management through timer compensation in a wireless communication system are provided. In the method, when a data loss occurs at a first point, whether a data loss has occurred previously and so whether a timer is being driven are determined. Whether the driven timer stops or expires at a second point is determined. When the timer stops or expires at the second point, a timer value is compensated for with consideration of a time difference between the first point and the second point. A timer for the data loss of the first point is restarted based on the compensated timer value. Therefore, a delay of a retransmission request time for lost data in an RLC (Radio Link Control) layer may be minimized.
Abstract: Systems and methods for adaptively operating a storage device are provided. A level of integrity of storing data in the storage device is determined. A coding scheme is selected based on the determined level of integrity of the storage device. An operation is performed on the storage device using the selected coding scheme.
Abstract: One embodiment of the present invention provides a system that facilitates transmission buffer under-run protection. During operation, the system stores bits of a data frame in a transmission buffer associated with an output port. The system also monitors the state of the transmission buffer and commences transmission of the data frame to the output port prior to complete reception of the data frame in the transmission buffer. The system further determines that the amount of data stored in the transmission buffer is below a predetermined threshold and inserts a number of predetermined unique bit sequences after the partially transmitted data frame, thereby allowing a receiving device to temporarily suspend reception of the data frame and resume reception at a later time without dropping the data frame.
Abstract: A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.
Type:
Grant
Filed:
June 6, 2012
Date of Patent:
June 10, 2014
Assignee:
Mellanox Technologies Ltd.
Inventors:
Michael Kagan, Noam Bloch, Ariel Shachar
Abstract: A system is provided for generating data packets of a message according to a first protocol, then analyzing the message according to a second protocol. The system determines if the message provides a correct checksum according to the second protocol. If the message provides the correct checksum according to the second protocol, the system alters the message and transmits the message according to the first protocol.
Type:
Grant
Filed:
January 13, 2011
Date of Patent:
June 10, 2014
Assignee:
Continental Automotive Systems, Inc.
Inventors:
Jean-Christophe Deniau, Brian J. Farrell, Yasser Gad
Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing.
Abstract: Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to decode codewords and decoder firmware configured to control one or more decoding parameters of the decoder. The decoder includes a recovery unit configured to store recovery instructions. The decoder is further configured to execute the stored recovery instructions without interaction with the decoder firmware when the decoding fails.
Abstract: A semiconductor apparatus includes a delay circuit to apply delay to an input signal, a phase detector to detect a phase of an output signal which is outputted from the delay circuit, a filter to set a range of the phase of the output signal for stable operation based on phase information outputted from the phase detector, a counter to count a number of detections of the output signal when the phase deviates from the range for stable operation, a discount controller to generate a discount signal indicating a discount number for the number counted by the counter, in accordance with an operating condition or an external factor outside the delay circuit and an error detector to determine whether or not an error of the phase of the output signal has occurred based on the number counted by the counter and a discount number indicated by the discount signal.
Abstract: According to one aspect of the present disclosure, a method and technique for hierarchical network failure handling in a clustered node environment is disclosed. The method includes: detecting a network failure by a node in a cluster, the cluster having plural nodes arranged in a hierarchy, wherein the network failure is associated with a subordinate node in the hierarchy to the detecting node; communicating the network failure from the detecting node to a superior node in the hierarchy; determining whether the network failure affects nodes higher than the detecting node in the hierarchy; and responsive to determining that the network failure does not affect nodes higher than the detecting node in the hierarchy, the detecting node initiating a protocol to expel the subordinate node from the cluster.
Type:
Grant
Filed:
August 12, 2011
Date of Patent:
June 3, 2014
Assignee:
International Business Machines Corporation
Inventors:
William B. Brown, David J. Craft, Robert K. Gjertsen