Abstract: Method and apparatus to efficiently detect/correct memory errors. A command and an address associated with a data transaction may be received. Parity information associated with the command/address may be received. In response to detecting a parity error, a data array of a memory device may be locked. An indicator indicating the parity error may be sent. A first portion of a memory page to store data may be reserved. A second portion of the memory page to store error correction codes associated with the data may be reserved. The second portion's size may equal or exceed the error correction code capacity needed for the maximum possible data stored in the first portion. A cache line of data may be stored in the first portion. An error correction code associated with the cache line of data may be stored in the second portion.

Abstract: Aspects of the disclosure pertain to a system and method for promoting improved error detection efficiency in a Content-Addressable Memory (CAM). The system and method provide CAM continuous error detection with interleave parity. The system continuously monitors for changes in cell contents and, when (e.g., as soon as) a soft error occurs, the error detection output bit for that entry will change, causing an error flag at chip level. The system can then immediately stop compare operations and rewrite the failing entry. Separate read operations are not needed to check for errors, thereby decreasing overall dynamic power usage and increasing possible search frequency for the system.

Abstract: A multiple access scheme is described. One or more encoders are configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding. The bit streams correspond to a respective plurality of terminals. The plurality of bit streams are converted to provide a multiple access scheme for the terminals.

Abstract: Each of (n?1) 2-bit checking units, where n is an integer larger than or equal to 4, receives n-bit redundant encoded data generated from 1-bit input data, and outputs 2-bit check data based on a result of comparison between bits of the encoded data, combinations of the bits differing in each comparison. An all-bit checking unit outputs all-bit check data based on exclusive ORs of all-bit of the encoded data. An error detecting unit detects errors in the encoded data on the basis of the (n?1) sets of 2-bit check data and the all-bit check data, and outputs the input data on the basis of the result of error detection.

Abstract: According to one embodiment, a storage device includes an error detector, a check module, and a replacement module. The error detector detects a bit error that occurs in entry data related to conversion to a physical address corresponding to a logical address based on an error detecting code assigned to the entry data. The check module checks, based on data obtained by inverting one bit among all bits of the entry data and on data read out from the physical address indicated by the obtained data, whether or not the obtained data is normal entry data. The replacement module replaces the entry data where the bit error is detected with the checked normal entry data.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing with soft guaranteed global processing iterations.

Abstract: A memory device electrically connectable to a host circuit receives, from the host circuit, data including a first actual data to be written into the first memory area; acquires first parity data associated with the first actual data; generates second actual data that is a copy of the first actual data, and second parity that is a copy of the first parity data; writes the first actual data and the first parity data into the first memory area, and writes the second actual data and the second parity data into the second memory area; and reads the first actual data, the first parity data, the second actual data, and the second parity data from the data memory section for transmission to the host circuit.

Abstract: An input power measuring device includes a board with an edge connector, a first dual inline memory modules (DIMM) socket, a resistor, a differential amplifier circuit, a voltage dividing circuit, a display screen, and a controller. When the edge connector is inserted into a second DIMM socket of a motherboard and the motherboard is powered on, the resistor samples first current, and converts the first current into a first voltage. The differential amplifier circuit amplifiers the first current to a second current. The voltage dividing circuit divides the first voltage, and outputs a second voltage. The controller converts the second current into a third current, converts the second voltage into a third voltage, and calculates a power according to the third current and the third voltage.

Abstract: According to one embodiment, an error correction channel determination module determines, a channel to be allocated to a logical page as an error correction channel so that each of a plurality of channels is allocated to a uniform number of logical pages as the error correction channel. A command list generation module generates a list of write commands each specifying that a corresponding logical page is to be written using, in parallel, channels included in the plurality of channels and excluding the error correction channel, based on the determination of the channel to be allocated to the corresponding logical page as the error correction channel. A command list issue module issues the list of the write commands.

Abstract: A cache memory is operated in a write through system, and an operation to be performed when a cache mishit occurs is performed when corresponding data is not stored in the cache memory, or only when an error occurs although there is the data. Then, a bit indicating that a soft error has occurred before is set in the cache memory, and when the bit indicates “1” and if an error has occurred again, it is determined that a hardware error has occurred, and an interrupt is generated in the CPU. The bit is to be reset at time intervals sufficiently shorter than the frequency at which it is considered that a soft error occurs.

Abstract: Disclosed herein is a coding apparatus handling quasi-cyclic codes in which a given code word cyclically shifted by p symbols provides another code word, wherein parallel processing is executed in units of mp (a multiple of p) symbols; mp generator polynomials are used; and the generator polynomials gj(x) are selected such that a coefficient of degree deg(gi(x)) of x becomes zero for all gi(x) lower in degree than that and circuits in which these generator polynomials gj(x) are combined are connected with each other.

Abstract: A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.

Abstract: Methods and apparatus are provided for recording input data in q-level cells of solid-state memory (2), where q>2. Input data words are encoded as respective codewords, each having a plurality of symbols. The coding scheme is such that each symbol can take one of q values corresponding to respective predetermined levels of the q-level cells, and each of the possible input data words is encoded as a codeword with a unique sequence of relative symbol values. The symbols of each codeword are then recorded in respective cells of the solid-state memory by setting each cell to the level corresponding to the recorded symbol value. Input data is thus effectively encoded in the relative positions of cell levels, providing resistance to certain effects of drift noise.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection.

Abstract: Systems and methods for maximizing a number of available states for a version number used for memory corruption detection. A physical memory may be a DRAM comprising a plurality of regions. Version numbers associated with data structures allocated in the physical memory may be generated so that version numbers of adjacent data structures in a virtual address space are different. A reserved set and an available set of version numbers are associated with each one of the plurality of regions. A version number in a reserved set of a given region may be in an available set of another region. The processor detects no memory corruption error in response to at least determining a version number stored in a memory location in a first region identified by a memory access operation is also in a reserved set associated with the first region.

Abstract: An SRAM memory device including a plurality of memory cells arranged in a plurality of rows and a plurality of columns; each row of memory cells is adapted to store a RAM word; the RAM word includes a corresponding data word, a corresponding ECC word to be used for error detection and correction purposes and a corresponding applicative word to be used during debugging operations. The SRAM memory device further includes a configurable port adapted to receive a RAM word and to program corresponding memory cells of a selected row based on the received RAM word during a writing access of the SRAM memory device. The SRAM memory device further includes a memory controller unit including circuitry for selectively configuring the configurable port in one among a plurality of modes.

Abstract: The invention realizes a semiconductor memory device that can efficiently execute a detection of a data error that might possibly occur in a continuous reading action, and a correction of the error data. The semiconductor memory device uses a variable resistive element made of a metal oxide for storing information. During a reading action of coded data with an ECC in the semiconductor memory device, when a data error is detected by an ECC circuit, a writing voltage pulse having a polarity opposite to a polarity of a reading voltage pulse is applied to all memory cells from which the error is detected so as to correct bits from which the error is detected, on an assumption that an erroneous writing has occurred due to the application of the writing voltage pulse having the polarity same as the polarity of the applied reading voltage pulse.

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract: Subject matter disclosed herein relates to methods and/or apparatuses, such as an apparatus that includes first and second groups of memory cells. The first group of memory cells stores multiple digits of program data per memory cell. The second group of memory cells stores a parity symbol per memory cell. Other apparatuses and/or methods are disclosed.

Abstract: A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.

Abstract: A method of storing data includes receiving general purpose (GP) data and special Error Tolerant or Streaming (ETS) data, storing the GP data using a data storage method, and storing the ETS data using a different data storage method which affects the access rate, resilience to errors, data integrity, storage density, or storage capacity. The storage medium, which can include a disk drive, flash memory, or holographic memory, is utilized differently depending on the required Quality of Service in aspects including block size, storage of error correction codes, utilization of error correction codes, storage area density, physical format pattern, storage verification, or reaction to failed storage verification. For disk drives these differences include spacing between tracks; overlap between tracks; spiral track formatting; concentric track formatting, and size of blocks, and for flash memories these differences include levels per cell and number of cells.

Abstract: A method, system and device for monitoring error code of CPRI link are disclosed. The method comprises: a CPRI link data transmitting end forming data to be transmitted into frames, outputting data, and calculating to obtain FCS of each frame; the CPRI link data transmitting end adds FCS of a former frame into FCS field of a current frame when forming frame; a CPRI link data receiving end splitting frame of received frame data to obtain FCS of the former frame carried in the current frame, calculating received frame data to obtain FCS of the current frame, caching FCS of the current frame, comparing FCS of the former frame which is carried in the current frame with cached FCS of the former frame, and judging CPRI link has error codes if the comparison result is inconsistent. Error code condition of CPRI link can be monitored without influencing normal service operation.

Abstract: A system and a method detects errors when writing data to a memory in a computer system. An error detection memory write request for writing an error detection value to a memory location within the memory section is issued, the error detection value being associated with the block of data. A data memory write request for writing the block of data to the memory section is issued such that at least part of the block of data is written to the memory location. A check is performed to determine whether the error detection value in the error detection memory write request corresponds to the block of data in the data memory write request.

Abstract: Methods and apparatus are provided for reading and writing data in q-level cells of solid-state memory, where q>2. Input data is encoded into codewords having N qary symbols, wherein the symbols of each codeword satisfy a single-parity-check condition. Each symbol is written in a respective cell of the solid state memory by setting the cell to a level dependent on the qary value of the symbol. Memory cells are read to obtain read signals corresponding to respective codewords. The codewords corresponding to respective read signals are detected by relating the read signals to a predetermined set of N-symbol vectors of one of which each possible codeword is a permutation.

Abstract: This disclosure relates generally to data decoding, and more particularly to iterative decoders for data encoded with a low-density parity check (LDPC) encoder. LDPC decoders are disclosed that use reduced-complexity circular shifters that may be used to decode predefined or designed QC-LDPC codes. In addition, methods to design codes which may have particular LDPC code performance capabilities and which may operate with such decoders using reduced-complexity circular shifters are provided. The generation of quasi-cyclic low density parity check codes and the use of circular shifters by LDPC decoders, may be done in such a way as to provide increased computational efficiency, decreased routing congestion, easier timing closure, and improved application performance.

Abstract: Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.

Abstract: A serial interface device includes multiple serial link connections that receive at least address values and at least one error detection code (EDC) on different serial link connections, the EDC generated from at least the address values, the serial link connections for the address values and EDC operated separately from one another; and multiple output serial links, at least a first one of the output serial links outputting data values read from memory locations corresponding to the address values, and at least a second one of the output serial links different from and operated separately from the first one outputting EDC values generated for the data values read from the memory locations.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: Values are grouped into a first set of groupings of values. Based on inner codes, the number of groupings in the first set of groupings that have at least one erroneous value is determined. If the number of groupings in the first set of groupings that have an erroneous value is fewer than a maximum number of groupings that can be corrected by outer codes, a seek operation is begun. During the seek operation, the outer codes are used to detect and correct the erroneous values that were produced during the reading of values. In other aspects, a parity section for a data section of a data storage device is dirtied before writing any data to the data section such that if writing to the data section is interrupted, the parity section will indicate that it should not be used to correct data read from the data section.

Abstract: A parity pattern defines a repeated distribution of parity blocks within a distributed parity disk array (“DPDA”). The parity pattern identifies on which disks the parity block or blocks for a stripe are located. When a new disk is added to the DPDA, the parity pattern is modified so that the distribution of parity blocks within the parity pattern is even. Parity blocks within the DPDA are then redistributed to conform with the modified parity pattern.

Abstract: A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.

Abstract: A disk controller comprising a disk formatter configured to receive data being transferred between a disk and a host. A buffer controller is in communication with the disk formatter, a buffer configured to store the data being transferred between the disk and the host, and the host. The buffer is external to each of the disk controller and the host. The buffer controller is configured to regulate transfer of the data between the buffer and the disk formatter. An error correction module is in communication with the disk formatter and the buffer controller. The error correction module is configured to generate an error correction mask to correct errors in the data. The error correction mask is applied to the data prior to the buffer controller transferring the data to the buffer.

Abstract: An approach is provided for processing structure Low Density Parity Check (LDPC) codes. Memory storing edge information and a posteriori probability information associated with a structured parity check matrix used to generate Low Density Parity Check (LDPC) coded signal are accessed. The edge information represent relationship between bit nodes and check nodes, and are stored according to a predetermined scheme that permits concurrent retrieval of a set of the edge information.

Abstract: A memory device may include a memory plane including a group of memory cells configured to store a block of bits including data bits and parity bits, and a detector for detecting a fault injection including a reader to read each bit, and a first checker to perform, when reading a block, a parity check based on the read value of each data and parity bit. The memory plane may include reference memory cells arranged between some of the memory cells to create packets of m memory cells. Each reference memory cell may store a reference bit and each packet of m memory cells may store m bits of the associated block, when m is greater than 1, with different parities. The detector may further include a second checker to perform, when reading the block, a check on the value of each reference bit.

Abstract: A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.

Abstract: One or more embodiments of the invention set forth techniques to perform integer division using addition operations in order to provide address translation capabilities to a processor. The processor supports a memory that maintains checksum information such that address requests received by the processor need to be translated to a checksum address and an actual data address that accounts for use of portions of the memory to store checksum information. Once the checksum address and the actual data address are computed, the processor can confirm the integrity of the data stored in the actual data address and correct any errors if need be, based on the checksum information stored in the checksum address.

Abstract: A semiconductor memory apparatus includes: a memory cell area including a plurality of memory cell arrays stacked therein, each memory cell array having a plurality of memory cells integrated and formed therein to store data and a plurality of through-lines formed therein to transmit signals; and a control logic area configured to generate parity bits using a data signal inputted to the memory cell area and transmit the generated parity bits and the data signal to different through-lines.

Abstract: A device includes a tag cache memory array; a pre-parity unit configured to receive an address, and calculate and output a pre-parity bit calculated from all bits of the address. A comparator is configured to compare a tag read from the tag cache memory array with the address, and output a read-hit bit. The read-hit bit is true when the tag and the address are identical, and is false when the tag and the address are not identical. The device further includes a simplified parity-check unit configured to receive and perform operations on the pre-parity bit, the read-hit bit, and a parity bit from the tag cache memory array, and to output a read-parity bit.

Abstract: An apparatus to manage data stability, including a plurality of storage units and a control unit to determine when protected data is stored in a particular address row of at least one of the plurality of storage units, to select another storage unit of the plurality of storage units to store the protected data, and to store relevance data related to the protected data in the same address row of the selected storage unit. Methods of storing and recover data also included.

Abstract: Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.

Abstract: Mechanisms for ensuring data consistency in a data store are provided. The mechanisms access a parity scrub factor f and perform a check on a data group of the data store. The check on the data group includes performing a parity check on a portion of the data group, the portion being equal to 1/f of the data group, and performing a data verify on the remainder of the data group. The performing of the check is repeated for the entire data store. An offset factor is used to select the portion of the data group for the parity check. In this case, the offset factor may be incremented when the performance of the check on the data group of the data store has been repeated for the entire data store.

Abstract: A system for transmission of signals between modules wherein, for example, it is possible to transmit reliably, between modules, information relating to, for example, the actuation of safety devices. A transmission module for transmitting a pulse signal of a specific period, which indicates the existence of information, generates, in time division, pulse signals by a plurality of signal generating units that are provided in parallel, and then combines these pulse signals into a single time series pulse signal. Then an attempt is made to output this pulse signal towards a receiving-side module through a relay for controlling the output, and the signals appearing at a normally-open terminal and at a normally-closed terminal of the relay are monitored to determine whether or not there is a failure, where the generation of the pulse signal is stopped when a failure is detected.

Abstract: Methods and apparatus for performing parity and/or ECC operations are disclosed. An example method includes determining that an opcode is being transmitted on a bus and determining if the transmitted opcode is a memory operation. In the event the transmitted opcode is a memory write operation, the example method includes calculating a parity bit for data associated with the opcode, writing the calculated parity bit to a parity table and writing the data to a memory. The example method also includes, in the event the transmitted opcode is the memory read operation, recovering data from a previously written memory, calculating a parity bit for the recovered data, recovering a previously stored parity bit for the recovered data, comparing the parity bit for the recovered data with the previously stored parity bit and, in the event the recovered data parity bit does not match the previously stored parity bit, providing an error notification.

Abstract: A wireless communication device includes a transmitter configured to transmit a transport block with a sequence of bits wherein A is the number of bits, a first CRC coder configured to generate a first block of CRC parity bits on a transport block and to associates the first block of CRC parity bits with the transport block, wherein a number of CRC parity bits in the first block is L, a segmenting entity configured to segment the transport block into multiple code blocks after associating when A+L is larger than 6144, a second CRC coder configured to generate a second block of CRC parity bits on each code block and to associate a second block of CRC parity bits with each code block, and a channel encoder configured to encode each of the code blocks including the associated second block of CRC parity bits if A+L>6144.

Abstract: Values are grouped into a first set of groupings of values. Based on inner codes, the number of groupings in the first set of groupings that have at least one erroneous value is determined. If the number of groupings in the first set of groupings that have an erroneous value is fewer than a maximum number of groupings that can be corrected by outer codes, a seek operation is begun. During the seek operation, the outer codes are used to detect and correct the erroneous values that were produced during the reading of values. In other aspects, a parity section for a data section of a data storage device is dirtied before writing any data to the data section such that if writing to the data section is interrupted, the parity section will indicate that it should not be used to correct data read from the data section.

Abstract: Techniques are described to store and retrieve an encoded info bit stream, and appropriate first and second sets of parity bits to perform interleaving and rate matching, prior to transmission. On the receiver side, a recovery technique is provided which operates on the same principle as that of encoding, but decoding occurs in reverse. In accordance with an exemplary embodiment, three dedicated logical memories are provided for each of the encoded info bit stream and two sets of parity bits, respectively. The proposed solution provides an alternative methodology and/or hardware implementation for performing LTE compliant rate matching and de-rate matching when required to interleave info bits and parity bits.

Abstract: An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.

Abstract: MDS array codes are widely used in storage systems to protect data against erasures. The rebuilding ratio problem is addressed and efficient parity codes are proposed. A controller as disclosed is configured for receiving configuration data at the controller that indicates operating features of the array and determining a parity code for operation of the array according to a permutation, wherein the configuration data specifies the array as comprising nodes defined by A=(ai,j) with size rm×k for some integers k, m, and wherein for T={v0, . . . , vk?1}Zrm a subset of vectors of size k, where for each v=(v1, . . . , vm)?T, gcd(v1, . . . , vm, r), where gcd is the greatest common divisor, such that for any l, 0?l?r?1, and v?T, the code values are determined by the permutation fvl:[0,rm?1]?[0,rm?1] by fvl(x)=x+lv.