Abstract: An estimating unit estimates, when there is a request for data in a system in which an error checking unit of data is formed with a plurality of memories each of which is a dual memory having an independent address line, whether an error has occurred on the address line based on a result of an error checking for data related to the request. A control unit generates, when it is estimated that an error has occurred on the address line, error data of the data related to the request, and controls the memory in such a manner that one line of the dual memory is disabled by switching the data related to the request to generated error data.

Abstract: A dynamic parity distribution system and technique distributes parity across disks of an array. The dynamic parity distribution system includes a storage operating system that integrates a file system with a RAID system. In response to a request to store (write) data on the array, the file system determines which disks contain free blocks in a next allocated stripe of the array. There may be multiple blocks within the stripe that do not contain file system data (i.e., unallocated data blocks) and that could potentially store parity. One or more of those unallocated data blocks can be assigned to store parity, arbitrarily. According to the dynamic parity distribution technique, the file system determines which blocks hold parity each time there is a write request to the stripe. The technique alternately allows the RAID system to assign a block to contain parity when each stripe is written.

Abstract: An circuit arrangement and method for reducing the number of processing loops needed to generate an error correction parameter used in the Montgomery method. An initial input to a processing loop is set to a value equal to the modulus, left shifted one register position. Values of the working register are shifted multiple positions during a single loop iteration, and a shifted result is subtracted and compared to zero to determine subsequent contents of the working register.

Abstract: A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.

Abstract: A method that measures a skew between a data signal and a clock signal at a receiving end of a serial link and then adjusts a phase relationship between the data signal and the clock signal to reduce the skew.

Abstract: One embodiment disclosed relates to a method of visually locating a memory module. An electronic communication is received by circuitry on the memory module to be visually located. A beacon state in the memory module is activated due to receipt of the electronic communication. A beacon device on the memory module is electronically turned on when the beacon state is activated to draw attention to that memory module. Another embodiment disclosed relates to an apparatus to visually locate a memory module in a memory system with a plurality of memory modules. The apparatus includes a system board, a plurality of memory modules, and an LED unit on a memory module. The beacon unit includes a beacon device and control circuitry for turning on the beacon device when an electronic communication to turn on the beacon device is received by that memory module.

Abstract: A method and apparatus for operating a content addressable memory (CAM) and a ternary CAM (TCAM) are described including an encoding circuit for encoding an incoming CAM or TCAM word to produce an encoded CAM or TCAM word such that a one-bit mismatch between a comparand and the incoming CAM or TCAM word results in at least a M-bit mismatch between said encoded CAM or TCAM word and a similarly encoded comparand, a circuit for precharging a match line to a predetermined state before a comparison between the encoded CAM or TCAM word and said similarly encoded comparand and a memory storage location for storing the encoded CAM or TCAM word.

Abstract: A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.

Abstract: A parity generation circuit includes a plurality of bit-generation circuits. Each bit-generation circuit receives respective data bits and a respective hard latch signal, and operates to generate a parity signal indicating the parity of the corresponding data bits when the hard latch signal is inactive. Each bit-generation circuit drives the parity signal to a set value when the hard latch signal is active. An output circuit is coupled to the bit-generation circuits to receive the parity signals and operates to generate an output parity signal in response to the parity signals from the bit-generation circuits.

Abstract: An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix.

Abstract: Methods for increasing defect tolerance and fault tolerance in systems containing interconnected components, in which a signal level is classified as belonging to one of a plurality of different, distinguishable classes based on one or more thresholds separating the signal-level classes, and defect-and-fault tolerant systems embodying the methods. An electronic-device embodiment including an array of nanowire crossbars, the nanoscale memory elements within the nanowire crossbars addressed through conventional microelectronic address lines, and a method embodiment for providing fault-tolerant interconnection interfaces with electrically distinguishable signal levels are described.

Abstract: A two-dimensional parity method and system for rotating parity information in a disk array, such as a RAID, to provide multiple disk fault tolerance with reduced write bottlenecks, is presented. The method includes forming a plurality of blocks, each block comprising a plurality of stripes extending across multiple disks, reserving at least one stripe in each block for parity, dividing each block into a plurality of chunks, wherein at least one of the chunks in the block comprises parity information, and shifting the position of each parity chunk in each block to a different disk with respect to the parity chunk in adjacent blocks. The method further includes shifting the position of each parity strip in the at least one stripe in each block to a different disk with respect to the parity chunk in adjacent blocks. A system for translating information in a disk array includes an array controller configured to shift parity chunks and parity strips.

Abstract: A system for maintaining cyclic redundancy check (“CRC”) protection of XOR'ed data sectors includes a register that is initialized with a non-zero seed value used for generating sector CRC values. The system includes logic for combining CRC values of at least two sectors and storing a result of the combination modified with a non-zero seeded CRC value.

Abstract: The present invention is broadly directed to a memory system comprising a a host integrated circuit component, at least two data memories, at least one parity memory for storing parity information corresponding to data stored in a corresponding address space of the data memories, and at least two controller integrated circuits. Each controller integrated circuit (IC) comprises memory control logic configurable to control communications between the controller IC and data memories directly connected to the controller IC, parity logic configurable to compute parity information for data communicated to or from the data memories, logic configurable to communicate the parity information to or from a companion IC, and logic configurable to communicated data to or from a companion IC.

Abstract: A method and apparatus is provided for handling parity errors within a data processing system. Each occurrence of a parity error is attributed to an addressable memory location or a block of memory locations that was being accessed when the error occurred. A memory location or a memory block is marked as unusable after a predetermined number of errors is attributed to that location or block, respectively. The predetermined number of errors that is allowed to occur prior to degradation could be two, or more. In one embodiment, the predetermined number of errors resulting in memory degradation is programmable.

Abstract: A system, method, and apparatus are disclosed for storing segmented data and corresponding parity data with modules configured to functionally execute the necessary steps of storing segmented data and corresponding parity data. These modules, in the described embodiments, include a designation module that designates a first set of data, from parity data and a plurality of segmented data, as surplus data and designates the remaining data as primary data. A storage module stores the primary data in main electronic storage devices in a distributed manner and stores a first copy of the surplus data on a first main electronic storage device and a second copy of the surplus data on a second main electronic storage device. An optional auxiliary storage module selectively activates an auxiliary electronic storage device and stores the surplus data on the auxiliary storage device. Beneficially, selective activation of the auxiliary electronic storage conserves power.

Abstract: A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array.

Abstract: A system wherein data is read from, and store in, a memory, such data having associated therewith an address/control portion. The system includes a pair of controller sections, one of such sections being a primary section and the other one of the sections being a secondary section. Both such sections are configured to implement identical control logic in controlling the transfer of such data between a first port connected to the pair of control sections and a write data port. The write data port of the primary section is connected to the memory. The first port receives an address/control portion associated with the data. A checker is included for producing a no-operation (NOOP) command to the memory if logic signal produced by the pair of control logic from the address/control portion at the first port are different from one another. The memory is configured to inhibit storage of data in the memory at the data port in response to the NOOP command.

Abstract: Determining an error-correcting code (ECC) for a cache entry based at least on the data stored in the cache entry and the memory address at which the data is permanently stored is disclosed. A cache entry for a desired memory address is retrieved. The cache entry includes data and a stored ECC based on the data and a memory address. An ECC is determined based at least on the data of the cache entry and the desired memory address. If the ECC at least based on the cache entry data and the desired memory address equals the stored ECC, then the cache entry caches the desired memory address without error.

Abstract: The present invention provides a method and system for performing in-line error correction in a disk storage system. The system includes an error correction (ECC) module; and a first memory storage device, wherein the first memory storage device and the error correction module simultaneously receive data from a storage disk before being buffered for transfer to a host system. The ECC module provides error correction mask before any data is transferred from the first memory storage device to a second memory buffer.

Abstract: An address information detecting apparatus in accordance with the present invention is arranged such that a first interpolation address generating section generates a first interpolation address according to a consistent signal supplied from an address comparison section, and a second interpolation address generating section generates a second interpolation address according to an error detection signal supplied from a CRC error detecting section. When a detected address is consistent with at least either of the first and second interpolation addresses and also no error is discovered according to the error detection signal, the detected address is adopted as absolute location information, whereas in situations other than the above, the first interpolation address is adopted as the absolute location information. On this account, even if an address error is mis-detected, the malfunction of the apparatus is prevented and proper recording/reproduction can be carried out.

Abstract: A memory subsystem includes a memory controller coupled to a memory module including a plurality of memory chips via a memory bus. The memory controller may generate a plurality of memory requests each including address information and corresponding error detection information. The corresponding error detection information is dependent upon said address information. The memory module may receive each of the plurality of memory requests. An error detection circuit within the memory module may detect an error the address information based upon the corresponding error detection information and may provide an error indication in response to detecting the error.

Abstract: An error detection system for detecting errors in data output from a FIFO memory includes a first CRC generator for receiving an inbound data stream and generating a first CRC value based on a data block in the inbound data stream. A device coupled to the first CRC generator selectively inputs the data block and the first CRC value into the FIFO. A second CRC generator generates a second CRC value based on the data block after being output from the FIFO in an outbound data stream. The second CRC value indicates whether the data block contains an error.

Abstract: Mechanisms and techniques allow a data storage system to detect errors in data received for storage within the data storage system. To do so, the data storage system receives, from an originator application operating on a server computer system, portions of data which comprise an application data block which is to be written to storage in the data storage system. In conjunction with the data received at the data storage system, the data storage system also receives application error checking information which the originator application generates on the data within the application data block. The application error checking information may be, for example, checksum information embedded within one or more portions of the data which comprise the application data block. Upon receipt of the data and the application error checking information, the data storage system generates data storage error checking information on the data within all portions of data which comprise the application data block.

Abstract: A memory system and method of using same are provided. One embodiment of the system includes a semiconductor memory that is configured to include a multiplicity of memory segments. The memory segments are grouped into groups. Each of the groups includes N respective memory segments, where N is an integer number. In each respective group of memory segments, the N respective memory segments include respective data segments and a respective parity segment. Also in each respective group of memory segments, the respective parity segment in the respective group stores a respective data value P that may be calculated by a logical exclusive-or of respective data values stored in the respective data segments in the respective group.

Abstract: In one aspect of the invention is a method for robust device token management. In x+ bit computers using x bit device cards, tokens are used for managing communication requests from applications to a device by using x+ bit to x bit conversion techniques, accompanied by error checking.

Abstract: The invention provides flexible disabling of disk sets. One or more disks in a RAID subsystem may be identified as temporarily inactive. The disk or disks are then marked as inactive by setting one of a set of bits associated with each disk in the RAID subsystem. If an inactivated disk is a data disk, marking it as inactive also marks it as read only. If an inactivated disk is a parity disk, the RAID group to which it supplies parity is also inactivated and a file system must look to a mirror of the inactivated RAID subsystem for its data. When a data disk is reactivated it is marked as read/write by clearing its associated bit. When a parity disk is reactivated it is also marked as read/write by clearing its bit, however, it is not available for use until it has synchronized its operation with its mirror.

Abstract: A system and related method for calculating parity information for disk array drive failure recovery. More specifically, using eight bit coefficients and calculating parity information using valid eight bit encryption keys to produce finite field encrypted resultant multiplication. Further disclosed is a method of determining whether a potential encryption key of a particular number of bits produces valid results for all possible multiplications in determining parity values.

Abstract: A cluster system managing a plurality of disk drives as a component of a virtual RAID comprises a cluster manager and a control unit. The cluster manager converts a global command G into local commands and a parity calculate command. The control unit comprises a command conversion function means, a disk control means, a parity calculation means, and a command transfer means. The command conversion function means makes the cluster manager convert the command G into the commands. The disk control means reads/writes from/to the units to according to the commands. The parity calculation means calculates the parity according to the command. The command transfer means transfers the command to one of the computer, the disk control means and the parity calculation means according to the commands.

Abstract: A microprocessor configured to store victimized instruction and data bytes is disclosed. In one embodiment, the microprocessor includes a predecode unit, and instruction cache, a data cache, and a level two cache. The predecode unit receives instruction bytes and generates corresponding predecode information that is stored in the instruction cache with the instruction bytes. The data cache receives and stores data bytes. The level two cache is configured to receive and store victimized instruction bytes from the instruction cache along with parity information and predecode information, and victimized data bytes from the data cache along with error correction code bits. Indicator bits may be stored on a cache line basis to indicate the type of data is stored therein.

Abstract: The disclosed parity stripping technique quickly and efficiently converts a multi-byte input stream having parity bits to an output data stream that contains the same data as the input stream but without the parity bits. The multi-byte input stream is indexed according to the number of times a loop is completed. During each iteration of the loop, a portion of the input steam having an associated parity bit, such as a byte of the input stream, has its parity bit set to zero and the portion of the input key is then shifted a number of bits equal to the number of times the loop has been completed. The shifted value is then logically ORed with the portion of the memory used to hold the output data stream.

Abstract: An embedded DRAM ECC architecture for purging data errors is disclosed. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation in order to identify parity failure for the word. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

Abstract: A method for correcting an error in N:N+1 channel codes categorizes 2N+1 codeword (N+1)-tuples into M subsets of codeword (N+1)-tuples, wherein each subset G has NG codeword (N+1)-tuples and the total number of codeword (N+1)-tuples in the M subsets is 2N and wherein each subset G has a predetermined number KG of lower bits and a predetermined number (N+1−KG) of higher bits and the number of lower bits in every codeword (N+1)-tuple in any subset is not equivalent to that of lower bits in every codeword (N+1)-tuple in any other subset. The 2N message N-tuples are mapped with said 2N codeword (N+1)-tuples in the M subsets, respectively, in one-to-one correspondence to generate a lookup table.

Abstract: To improve the processing efficiency and throughput by performing only a recovery process in read-accessing to a memory even when an address parity error has occurred in write-accessing to the memory, a selector is provided to select one of write data and a parity-bitted address for writing to the memory. If an address parity error has detected, the selector selects the parity-bitted address, in which the address parity error has occurred, instead of write data to be written to the memory during the write-accessing thereto. This address parity error processing method is particularly useful when applied to an information processor, such as a computer system, including a storage (memory).

Abstract: The present invention relates to a computer primary data storage system that integrates the functionality of file backup and remote replication to provide an integrated storage system that protects its data from loss related to system or network failures or the physical loss of a data center.

Abstract: A method for the correction of an erroneous bit in a string of bits includes providing, in the string of bits, for a first parity bit computed from the other bits of the string of bits at a point in time when the erroneous bit was valid. The correct value of the erroneous bit is computed by using the other bits of the string of bits comprising the parity bit. The erroneous bit is then replaced by its correct value. The method is applicable to error correction circuits in EEPROM memories.

Abstract: A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The method comprises the following steps. A row parity bit corresponding to a parity of a first plurality of bits stored along a row of CAM cells is stored. A column parity bit corresponding to the parity of a second plurality of bits stored along a column of CAM cells is stored. A parity of the first plurality of bits is read and generated and the generated parity is compared to the stored row parity bit. If the generated and stored parity bits do not match, columns of the array are cycled through. A parity of the second plurality of bits is read and generated and the generated parity is compared to the stored column parity bit until a mismatch is indicated.

Abstract: According to one aspect of the present invention, a method is provided in which a device, in response to a read request issued by a host, transfers data to the host through a series of direct memory access (DMA) data in bursts. The host is allowed to interrupt the data transfer and terminate the data in burst upon completion of a portion of the data transfer.

Abstract: A method and related system for generating error correction or parity information in a multiple disk computer system supporting multiple drive fault tolerance. The method involves defining parity equations to be based not only on data written to drives of the computer system but also on other parity information such that in solving for missing data, specific equations need not be used. Defining parity equations in this manner, in combination with a coefficient matrix that defines the coefficients of the various parity equations, ensures the ability to solve for the missing data even if some of the failed drives contain parity information.

Abstract: A parity check matrix is generated for detecting predefined errors in a coded string of bits. A column of the matrix is generated by selecting values for elements in the column and processing a predefined error with the selected values in order to produce a syndrome. The selected values are assigned to the column of the parity check matrix if an element of the syndrome has a value indicative of the predefined error.

Abstract: A system and method for checking and correcting soft errors in a next instruction pointer is described. In one embodiment, a parity bit is generated for a next instruction pointer that is produced in a front end of a processor. The next instruction pointer and the parity bit are staged from the front end of the processor to a back end of the processor. Another next instruction pointer is generated in the back end of the processor when an instruction corresponding to the next instruction pointer generated in the front end executes. The next instruction pointer generated in the back end is also parity protected. The next instruction pointer generated in the front end is checked for a parity error. The next instruction pointer generated in the back end is also checked for the parity error. Finally, both next instruction pointers are compared to determine if both are equal.

Abstract: A computer system with an array of disk drives is disclosed. The drive array is capable of supporting greater than 15 drive fault tolerance accomplished by using coefficients for parity equations spanning greater than eight bits.

Abstract: The invention provides a method and process for transmitting data without using additional CPU cycles and memory accesses to calculate checksums. The transmitting device obtains data from an internal or external data source and stores that data in memory. The data is then divided into zones and checksums are calculated for each zone. The checksums are recorded on a checksum array. A data pointer containing an address for the data stored in memory, a description of the data and an address for the checksum array is transferred through data transfer protocol to network and transmission layers. The network and transmission layers are then able to access and send the data without having to either copy the data through data transfer protocol to network and transfer layers or read all of the data to calculate the checksums. This method and process uses fewer CPU cycles and memory accesses to transmit data and is, therefore, more efficient than the prior art.

Abstract: A system and method for recovering from radiation induced memory errors invalidates information stored in a cache memory, upon the detection of the memory error. The cache memory is then reloaded with valid information.

Abstract: According to one aspect of the present invention, a method is provided in which a device, in response to a read request issued by a host, transfers data to the host through a series of direct memory access (DMA) data in bursts. The host is allowed to interrupt the read command and determine whether a first portion has been transferred correctly from the device based upon an error code calculation transmitted from the device to the host during the termination phase of a data in burst.

Abstract: A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.

Abstract: A method and apparatus for checking errors in data. The method includes transmitting data along with parity bits to a first end of a data transmission network; generating check bits from the data as such data passes through the network; comparing the check bits with the parity bits to determine whether there has been an error generated by the network. The error detector apparatus includes: a data source for providing data. The data has a plurality of bytes, each byte having a parity bit. A first logic is provided for determining whether the parity bits have the same parity and for producing a combined parity bit representative of such determination. A check bit generator produces a plurality of check bits from the data. A second logic determines whether the produced check bits have the same logic state and produces a combined check bit representative of such determination. A third logic determines whether the combined check bit and the combined parity bit have the same logic state.

Abstract: A device controller having an autodisk controller is presented. The autodisk controller in monitor mode is capable of monitoring the address of incoming data blocks and, when a target address is reached, triggers a switch of the device controller to buffer mode. In buffer mode, the autodisk controller is capable of monitoring parameters regarding incoming data blocks and reporting status or errors to a microprocessor. The autodisk controller can, for example, check for Id errors, EDC errors, copyright errors, addressing errors, or data area errors. The autodisk controller can also monitor the memory buffer and determine when it is full. The autodisk controller, therefore, relieves the microprocessor of the duties of monitoring incoming data blocks and error checking those data blocks.

Abstract: A method, apparatus, and computer implemented instructions for processing and recovering from soft errors in computer array with a parity error checking design in a data processing system. In response to an occurrence of a parity error, processor status information is stored to form stored processor information. A determination is made as to whether the parity error is a recoverable parity error using the stored processor information. In response to the parity error being a recoverable parity error, a recovery action is performed. The specific action taken varies depending on the type of error.

Abstract: Cache memory, and thus computer system, reliability is increased by duplicating cache tag entries. Each cache tag has a primary entry and a duplicate entry. Then, when cache tags are associatively searched, both the primary and the duplicate entry are compared to the search value. At the same time, they are also parity checked and compared against each other. If a match is made on either the primary entry or the duplicate entry, and that entry does not have a parity error, a cache “hit” is indicated. All single bit cache tag parity errors are detected and compensated for. Almost all multiple bit cache tag parity errors are detected.