Abstract: A storage control apparatus controls a storage device. The storage device includes a first storage area and a second storage area different from the first storage area. An error detection information storage unit generates an ECC for each of data blocks in data to be written, as error detection information. The error detection information storage unit stores generated ECC 1 to ECC 4 in the first storage area. A data storage unit stores data blocks DB1 to DB4 in the second storage area. A detection unit performs error detection on each of the data blocks according to the error detection information read from the first storage area and the data to be written read from the second storage area.

Abstract: Resource elements from multiple code blocks are separated into different groups, and the code bits of the resource elements within each group are decoded without waiting for a completed reception of a transport block to start decoding. Coded bits from multiple code blocks are similarly separated into different groups, and code blocks containing coded bits within each group are decoded. A first CRC is attached to the transport block and a second CRC is attached to at least one code block from the transport block. An improved channel interleaver maps coded bits of different code blocks to modulation symbols, and maps modulation symbols to time, frequency, and spatial resources, to make sure each code block receives approximately the same level of protection.

Abstract: Overhead associated with packet communication is reduced by combining or eliminating one or more fields of a packet. In some implementations, a reduction in overhead associated with packets employing security (e.g., IEEE 802.11ah packets) can be achieved by reducing overhead associated with verification-related fields. For example, a packet can include a merged frame check sequence (FCS) and an integrity check value (ICV). In some implementations, an FCS is omitted from a packet.

Abstract: A storage controller is provided. The storage controller includes a memory storing an indication of a current owner, a previous owner, and a preferred owner for each of one or more logical volumes. The storage controller is configured to write protect the logical volumes where the current owner and the preferred owner is the storage controller and the previous owner of the logical volumes was a different storage controller. For the logical volumes where the storage controller is the preferred but not the current owner, the storage controller is set as the current and preferred owner of the logical volumes that the different storage controller was the current but not the preferred owner for, storage controller is set as the previous owner of the logical volumes that the storage controller is the current and preferred owner of, and allowing read and write access to the one or more logical volumes.

Abstract: The invention relates to the field of communications and provides a method of and apparatus for transmitting downlink control information, and the method includes: for transmission of DCI over any carrier, determining DAI information fields in uplink scheduling DCI and downlink scheduling DCI to be carried over the carrier and an HARQ process number information field in the downlink scheduling DCI dependent upon PDSCH HARQ feedback scheme currently in use; and determining a UL index information field in the uplink scheduling DCI to be carried over the carrier dependent upon a PUSCH scheduling scheme currently in use, so that an appropriate DCI design scheme is provided for an application scenario of across-system carrier aggregation to thereby satisfy a demand for the use of an evolved process in an LTE system and improve effectively the performance of the system.

Abstract: Methods, systems, and computer readable media for a multi-packet CRC engine are disclosed. According to one aspect, the subject matter described herein includes a system for a multi-packet CRC engine. The system includes an input module for receiving set of bits associated with at least one data packet and identifying packet boundaries within the plurality of bits, multiple CRC pre-calculation blocks (CPBs) that receive from the input module subsets of the set of bits, each subset containing a portion of a packet less than all of a packet, and calculate a CRC value for its respective subset of bits, and an output module for receiving the calculated CRC values from the CPBs and using the calculated CRC values to produce packet-specific CRC values, where the output module is dynamically configurable to combine the calculated CRC values according to the identified packet boundaries to produce packet-specific CRC values.

Abstract: Resource elements from multiple code blocks are separated into different groups, and decoding the code bits of the resource elements within each group without waiting for a completed reception of a transport block to start decoding. Coded bits from multiple code blocks are separated into different groups, and the code blocks containing coded bits within each group are decoded. A first CRC is attached to the transport block and a second CRC is attached to at least one code block from the transport block. An improved channel interleaver design includes mapping from coded bits of different code blocks to modulation symbols, and mapping from modulation symbols to time, frequency, and spatial resources, to make sure each code block to get roughly the same level of protection.

Abstract: A circuit provides parallel computation of error codes for simultaneously received words. The words received simultaneously may be portions of a common data message, or may be portions of distinct data messages. Accordingly, the circuit selectively accumulates the error codes based on their association with successive data words, outputting an accumulated error code when the last word of a data message has been received and the respective error code is calculated. Based on such information, the error codes calculated in parallel can be output independently, accumulated with one another, or accumulated with the error codes of a previous or subsequent calculation cycle. Thus, the circuit dynamically provides a single parallel error code generation of a given width or multiple parallel error code generations, each of a width divisible by the given width.

Abstract: A method of fault testing in a storage device comprises testing, in accordance with a storage device testing protocol, operability of a plurality of distinct portions on the storage device. The testing includes, for each of the plurality of distinct portions on the storage device: performing one or more operations on a respective portion of the storage device; recording data corresponding to electrical current drawn during performance of the one or more operations on the respective portion of the storage device; analyzing the recorded data, including determining whether one or more predefined characteristics of the recorded data meets predetermined failure criteria; and, in accordance with a determination that the recorded data meets the predetermined failure criteria, performing one or more remedial actions including updating a mapping of the storage device to mark the respective portion as a known-bad portion.

Abstract: A method of fault detection includes, while in normal operation: recording data corresponding to measurements of electrical current drawn during performance of a respective operation on a specified portion of a storage device; analyzing the recorded data, including determining whether one or more predefined characteristics of the recorded data meets predetermined failure criteria; and in accordance with a determination that the recorded data meets the predetermined failure criteria, performing one or more remedial actions, the one or more remedial actions including marking the specified portion as a known-bad portion.

Abstract: A communicating unit of a base station performs a plurality of periodic communication services with a wireless terminal. A communication control unit of the base station includes, in a control channel, identification information for distinguishing the periodic communication services one from the other to thereby allow the wireless terminal to control at least one of activation and release of each of the periodic communication services. A communicating unit of the wireless terminal performs the plurality of periodic communication services with the base station. A communication control unit of the wireless terminal controls at least one of the activation and the release of each of the periodic communication services using the identification information included in the control channel transmitted from the base station.

Abstract: A two part process is used for modifying records to be written and retrieved from tape devices. A record is appended with a cyclic redundancy check and a string of zeros. Submitting the entire record to tape drives which are logical block protection enabled will result in no change. For drives that are not LBP enabled, the string of zeros at the end of the record is removed. In addition to determining whether a drive is LBP compliant, a determination may be made as to whether a drive is a linear tape open drive from a particular manufacturer. Linear tape open drives may behave similarly as drives which may not be enabled with logical block protection.

Abstract: Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert.

Abstract: Transponder (104), comprising a storage unit (106) having stored a number of different applications, a processing unit (108) which, on request of a reader (102), is adapted to generate a response interpretable using an encryption scheme known by both the transponder (104) and the reader (102) so that the reader (102) is capable of determining whether an application is supported by the transponder (104) by analyzing the response using the encryption scheme, and a transmission unit (110) adapted to send the response to said reader (102).

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for allocating machine check architecture banks. The processing device includes a plurality of machine check architecture banks to communicate a machine check error. The processing also includes an allocator to allocate during runtime of the processor a target machine check architecture bank of the plurality of machine check architecture banks. The runtime of the processor is during an occurrence of the machine check error.

Abstract: A method for providing information on the validity of encoded audio data is disclosed, the encoded audio data being a series of coded audio data units. Each coded audio data unit can include information on the valid audio data. The method includes: providing either information on a coded audio data level which describes the amount of data at the beginning of an audio data unit being invalid, or providing information on a coded audio data level which describes the amount of data at the end of an audio data unit being invalid, or providing information on a coded audio data level which describes both the amount of data at the beginning and the end of an audio data unit being invalid. A method for receiving encoded data including information on the validity of data and providing decoded output data is also disclosed. Furthermore, a corresponding encoder and a corresponding decoder are disclosed.

Abstract: In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: A communication system is provided wherein a user equipment (UE) receives control information from a wireless network. The UE monitors control channel candidates using common reference signals (CRS) and monitors enhanced control channel candidates using demodulation reference signals (DMRS) when the UE is configured in a first transmission mode, such as transmission mode 9, for receiving a downlink shared traffic channel based on DMRS. The UE monitors control channel candidates only using CRS when the UE is configured in a second transmission mode, such as any of transmission modes 1-6, for receiving a downlink shared traffic channel based on CRS. The UE then receives downlink control information (DCI) in a subframe in one of the monitored control channel candidates or enhanced control channel candidates in the subframe.

Abstract: A frame configuration used for both SISO transmission and MISO and/or MIMO transmission. According to the frame configuration, a frame has a preamble, a control symbol, and transmission data symbols. A transmission device includes the designation of a transmission scheme of the transmission data symbols in the control symbol and includes the designation of a transmission scheme of the control symbol in the preamble. This frame configuration improves the reception performance (detection performance) of a reception device.

Abstract: A bit stream having non-deterministic entropy is generated by a Self-Timed Logic Entropy Bit Stream Generator (STLEBSG). The STLEBSG includes an incrementer and a linear feedback shift register (LFSR), both implemented in self-timed logic as parts of an asynchronous state machine. In response to a command, the incrementer asynchronously increments a number of times and then stops, where the number of times is determined by command. For each increment of the incrementer, the LFSR undergoes a state transition. As the incrementer increments, the LFSR outputs the bit stream. If the command is a run repeatedly command, then after the incrementer stops the incrementer is reinitialized and then again increments the number of times. This incrementing, stopping, reinitializing, and incrementing process is repeated indefinitely. Another command causes the incrementer to be loaded. Another command causes the LFSR to be loaded.

Abstract: A method and apparatus for encoding a transport block are provided. The method for encoding the transport block includes: determining, by a transmitter, a size of transport block; dividing, by the transmitter, the transport block into at least one code block based on the size of transport block; interleaving, by the transmitter, the at least one code block by an interleaver; and performing, by the transmitter, a turbo coding for the interleaved at least one code block, wherein the size of transport block is determined based on the number of the divided code blocks.

Abstract: A wireless communication base station apparatus that allows the number of times of blind decodings at a mobile station to be reduced without increasing the overhead caused by notifying information. In this apparatus, a CCE allocation part allocates allocation information allocated to a PDCCH received from modulation parts to a particular one of a plurality of search spaces that is corresponding to a CCE aggregation size of the PDCCH. A placement part then places the allocation information in one of downstream line resources, reserved for the PDCCH, that is corresponding to the CCE of the particular search space to which the allocation information has been allocated. A radio transmission part then transmits an OFDM symbol, in which the allocation information has been placed, to the mobile station from an antenna.

Abstract: Data is divided into parts and each part provided to a different processor. Each processor processes the provided data part to produce a partial CRC result. The partial CRC results from each of the different processors are XORed to produce a CRC of the data.

Abstract: Methods and devices generate cyclic redundancy check (CRC) values for a sequence of parallel words of data. The data words may have only some of the bits enabled. The input words are preconditioned, and then a common block generates a CRC remainder value. A specific preconditioning is selected based on the number of enabled bits. Additional post-processing may be performed to the CRC remainder.

Abstract: A reliability metric is used for determining whether to prune a decoding hypothesis. For example, a reliability metric can be generated for each possible hypothesis generated during blind decoding operations. The reliability metric can then be used in a pruning process whereby a determination to prune a given hypothesis is based on whether the corresponding reliability metric is above or below a reliability metric threshold. In some aspects, the reliability metric is based on the correlation between the symbols of a hypothesis and re-encoded symbols that are based on the hypothesis, whereby the correlation is normalized using an estimated power parameter that is independent of the hypothesis. Through the use of the reliability metric, decoding may be achieved with a low probability of false passes (in the case of noise) and a low probability of missed detection (in the case of a real signal).

Abstract: A memory controller comprises at least one interface configured to receive a request, user data, and an address from an external source, a first data check engine configured to generate data check information based on the received address and the user data in response to the received request, and a second data check engine configured to check the integrity of the user data based on the generated data check information where the user data is transmitted to the nonvolatile memory. The memory controller is configured to transmit the user data received from the external source to an external destination where the integrity of the user data is verified according to a check result, and is further configured to transmit an interrupt signal to the external source and the external destination where the check result indicates that the user data comprises an error.

Abstract: In an arrangement of the disclosed systems, devices, and methods, a codeword encoded with a first number of check symbols is received and asymmetrically processed according to a second number of check symbols, where the second number of check symbols is less than the first number of check symbols, to produce an error locator polynomial and an error evaluator polynomial. A derivative of the error locator polynomial is produced by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant. The derivative of the error locator polynomial is produced using a variable finite-field multiplier and without use of a divider.

Abstract: A method for recovering from an interruption during a Firmware Over-The-Air (FOTA) update is provided. The method includes identifying a missing block of a plurality of blocks to be updated in the first memory, the missing block corresponding to a block being updated when the interruption occurred, copying a backup block into a backup buffer, simulating an application of the FOTA update in a second memory, the simulation including, for each block of the plurality of blocks to be updated, performing a reversible operation on the contents of the backup buffer and an updated block, and updating the backup buffer with the operation result, replacing the missing block with the updated backup buffer, and resuming the FOTA update.

Abstract: A decoding apparatus has an on-chip buffer, an external buffer interface, and a turbo decoder. The on-chip buffer is arranged for buffering each code block to be decoded. The external buffer interface is arranged for accessing an off-chip buffer. The turbo decoder is arranged for decoding a specific code block read from the on-chip buffer. The specific code block is not transmitted from the on-chip buffer to the off-chip buffer via the external buffer interface unless decoding fail of the specific code block is identified.

Abstract: An audio coding terminal and method is provided. The terminal includes a coding mode setting unit to set an operation mode, from plural operation modes, for input audio coding by a codec configured to code the input audio based on the set operation mode such that when the set operation mode is a high frame erasure rate (FER) mode the codec codes a current frame of the input audio according to a select frame erasure concealment (FEC) mode of one or more FEC modes. Upon the setting of the operation mode to be the High FER mode the one FEC mode is selected, from the one or more FEC modes predetermined for the High FER mode, to control the codec by incorporating of redundancy within a coding of the input audio or as separate redundancy information separate from the coded input audio according to the selected one FEC mode.

Abstract: A method for a first communication device transmitting data to a second communication device, according to one embodiment of the present invention, comprises the steps of: the first communication device generating a safety unique identifier by using a unique identifier of the first communication device and a unique identifier of the second communication device, in order to confirm the validity of connection between the first communication device and the second communication device; the first communication device calculating a data error detection code for detecting an error by using the safety unique identifier and the data; the first communication device generating a packet comprising the data and the data error detection code; and the first communication device transmitting the packet to the second communication device.

Abstract: Provided are an encoding method and an encoding apparatus in a wireless communications system. The encoding apparatus generates an error detection code for a first UCI (uplink control information), and adds the error detection code to a second UCI. The encoding apparatus encodes the first UCI, and then the second UCI added with the error detection code.

Abstract: Circuitry for providing error check values for indicating errors in data portions within a data stream. The circuitry comprises error detecting code generation circuitry configured to apply an error detecting code algorithm to the data stream and to thereby generate and periodically update a multi-bit check value as the data stream is processed, each update of the multi-bit check value being indicative of the error detecting code generation circuitry receiving a further item of the data stream. An output for periodically outputting a fragment of the multi-bit check value from the error detecting code generation circuitry during the processing of the data stream, the fragments output each corresponding to a data portion of the data stream. Wherein each of the fragment of the multi-bit check value provides a value indicative of an error occurring either in the corresponding portion of the data stream or in an earlier portion of the data stream.

Abstract: A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.

Abstract: An information processing apparatus includes an MMU that translates between a virtual address and a physical address on the basis of a translation table for translation between physical addresses that are addresses in physical memory and virtual addresses that are addresses in virtual memory. Stored in a RAM are page table information indicating a page table, as well as error detection information attached to the page table information for detecting the presence or absence of an error in translation between a virtual address and a physical address performed by the MMU. A CPU detects the presence or absence of an error in translation between a virtual address and a physical address performed by the MMU on the basis of the error detection information.

Abstract: An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: A method for sending information and a device thereof are provided. The method includes: selecting a sequence corresponding to original information to be sent according to mapping table of information-sequence; performing cyclic redundancy check on the original information according to the sequence to obtain a cyclic redundancy check code; and sending the original information and the cyclic redundancy check code. Compared with the conventional technology, no modifications on existing chips or protocols are required in the embodiments of the application, and development costs are saved.

Abstract: Disclosed herein is an apparatus and method for calculating a TCP checksum. An apparatus for calculating a TCP checksum includes a data division unit for dividing content to be transmitted into two or more primary data fragments by a unit of a preset byte. A first checksum calculation unit calculates first checksums for the primary data fragments, respectively. A second checksum calculation unit calculates a second checksum for secondary data to be inserted into a data area of the TCP segment using the first checksums. Accordingly, in TCP-based networks, a checksum calculation procedure is improved upon transmitting static content, so that a static content transfer rate occupying most of TCP-based network traffic can be improved.

Abstract: A device is provided comprising a shared bus, a slave device, and a master device. The slave device may be coupled to the shared bus. The master device may be coupled to the control data bus and adapted to manage communications on the shared bus. Transmissions over the shared bus are a plurality of bits that are encoded into ternary numbers which are then transcoded into symbols for transmission, and either the 3 least significant bits or the least significant in the plurality of bits are used for error detection of the transmission.

Abstract: A method and apparatus for encoding and decoding a data block are disclosed. The data block may be for a physical channel. Further, the data block may be for a shared channel. For data block encoding, a Node-B may calculate cyclic redundancy check (CRC) bits for the data block. The data block may be used to calculate the CRC bits. The Node-B may mask the CRC bits with a wireless transmit/receive unit (WTRU) identity (ID). Further, the Node-B may attached the masked CRC bits to the data block. Using a transmitter, the Node-B may transmit the data block over a physical channel. Further, the Node-B may transmit the data block over a shared channel. A WTRU may receive the data block, including the masked CRC bits. Using the WTRU ID, the WTRU may de-mask the CRC bits. The WTRU may perform a CRC check using the de-masked CRC bits.

Abstract: A circuit arrangement for determining m check bits c1, . . . , cm for k data bits u1, . . . , uk is provided, wherein the circuit arrangement includes a first subcircuit and a second subcircuit. The first subcircuit has k binary inputs for inputting the k data bits u=u1, . . . , uk and M binary outputs for outputting M binary intermediate values z1, . . . , zM determined from the data bits. The second subcircuit is configured to transform the intermediate values z1, . . . , zM into the check bits c1, . . . , cm.

Abstract: An approach to determine whether errors associated with transmitted data are associated with a transmitting device, a receiving device, and/or a connecting device that connects the transmitting device to the receiving device. The approach includes a method that includes receiving transmitted data with a buffer. The approach further includes analyzing the transmitted data which includes an error correcting process to detect errors and determine that the transmitted data has an error that requires additional analysis. The approach further includes determining that the error is associated with a receiving device, the transmitting device, or a connecting device that connects the receiving device and the transmitting device.

Abstract: User equipment (UE) cooperation can be improved by relaying partial soft information to target UEs. More specifically, a cooperating UE may relay a subset of log-likelihood ratios (LLRs) to the target UE. The subset of LLRs may correspond to fewer than all resource blocks of the original transmission. This may allow UE cooperation to be effective when the cooperating UE was only able to decode a portion of the original transmission. This may also allow fewer network resources (e.g., bandwidth, etc.) to be used when the target UE does not need all of the soft information to decode the original transmission. Multiple cooperating UEs can provide different subsets of LLRs, and the subsets may or may not overlap with one another.

Abstract: A method of transmitting data via a wireless transmission path, that may include a user equipment as a first end point, a base station as a second end point, and at least one relay station as an intermediate point, includes receiving a data transmission from a prior point in the wireless transmission path, and, substantially concurrently, forwarding the received data to the next point in the transmission path, and determining whether the received data is corrupt. The method further includes transmitting a transmission message to the next point in the transmission path indicating whether the received data was corrupt. The method finally includes, when the data is not corrupt, transmitting a receipt message to the prior point indicating that the data was uncorrupt when received.

Abstract: In accordance with the teachings described herein, systems and methods are provided for calculating a Cyclic Redundancy Check (CRC) code for a message. A system includes a first CRC calculator and a second CRC calculator. The first CRC calculator is configured to receive a first data block of the message, and to calculate a first CRC value based at least in part on the first data block, the message including the first data block and a second data block. The second CRC calculator is configured to receive the first CRC value and the second data block of the message, and to calculate a second CRC value based on the first CRC value and the second data block, the second CRC calculator being different from the first CRC calculator.

Abstract: A method for semi-orthogonal transmission of a signal intended for a system with N sources, M relays and a single receiver whereby the simultaneous transmission on a same spectral resource by the relays is successive and not simultaneous to a simultaneous transmission on a same spectral resource by the sources. The includes, by relay: joint iterative detection/decoding of messages transmitted respectively by the sources to obtain decoded messages, detecting errors on the decoded messages, interleaving the detected messages without errors followed by algebraic network coding consisting of a linear combination in a finite group of an order strictly higher than two of the interleaved messages to obtain a coded message, the linear combinations being independent, two by two, between the relays of the system, and formatting including channel coding to generate a signal representative of the network coded message.

Abstract: A first communication device calculates a plurality of data error codes for detecting an error in a plurality of data fields by using the plurality of data fields. The first communication device generates a packet comprising the plurality of data fields and the plurality of data error codes, and then transmits the packet which is generated to a second communication device.

Abstract: Systems, methods, and apparatuses are directed to optimizing turnaround timing of successive transactions between a host and a memory device. The host includes framing logic that generates a write frame that includes a plurality of data bits and an error bit checksum that is appended at the end of the data bits. The host further includes a bus infrastructure configured to accommodate the transfer of the write frame to the memory device and logic that defines the turnaround time to begin at a time instant that immediately follows the transfer of the data bits of the write frame. The turnaround time measures the time delay at which a succeeding write frame is to be transferred. In this manner, the turnaround time is optimized to enable the earlier initiation of successive data operations, thereby reducing the overall latency of successive back-to-back transactions.

Abstract: A first communication device calculates a data error detection code for detecting an error in data by using the data and a virtual sequence number, and generates a packet comprising the data and the data error detection code. The packet does not include the virtual sequence number which is used for calculating error detection. The first communication device transmits the packet to a second communication device.

Abstract: A communication system having a main control portion (MCP) to transmit information destined to a device n cascade levels down, and create an error detection code (CRC code) for data that contains a count of remaining cascade levels until an n-th cascade level and the information. The code is transmitted to an upstream sub-control portion (USCP) with the data. The USCP creates a CRC code for the data, and compares the created and received codes. For a match, the USCP determines whether the information is destined to itself based on the remaining cascade level count. When the information is not so destined, the USCP creates new data with the remaining cascade level count reduced by 1, and a CRC code for the new data, and transmits the created code to a further device, with the new data.