Abstract: A high speed communication apparatus with means for reducing timing uncertainty providing a high accuracy of transferring and receiving signals by intelligent skew calibration of the apparatus. The system for reducing timing uncertainty of a communication apparatus comprises a plurality of driving registers for transmitting signals; a plurality of receiving registers for receiving signals; a main clock for generating a main clock signal; a reference clock for generating reference signals for calibrating the registers; and a plurality of phase shift means comprising at least one set of phase shift means associated with each said plurality of registers, for the relative alignment of the register's timing within each plurality.

Abstract: A flash programmable microprocessor-based control module is operated in a manner to protect the integrity of event data stored in the programmable memory of the module while permitting authorized manufacturing and field alteration of the programmable memory with a Download and Execute routine. The Download and Execute routine is resident in a designated sector of the module's read-only memory, and download access to the module's random access memory after module manufacture has been completed is denied. During manufacture of the module, and during field programming of the controller prior to the writing of event data, the programmable memory may be externally altered by an authorized service tool by transferring the Download and Execute routine from read-only memory to random access memory for execution by the module's microprocessor, and downloading the new data or code over a data link coupling the service tool to the module.

Abstract: A receiver in which sync data detection logic detects unencoded sync data at block boundaries of blocks encoded symbols received over a communications channel. Based on the detection of the sync data, the sync data detection logic determine synchronization information for one or more components of the receiver. It may also determine one or more system parameters by counting the number of symbols between successive instances of the sync data.

Abstract: A time data compression technique which allows high speed integrated circuit (“IC”) memory devices to be tested at full speed with test equipment which is capable of operating at only at relatively slower speeds than that of the memory devices without increasing test time or decreasing production throughput. Through the use of the technique disclosed herein, data is initially sorted in time and them compared for a predetermined number of logic level “1s” or “0s” to be effectively compressed in time. This time compression allows high rate data streams to be tested at effectively slower rates. The technique of the present invention can be utilized to effectively reduce the data rate by one half, one quarter or to any sub-multiple of the normal memory frequency without increasing time in test.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: A repetitive transmission technique with time diversity which provides improved signal-to-noise ratio (SNR) in the presence of packet loss. Time shifts are introduced between N versions of a particular block of information to be transmitted, and the time-shifted versions are encoded in a set of N encoders and transmitted as N packets. The time shift introduced between a given pair of the N versions corresponds to approximately 1/N of the time duration of a particular one of the versions. The SNR of a composite reconstructed signal generated from the N packets with the introduced time shift in a receiver of the system is approximately the same as would be obtained using a set of N independent encoders to generate the plurality of packets without the introduced time shifts. The gain in the SNR of the composite reconstructed signal attributable to the introduction of the time shifts is 10 log10N′, where N′=1, . . .

Abstract: A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.

Abstract: A method for automatically finding the transition interval from a fast write to a delayed fast write, in a mass storage system in which the mass storage system has a plurality of disk drive storage elements controlled by a disk drive controller, the controller having a cache memory through which all data writes pass, and the controller receiving commands and data from at least one host computer.

Abstract: A high speed communication apparatus with means for reducing timing uncertainty providing a high accuracy of transferring and receiving signals by intelligent skew calibration of the apparatus. The system for reducing timing uncertainty of a communication apparatus comprises a plurality of driving registers for transmitting signals; a plurality of receiving registers for receiving signals; a main clock for generating a main clock signal; a reference clock for generating reference signals for calibrating the registers; and a plurality of phase shift means comprising at least one set of phase shift means associated with each said plurality of registers, for the relative alignment of the register's timing within each plurality.

Abstract: A method of testing a circuit having an interface which includes data and clock information where phase jitter is introduced into the clock that produces the clock information. The clock is cycled by increasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift advance in the clock. The clock is also cycled by decreasing the period of the clock for a predetermined number of clock cycles so as to introduce an increasing phase shift delay in the clock. The circuit under test is caused to sample the data using a clock derived from the clock information. The sampled data is then compared with reference data to determine the error rate.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: A pre-conditioner for enabling high-speed time interval measurements in an ATE system having a relatively low-bandwidth pathway between a UUT and a timer/counter includes a frequency divider and a D flip-flop located near the UUT. The frequency divider receives a first input signal from the UUT and produces a first output signal having a frequency equal to 1/N times the frequency of the first input signal. The first output signal connects over the low-bandwidth pathway to a first channel of the timer/counter. The first output signal also connects to the D input of the D flip-flop. The pre-conditioner receives a second input signal from the UUT that drives the CLOCK input of the D flip-flop. The Q output of the D flip-flop supplies a second output of the pre-conditioner. The second output connects over the low-bandwidth pathway to a second channel of the timer/counter.

Abstract: A method of processing a DVD bitstream includes the steps of reading the DVD bitstream, the bitstream including a sync frame. A sync window is created, the sync window being open at least during the expected timing of a sync detection signal within the sync frame. The sync pattern is detected within the sync frame and the sync detection signal is generated only when the sync pattern has been detected and the sync window is open. A DVD sync pattern detection circuit includes a sync window generator to generate a sync window signal, a sync pattern detector, the sync pattern detector generating a sync detection signal only when both a sync pattern is detected in a DVD input stream and the sync window signal is asserted. A read channel bit counter generates a read counter signal to control the sync window generator, the read channel bit counter being reset when the sync pattern detector detects the sync pattern.

Abstract: Effects of glitches on the data line which can cause an I2C bus (or SMBus) interface to invalidate a detected I2C start command or to erroneously detect an I2C start command, which occurs when the data signal transitions from a logic high to a logic low while the clock signal has a logic high, are reduced by detecting the logic state of the data signal when the clock signal next transitions from a logic high to a logic low.

Abstract: A data reception method is described in which errors due to a phase shift between the data signals and the clock pulse are compensated in data signals transmitted at a constant frequency with the receiving device operating at this frequency by operating two readout devices with a time offset, and a signal output by one of the readout devices is selected, after which this signal is checked for validity. This makes additional transmission of an operating clock pulse via a bus system and synchronization of an input signal with an operating clock unnecessary.

Abstract: A method and apparatus for testing an input data path of an integrated circuit. Dual transmit and receive delay locked loops (DLLs) provide clocks for test mode data transmit and receive. Test mode logic drives a data pattern into an input receiver with the data pattern clocked by the transmit DLL and the input receiver clock by the receive DLL. The output of the input receiver is compared with the data pattern. The transmit DLL is adjusted relative to the receive DLL to measure setup and hold times of the data pattern driven through the input receiver.

Abstract: A method of detecting synchronization errors during the transfer of data in which a transmitting agent sends to the receiving agent either: (a) data parity encoded with a data parity function when the transmitting agent encodes data in one or more clock signals, or (b) header parity encoded with a header parity function when the transmitting agent encodes header information in the one or more clock signals. A synchronization error condition is detected when the receiving agent either: (a) is configured to receive the data parity and actually receives the header parity, or (b) is configured to receive the header parity and actually receives the data parity.

Abstract: The present invention simulates the behavior of a storage component by first determining whether a timing violation has occurred for the storage component. If one or more timing violations is detected, then an x (indicating uncertainty) is reflected at the output of the storage component. This x is maintained at the output of the storage component for a predetermined number of timing units. After the predetermined number of timing units has expired, the output of the storage component is changed from x to a certain value, such as a logical 1 or a logical 0. By changing the output to a certain value, the present invention prevents the x at the output of the storage component from indefinitely propagating to other components in the circuit. This in turn prevents large numbers of x's from appearing in the simulation results provided to the designer. Instead, values that are certain will appear in the results.

Abstract: A signal comparison system determines whether a data signal is transitioning close to transitions of its clock signal, thereby causing possible errors in the sampling of the data signal. The signal comparison system includes a plurality of latches that receive a first signal and a second signal and that transmit a respective value of the first signal in response to a transition of the second signal. Delay mechanisms delay the transition of the second signal before the transition is received by latches so that the transition is delayed different amounts relative to each of the latches. A feedback mechanism receives the values transmitted by the latches and determines whether these values are logically equivalent. The feedback mechanism then transmits a feedback signal in response to a determination that one of the values is logically different than another of the values.

Abstract: Data output from a semiconductor device under test and a reference clock output therefrom in synchronization with the data are sampled by slightly phased-apart multiphase strobe pulses. The phases of points of change of the output data and the reference clock are obtained from the sampled outputs, then the phase difference between them is measured, and a check is made to determine if the phase difference falls within a predetermined range, thereby evaluating the semiconductor device under test on a pass/fail basis.

Abstract: The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop (“PLL”) circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period.

Abstract: Automatic test equipment for memory device testing with elements providing a high accuracy of transferring and receiving signals when testing a semiconductor device under test (DUT) by intelligent skew calibration of a timing system. The device for automatic skew calibration of a transceiver comprises a plurality of input registers for transmitting signals; a plurality of output registers for receiving signals; a main clock driver for generating a main clock signal; a reference clock driver for generating reference signals for calibrating the registers; the reference clock driver being associated with the main clock driver; and a plurality of phase shifters comprising at least one set of phase shifters associated with each plurality of registers, for the relative alignment of the register's timing within each plurality. The calibration is performed using a common time base which is distributed by means of a transmission line having predetermined wave characteristics.

Abstract: A built-in self test system for testing a clock and data recovery circuit is disclosed. The present invention provides a built-in self test circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing means coupled to the data generating means for converting the test data byte into serial test data. The clock and data recovery means are coupled to the output of the serializing means for recovering the clock and test data from the serial test data. A deserializing means coupled to the output of the clock and data recovery means converts the recovered serial test data into a recovered test data byte, and analyzing means connected to the output of the deserializing means compares the recovered test data byte to the initial test data byte.

Abstract: A fault tolerant clock system which employs a plurality of latches each of which is set to fault a clock signal upon the occurrence of one of a like plurality of anomalies and each of which can be independently reset so that the system can be started with asynchronous signals and so that, upon the removal of the anomalies, the latches can be reset to unfault previously faulted signals when the anomaly causing the fault has been cured.

Abstract: A method of making a phase lock loop circuit is disclosed. The method includes a method of simulating the phase lock loop circuit. The simulation runs on a system for making phase lock loop circuits. The simulation step initializes a reference frequency variable associated with a reference frequency of a phase lock loop circuit. The simulation method also initializes a voltage controlled oscillator (VCO) frequency variable associated with a VCO frequency of the phase lock loop circuit. A phase error is obtained from a frequency error between the reference frequency variable and the VCO frequency variable. The simulation method resets the phase error by a reset phase level when the phase error is approximately the same as a multiple of a reset threshold. When the frequency error changes sign, the phase error is permitted to also change sign. The simulation also determines a loop filter input for the phase lock loop circuit that depends upon the phase error and the frequency error.

Abstract: Synchronization (sync) marks on a digital-versatile disk (DVD) optical disk are initially detected and later used to adjust bit timing after jitter has occurred. Each DVD physical sector contains many sync marks in a predefined sequence. Each sync mark has a sync-code field that varies for the sync marks in a sector, and a fixed sync pattern that is constant for all sync marks. The first sync mark is detected at initialization by detecting a previous sequence of sync codes of sync marks that precede the first sync mark. The sequence is programmable so that one to seven sync marks are in the sequence searched for. Detection for sync marks with bit errors can still occur since a programmable number of bit errors are allowed in each sync code and in the fixed sync pattern. One of the sync codes can be missed in the sequence and detection still made, allowing tolerance of errors in the sync marks when longer sequences of sync codes are matched.

Abstract: In a transmission system or recording system, a detector (16,30) using quality measures indicating the quality of the received signal is applied.In contradistinction with the prior art system the quality measure comprises the deviation of the position of transitions in the input signal from the nominal positions of said transitions. The advantage of using this type of quality measure is that the required information for determining it, is already available within the PLL (34) needed for clock recovery.

Abstract: A transmitter/receiver chip includes circuitry for testing the bit error rate of the chip. A controlled amount of noise is introduced to the chip to vary a timing parameter of a transmit clock, resulting in an increase in a bit error rate of the chip. Artificially increasing the bit error rate of the chip reduces the amount of time required to test the chip to determine the acceptability of the chip and its actual bit error rate.

Abstract: An improved thermal asperity detector is disclosed for detecting short thermal asperities using a variable time threshold. The thermal asperity detector includes a saturation detector, and a comparator system. The comparator system may include a polarity latch, a processor, a level comparator and a timing comparator. The saturation detector compares a programmable saturation threshold to an A/D sample to generate an enable signal in response to the A/D sample exceeding the saturation threshold. The polarity latch receives the A/D sample and the enable signal, and records the most significant bit of the A/D sample to identify the polarity of the saturation and to provide an output signal representative thereof in response to the enable signal. The processor generates a threshold level control signal based upon a programmable level threshold and the polarity latch output signal.

Abstract: A frequency detection circuit has a transistor switching device between first and second electric potentials, and a gate applied with a clock signal. A resistor and a capacitor are connected in parallel between the output of the transistor switching device and the second potential. The capacitor is charged toward the first potential when the clock signal assumes one level and discharged toward the second potential in accordance with a time constant determined by the resistor and the capacitor when the clock signal changes to the other level.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. Discrete time timing recovery within the read channel comprises a variable frequency oscillator (VFO) for generating a sampling clock. A center operating frequency of the VFO is adjusted through a programmable register which stores a digital center frequency setting. A phase error is computed from the sample values and combined with the center frequency setting to control the frequency and phase of the sampling clock at the output of the VFO.

Abstract: The data processing circuit has a self-timed instruction execution unit, which operates asynchronously, signalling the completion of processes and starting subsequent processes in response to such signalling. In order to satisfy real time constraints upon program execution ready signals generated after completion of selected instructions are gated with a timer signal before they are used to start a next instruction. In an embodiment, the amount of time left between the ready signal is used to start a next instruction is measured and used to regulate a power supply voltage of the instruction execution unit so that it is just high enough to make the instruction execution unit sufficiently fast to meet the real time constraints.

Abstract: An energy efficient remote control protocol uses a start bit which has a variable length which corresponds to the parity of the transmitted symbol, a guard time which is fixed at a predetermined length, and a data transmission time which corresponds to the data to be transmitted. The data to be transmitted is transmitted as a logic low, thus improving the energy efficiency of the system. During the transmission of a code, only one stop bit is used at the end of the transmission. The guard time and parity check are used to verify proper transmission.