Responding To The Occurrence Of A Fault, E.g., Fault Tolerance, Etc. (epo) Patents (Class 714/E11.021)

  • Publication number: 20110185228
    Abstract: According to the invention, a managing server, using a snapshot-appended information table which stores management information for identifying snapshots of a virtual server, a setting change table which stores setting change information on the virtual server, and a policy table which stores policies to be met by the virtual server, acquires the setting change information from the setting change table, selects the setting change information items from the acquired setting change information matching policies stored in the policy table, acquires management information on the snapshots of the virtual server from the snapshot-appended information table, identifies a snapshot of the virtual server with reference to the acquired management information, changes the identified snapshot of the virtual server based on the selected setting change information items, and rolls back the virtual server according to the changed snapshot.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 28, 2011
    Applicant: HITACHI, LTD.
    Inventors: Kentaro WATANABE, Yoshimasa MASUOKA
  • Publication number: 20110185237
    Abstract: A system and method for delivering messages are provided. A method for communications device operations includes detecting a failure in a delivery of a message to a first recipient device, determining a second recipient device for the message, and initiating a redelivery of the message to the second recipient device. The first recipient device is formerly registered in a first domain of a communications network or is unavailable in the first domain.
    Type: Application
    Filed: January 28, 2011
    Publication date: July 28, 2011
    Applicant: FutureWei Technologies, Inc.
    Inventors: Kaniz Mahdi, Shufeng Shi
  • Publication number: 20110173483
    Abstract: A resource recovery system may maintain a counter in memory that indicates a number of times one or more threads of execution, which use shared resources, have crashed. The system may associate a first value of the counter with a resource allocated to a thread of the one or more threads, and may set an indicator associated with the thread to indicate whether the thread has crashed. The system may determine whether to re-allocate the resource to the thread based on the first value of the counter associated with the resource and based on the indicator associated with the thread.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 14, 2011
    Applicant: JUNIPER NETWORKS INC.
    Inventor: Michael LYNN
  • Publication number: 20110154100
    Abstract: The present invention relates to an apparatus and method of performing an error recovery process in an asymmetric clustering file system that has higher efficiency in data recovery when a data server in an asymmetric clustering file system fails than a method of processing the data recovery in the metadata server. The present invention includes receiving a chunk list requiring recovery by a data server included in the other data server groups than a data server group including a failed data server among a plurality of data server groups, requesting chunk data necessary for recovering an erroneous chunk from a data server in the other data server groups to the other data servers than the failed data server in the data server group, and recovering the erroneous chunk based on the chunk data by the data server in the other data server group.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 23, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sang-Min LEE, Young-Kyun Kim, Han Namgoong
  • Publication number: 20110154128
    Abstract: In accordance with at least some embodiments, a system comprises a plurality of partitions, each partition having its own error handler. The system further comprises a plurality of resources assignable to the plurality of partitions. The system further comprises management logic coupled to the plurality of partitions and the plurality of resources. The management logic comprises an error management tool that synchronizes operation of the error handlers in response to an error.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Anurupa Rajkumari, Andrew C. Walton, Howard Calkin
  • Publication number: 20110107139
    Abstract: Example apparatus, methods, and computers prevent a split brain scenario in a pair of high availability servers by maintaining single writer access to a resource by controlling the resource according to a timer bounded arbitration protocol that controls self-termination of a writer process. One example method includes monitoring control of an arbitration (ARB) block by an active file system manager (FSM) and selectively causing a selection of a standby metadata controller (MDC) when control of the ARB block does not satisfy the timer bounded ARB protocol. The example method also includes selectively forcing a hardware reset of an apparatus running the active FSM and selectively establishing an FSM on a selected redundant MDC as a replacement FSM.
    Type: Application
    Filed: June 23, 2010
    Publication date: May 5, 2011
    Applicant: QUANTUM CORPORATION
    Inventors: William J. MIDDLECAMP, Tim LaBERGE, John REINART
  • Publication number: 20110107012
    Abstract: A non-volatile semiconductor memory is disclosed comprising a first memory device having a memory array including a plurality of memory segments, and a data register for storing write data prior to being written to one of the memory segments. A memory controller comprises a microprocessor for executing access commands received from a host. Interface circuitry generates control signals that enable the microprocessor to communicate with the first memory device. Power fail circuitry transmits a flush command to the first memory device through the interface circuitry in response to a power fail signal, wherein the first memory device responds to the flush command by transferring the write data stored in the data register to the memory segment.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 5, 2011
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Alan Chingtao Kan
  • Publication number: 20110087917
    Abstract: A method for implementing a predetermined operation in device management, being based on a DM system defined by OMA, includes: sending by the device management system a second predetermined operation based on a trigger condition to a terminal device and storing by the terminal device the received second predetermined operation; and obtaining by the terminal device from itself the second predetermined operation and executing the second predetermined operation when the trigger condition is satisfied. The present invention also discloses an apparatus for implementing a predetermined operation in device management.
    Type: Application
    Filed: December 31, 2010
    Publication date: April 14, 2011
    Applicant: Huawei Technologies Co., Ltd.
    Inventor: Jiangshui He
  • Publication number: 20110083004
    Abstract: To perform recovery of a headless computer, a direct connection is established by the headless computer with a recovery computer over a network link. After establishing the direct connection, the headless computer is initiated in recovery mode. The headless computer receives a recovery routine from the recovery computer, and the recovery routine is executed in the headless computer to implement a procedure to receive a recovery image from the recovery computer. The recovery image upon loading in the headless computer causes loading of software for recovery of the headless computer.
    Type: Application
    Filed: October 7, 2009
    Publication date: April 7, 2011
    Inventors: Greg J. Lipinski, Paul A. Boerger
  • Publication number: 20110083044
    Abstract: A system and associated method for automatically correcting an application based on runtime behavior of the application. An incident indicates a performance of the application in which a problem object produces an outcome that had not been expected by a user or by a ticketing tool. An incident flow for the problem object is automatically analyzed. Actual run of the application renders a forward data flow and at least one backward data flow is simulated from an expected outcome of the problem object. The forward data flow and the backward data flow(s) are compared to create a candidate fault list for the problem object. A technical specification to correct the candidate fault list and a solution to replace the application are subsequently devised.
    Type: Application
    Filed: October 5, 2009
    Publication date: April 7, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: ANUP K. GHOSH
  • Publication number: 20110055628
    Abstract: A computer implemented method, apparatus, and computer program product for determining a state associated with a transaction for use with a transactional processing system comprising a transaction coordinator and a plurality of grouped and inter-connected resource managers, the method comprising the steps of: in response to a communications failure between the transaction coordinator and a first resource manager causing a transaction to have an in doubt state, connecting to a second resource manager; in response to the connecting step, sending by the transaction coordinator to the second resource manager, a query requesting data associated with the in doubt transaction; obtaining at the first resource manager, by the second resource manager, a shared lock to data associated with the in doubt transaction; and in response to the obtaining step, collating, by the second resource manager, data associated with the in doubt transaction associated with the first resource manager.
    Type: Application
    Filed: July 22, 2010
    Publication date: March 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul S. Dennis, Stephen J. Hobson, Pete Siddall, Jamie P. Squibb, Philip G. Willoughby
  • Publication number: 20110047405
    Abstract: Method and system for implementing a backup in a cluster comprising a plurality of interconnected nodes, at least one of the nodes comprising a cluster resource manager (CRM), and at least one of the nodes comprising a policy engine (PE), the PE maintaining at least one dependency associated with at least a first resource executing on at least one of the nodes. For example, the method comprises, receiving by the CRM a backup request for the first resource from an administrator; responsive to the request, updating by the CRM the cluster configuration; communicating by the CRM to the PE a cluster status and the updated configuration; providing by the PE to the CRM an instruction sequence for carrying out the backup, the instruction sequence based on the dependency associated with the first resource; and responsive to the instruction sequence, carrying out by the CRM the backup of the first resource.
    Type: Application
    Filed: August 21, 2009
    Publication date: February 24, 2011
    Applicant: Novell, Inc.
    Inventors: Lars Marowsky-Bree, Andrew John Beekhof
  • Publication number: 20110047407
    Abstract: Redundancy of data and/or Inline Power in a wired data telecommunications network from a first network device and a second network device configured as power sourcing equipment (PSE) devices and coupled together and to a third network device (such as a PD) via a Y device is provided by providing redundant signaling to/from each of the pair of network devices, and coupling a port of each of the network devices to the Y device and from there to a third port where a third network device such as a PD may be coupled. Because the Y device is essentially passive, communications paths between the PSE devices and the PD are provided for negotiating master/slave status and other status and related information among the respective network devices. Dynamic impedance matching is provided to handle situations where not all devices are plugged in and as a communications technique among the devices.
    Type: Application
    Filed: October 28, 2010
    Publication date: February 24, 2011
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Roger A. Karam, Luca Cafiero
  • Publication number: 20110035621
    Abstract: A system and method for communicating, browsing, verifying and routing data in storage operation systems using network attached storage devices is provided. In some embodiments, the system may include a management module and a media management component connected to the management server, which interoperate with network attached storage devices to provide the communicating, browsing, verifying and routing functions.
    Type: Application
    Filed: September 9, 2010
    Publication date: February 10, 2011
    Inventors: Duncan LITTLEFIELD, Ho-Chi CHEN, Rajiv KOTTOMTHARAYIL
  • Publication number: 20110035648
    Abstract: A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaver which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet.
    Type: Application
    Filed: October 19, 2010
    Publication date: February 10, 2011
    Inventors: In Hwan Choi, Kyung Won Kang, Kook Yeon Kwak, Byoung Gill Kim, Woo Chan Kim, Jae Hyung Kim, Hyoung Gon Lee, Jong Moon Kim
  • Publication number: 20110004730
    Abstract: A cache memory device that connects an instruction controlling unit outputting a memory access request for requesting data and a storage device storing data, the cache memory device including: a data memory unit that holds data for each cache line, a tag memory unit that holds, for each cache line linked with a cache line of the data memory unit, tag addresses specifying storage positions of data covered by the memory access request at the storage device and status data indicating states of the data of the data memory unit corresponding to the tag addresses, a search unit that searches for a cache line of the tag memory unit corresponding to an index address included in the memory access request, a comparison unit that compares a tag address held in the found cache line of the tag memory unit and a tag address included in the memory access request and, when the two do not match, detects a “cache miss” and reads out the status information of the found cache line, and a controlling unit that, when the compariso
    Type: Application
    Filed: June 30, 2010
    Publication date: January 6, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Hiroaki Kimura
  • Publication number: 20100332897
    Abstract: Power-backup capabilities are provided by implementing a variety of different methods, systems and devices. According to one such implementation, a solid-state memory device is implemented with a primary power source that provides primary power. A secondary power source provides secondary power. A power controller provides the primary power to an operating power circuit. The secondary power is provided by enabling a secondary switch located between the secondary power source and the operating power circuit. A solid-state memory uses power from the operating power circuit as a primary source of power when accessing stored data and retains data in the absence of power being provided by the operating power circuit. A memory controller facilitates access to the stored data. In response to problems with the primary power source, pending writes are completed to the solid-state memory circuit. A timing circuit substantially delays full enablement of the secondary switch.
    Type: Application
    Filed: December 7, 2009
    Publication date: December 30, 2010
    Inventor: Dean Clark Wilson
  • Publication number: 20100332890
    Abstract: A system and method are provided for virtual machine management. The system comprises a virtual machine manager, a blade server management module, at least one blade server, and a virtual machine manager. The virtual machine manager comprises an abnormal event receiving module for receiving information about a blade server having a hardware problem directly from the blade server management module and additionally a virtual machine management module for sending a processing command to a virtual machine hypervisor on the blade server having the hardware problem. The virtual machine management module receives the information about the hardware problem from the abnormal event receiving module. The processing command is determined in accordance with the information about the hardware problem and strategies for handling predefined hardware problems.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 30, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wei Chen, Wen Long Lan, Xian Dong Meng, Jian Xu
  • Publication number: 20100325495
    Abstract: The present invention is directed towards systems and methods for determining failure in and controlling access to a shared resource in a multi-core system. In some embodiments of a multi-core system, individual cores may share the same resource. Additionally, the resource may occasionally fail or need to be reset, and the period during which the resource is being reset may be non-instantaneous. In an embodiment without coordination between the cores, one core experiencing a failure may reset the resource. During the period in which the resource is resetting, another core may interpret the reset as a failure and reset the resource. As more cores interpret the resets as failures, they will trigger resets, quickly resulting in the resource being constantly reset and unavailable. Thus, in some embodiments, a coordination system may be utilized to determine failure of a shared resource and control resets and access to the shared resource.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 23, 2010
    Inventors: Ramanjaneyulu Y. Talla, Henk Bots, Abhishek Chauhan
  • Publication number: 20100325485
    Abstract: The present disclosure presents systems and methods for maintaining operation of stateful sessions by a secondary multi-core appliance upon failover of a first multi-core appliance. A stateful session failover module of primary appliance may receive session states from each of the cores of the primary appliance. The stateful session failover module may communicate the session states of the cores of the primary appliance to a stateful session failover module of the secondary appliance. The stateful session failover module of the secondary appliance may update each of the cores of the secondary appliance with the session states. Upon failover, cores of the secondary appliance may maintain operation and features of the sessions handled by the primary appliance prior to failover using the received state sessions for each session maintained.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 23, 2010
    Inventors: Sandeep Kamath, Sergey Verzunov
  • Publication number: 20100318842
    Abstract: According to one embodiment, a controller includes a receiver, an acquisition module, and a writer. The receiver receives information. The acquisition module acquires redundant information for correcting an error in the information. The writer writes the information to a first memory bank from a start address to a predetermined address of the first memory bank, and writes the redundant information to a second memory bank from the predetermined address to an end address of the second memory bank.
    Type: Application
    Filed: February 8, 2010
    Publication date: December 16, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kunio UTSUKI
  • Publication number: 20100313064
    Abstract: A status of connectivity between servers of different sites (locations) is used to infer whether a network or a server failure has occurred such that data between the servers can be routed more efficiently reducing unnecessary network traffic due to duplicate messages. Servers may be grouped based on location or other characteristics and connectivity status determined based on the communication status of individual servers and their respective groups.
    Type: Application
    Filed: June 8, 2009
    Publication date: December 9, 2010
    Applicant: Microsoft Corporation
    Inventors: Victor Boctor, Todd Luttinen
  • Publication number: 20100299553
    Abstract: Processing cache data includes sending a cache processing request to a master cache service node in a cache cluster that includes a plurality of cache service nodes, the cache cluster being configurable in an active cluster configuration mode wherein the plurality of cache service nodes are all in working state and a master cache service node is selected among the plurality of cache service nodes, or in a standby cluster configuration mode, wherein the master cache service node is the only node among the plurality of cache service nodes that is in working state. It further includes waiting for a response from the master cache service node, determining whether the master cache service node has failed; and in the event that the master cache service node has failed, selecting a backup cache service node.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 25, 2010
    Inventor: Wenchu Cen
  • Patent number: 7831767
    Abstract: An object of the present invention is to provide a means for detecting a logical command error, and a storage system and its control method that can properly perform error handling, and detection and blockage of a malfunctioning section. A storage control system includes controller units 130A and 130B for performing processing for data I/O to/from drives 150 and 160 in response to a data I/O request from a host device 100, switches 140A and 140B connecting the controller units 130A and 130B and the drives 150 and 160, and a port selector 300 inserted between the switches 140A and 140B and the drive 160. The port selector 300, when receiving a command generated based on processing performed by an MPU 131, accesses a target drive 160 if that data that forms a command is valid. Meanwhile, if the port selector 300 detects logical command inconsistency, the port selector 300 forwards that detection result to the MPU 131 via the switch 140A or 140B and requests retry processing from the MPU 131.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: November 9, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Akio Nakajima
  • Publication number: 20100281345
    Abstract: A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaves which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet.
    Type: Application
    Filed: July 12, 2010
    Publication date: November 4, 2010
    Inventors: In Hwan Choi, Kyung Won Kang, Kook Yeon Kwak, Byoung Gill Kim, Woo Chan Kim, Jae Hyung Kim, Hyoung Gon Lee, Jong Moon Kim
  • Publication number: 20100281346
    Abstract: A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaves which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet.
    Type: Application
    Filed: July 12, 2010
    Publication date: November 4, 2010
    Inventors: In Hwan Choi, Kyung Won Kang, Kook Yeon Kwak, Byoung Gill Kim, Woo Chan Kim, Jae Hyung Kim, Hyoung Gon Lee, Jong Moon Kim
  • Publication number: 20100281321
    Abstract: A method and apparatus for selectively replacing damaged portions of a data stream. The method comprises analyzing the data stream to identify damaged portions therein; selecting a damaged portion for replacement; and replacing the selected damaged portion. The selected damaged portion is selected for replacement in dependence on a rate of replacement, the rate of replacement being that at which previous portions of the data stream have been replaced.
    Type: Application
    Filed: May 1, 2009
    Publication date: November 4, 2010
    Applicant: CAMBRIDGE SILICON RADIO LIMITED
    Inventors: Xuejing Sun, Sameer Gadre, Scott Plude
  • Publication number: 20100281325
    Abstract: The present invention relates to a method for transmitting data packets from a mobile terminal to a base station using a hybrid automatic repeat request protocol and soft combining of received data. Further, the present invention provides a base station and a mobile terminal both adapted to perform the respective method steps. Moreover, a communication system is provided which comprises at least one base station and at least one mobile terminal. The present invention also provides a computer-readable medium for storing instructions that, when executed on a processor, cause the processor to transmit data packets from a mobile terminal to a base station using a hybrid automatic repeat request protocol and soft combining of received data. In order to restrict the interference caused by retransmissions, the present invention suggests controlling the amount of information in the retransmissions and thus the transmission power required for their transmission by TFCS restriction.
    Type: Application
    Filed: July 13, 2010
    Publication date: November 4, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Joachim Lohr, Eiko Seidel, Dragan Petrovic
  • Publication number: 20100251000
    Abstract: In embodiments of the present invention improved capabilities are described for runtime additive disinfection of malware. Runtime additive disinfection of malware may include performing the steps of identifying, based at least in part on its type, an executable software application that is suspected of being infected with malware, wherein the malware is adapted to perform a function during the execution of the executable software application, predicting the malware function based on known patterns of malware infection relating to the type executable software application, and in response to the prediction, adding a remediation software component to the executable software application that disables the executable software component from executing code that performs the predicted malware function.
    Type: Application
    Filed: March 27, 2009
    Publication date: September 30, 2010
    Inventors: James I.G. Lyne, Paul B. Ducklin
  • Publication number: 20100251006
    Abstract: A system and method provides for failover of guest operating systems in a virtual machine environment. During initialization of a computer executing a virtual machine operating system, a first guest operating system allocates a first memory region within a first domain and notifies a second guest operating system operating in a second domain of the allocated first memory region. Similarly, the second guest operating system allocates a second region of memory within the second domain and notifies the first operating system of the allocated second memory region. In the event of a software failure affecting one of the guest operating systems, the surviving guest operating system assumes the identity of the failed operating system and utilizes data stored within the shared memory region to replay to storage devices to render them consistent.
    Type: Application
    Filed: May 20, 2010
    Publication date: September 30, 2010
    Inventors: Garth Richard Goodson, Sai Susarla, Randal Thelen, Kiran Srinivasan
  • Publication number: 20100250750
    Abstract: A method and system for increasing server cluster availability by requiring at a minimum only one node and a quorum replica set of replica members to form and operate a cluster. Replica members maintain cluster operational data. A cluster operates when one node possesses a majority of replica members, which ensures that any new or surviving cluster includes consistent cluster operational data via at least one replica member from the immediately prior cluster. Arbitration provides exclusive ownership by one node of the replica members, including at cluster formation, and when the owning node fails. Arbitration uses a fast mutual exclusion algorithm and a reservation mechanism to challenge for and defend the exclusive reservation of each member. A quorum replica set algorithm brings members online and offline with data consistency, including updating unreconciled replica members, and ensures consistent read and update operations.
    Type: Application
    Filed: June 14, 2010
    Publication date: September 30, 2010
    Applicant: MICROSOFT CORPORATION
    Inventors: MICHAEL T. MASSA, DAVID A. DION, RAJSEKHAR DAS, RUSHABH A. DOSHI, DAVID B. LOMET, GOR V. NISHANOV, PHILIP A. BERNSTEIN, ROD N. GAMACHE, ROHIT JAIN, SUNITA SHRIVASTAVA
  • Publication number: 20100251052
    Abstract: Methods, media and systems are disclosed in which data is transferred from a data source apparatus to an application of a data receiving apparatus using both a first protocol and a second protocol. The data receiving apparatus identifies data received via the second protocol that has not been received via the first protocol, and delivers the identified data received via the second protocol to the application.
    Type: Application
    Filed: March 30, 2009
    Publication date: September 30, 2010
    Inventors: Mark D. Yarvis, Philip A. Muse, Lenitra M. Durham
  • Publication number: 20100232205
    Abstract: A memory includes an interface through which it provides access to memory cells, such as phase change memory cells. Such access permits circuitry located on a separate integrated circuit to provide access signals, including read and write signals suitable for binary or multi-level accesses.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 16, 2010
    Inventor: Ward Parkinson
  • Publication number: 20100211819
    Abstract: A method and device for controlling memory access in a computer system having at least two execution units, a buffer, in particular a cache being provided for each execution unit, and furthermore a switchover device and a comparison device being provided, the system switching between a performance mode and a compare mode, wherein in the performance mode each execution unit accesses the buffer assigned to it and in the compare mode both execution units access one buffer.
    Type: Application
    Filed: July 26, 2006
    Publication date: August 19, 2010
    Inventors: Reinhard Weiberle, Bernd Mueller, Eberhard Boehl, Yorck von Collani, Rainer Gmehlich
  • Patent number: 7779219
    Abstract: Techniques are provided for locating data. Mapping information for blocks associated with a file is provided. It is determined that a copy service has copied source blocks to target blocks. It is determined whether the mapping information should be updated to refer to the target blocks. Then, updated mapping information is provided in response to determining that the mapping information should be updated to refer to the target blocks.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Gregory Edward McBride, Cuong Minh Le, David Michael Shackelford
  • Publication number: 20100205496
    Abstract: Input messages are received at respective ports (10, 11, 12) of a message controller 4 from a plurality of external devices (100, 110, 120) which use different protocols. When an incoming message arrives at an input port a message object is created, the message object including a label identifying the respective input port. The conversion and subsequent handling of the messages uses program data which is retrieved from a program data store (5) according to the label indicating the input port. The program data retrieved is thus specified by the input port and allows conversion of messages into a common protocol to allow subsequent processing of the messages. This architecture allows the same program data to be called for external devices using the same protocol. Other processes may also be called from the program data store, covering functions such as validation, data enrichment, and exception handling processes.
    Type: Application
    Filed: June 7, 2007
    Publication date: August 12, 2010
    Inventors: Paul S. Boardman, Steven J. Smith, David L. Tullett
  • Publication number: 20100199148
    Abstract: An embodiment of the invention relates to a memory device and a related method. In an embodiment, a check matrix for an error-correcting code is formed so that sets of input data bits can be written, wherein each set of input data bits generates one set of error-correcting code bits that can be written independently of each other and in an arbitrary order. An error-correcting code is thereby produced without the need to erase or copy any existing, originally written bit upon presentation of new input data.
    Type: Application
    Filed: February 5, 2009
    Publication date: August 5, 2010
    Inventor: Jan Otterstedt
  • Publication number: 20100192036
    Abstract: A system for low density parity code decoding according to one embodiment includes a plurality of variable node (vnode) logic modules for sequentially processing groups of vnode values associated with a codeword and outputting updated vnode values; a vnode memory for storing the vnode values and updated vnode values; a plurality of check node (cnode) logic modules for sequentially processing groups of cnode values and outputting updated vnode values; a cnode memory for storing the cnode values and updated cnode values; and logic for checking the codeword using the updated vnode values and the updated cnode values. Additional systems and methods are also presented.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 29, 2010
    Inventors: Melanie Jean Sandberg, Matthew Michael Viens
  • Publication number: 20100192004
    Abstract: A system, method and program product for transferring structured and unstructured data in a service oriented architecture (SOA) infrastructure. A method is disclosed that includes: receiving a request for a synchronization at a service orchestration engine (SOE), wherein the synchronization includes a transfer of structured meta-data from a first node to a second node and a transfer of unstructured file data from a first file node to a second file node; creating an entry in a routing table to track the synchronization; receiving the structured meta-data at the SOE from the first node and transferring the structured meta-data to the second node; and orchestrating a peer-to-peer data transfer from the first file node to the second file node, including communicating with file handling agents at the first and second file handling nodes.
    Type: Application
    Filed: January 29, 2009
    Publication date: July 29, 2010
    Inventors: Frederic Bauchot, Hubert Lalanne
  • Publication number: 20100185922
    Abstract: A method of de-duplicating duplicate data in a data storage system that includes identifying a plurality of portions of data, comparing each portion of the data to identify duplicate data and identifying a link associated with each duplicate data, determining whether a Hamming link-separation-distance between the identified link and all other existing links is greater than twice the Hamming radius of an error correction code in the data storage system, and then replacing the duplicate data with the identified link.
    Type: Application
    Filed: January 16, 2009
    Publication date: July 22, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Haas, Nils Haustein, Craig Anthony Klein, Ulf Troppens, Daniel James Winarski
  • Publication number: 20100169742
    Abstract: In an embodiment, the invention provides a method for correcting soft errors in memory. A block of data is written in memory wherein all rows and all columns have a first checksum appended to it. A second checksum for each row and each column is generated after reading each row and each column from memory. The first and second checksum for each row and each column are compared for a compare such that when one and only one column has a miscompare, the logical value of any bit at an intersection of the one and only one column that has a miscompare and any row that has a miscompare is reversed.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Applicant: Texas Instruments Incorporated
    Inventor: Harland Glenn Hopkins
  • Publication number: 20100169240
    Abstract: Systems and methods for providing funds recovery for mailing machines including integrated circuits such as those used in postal security devices are described, and in certain configurations, systems and methods for recovering data such as postal funds records from a partially disabled single integrated circuit in a postal security device are described.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Robert J. Tolmie, JR., Douglas A. Clark, Mark A. Scribe
  • Publication number: 20100169735
    Abstract: Apparatus for optimizing low-density parity check (“LDPC”) decoding in a processor is disclosed herein. A processor in accordance with the present disclosure includes an LDPC decoder row update execution unit. The LDPC decoder row update execution unit accelerates an LDPC row update computation by performing a logarithm estimation and a magnitude minimization in parallel. The execution unit is activated by execution of an LDPC row update instruction. The execution unit adds a minimum of magnitudes of two input values to a difference of estimated logarithms of exponential functions of a sum and a difference of the two input values to produce a row update value.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Eric BISCONDI, David J. HOYLE, Tod D. WOLF
  • Publication number: 20100162032
    Abstract: Methods and systems for maintaining data connectivity in a secure data storage network are disclosed. In one aspect, a method includes assigning a volume to a primary secure storage appliance located in a secure data storage network the primary secure storage appliance selected from among a plurality of secure storage appliances located in the secure data storage network, the volume presented as a virtual disk to a client device and mapped to physical storage at each of a plurality of storage systems. The method further includes detecting at one of the plurality of secure storage appliances a failure of the primary secure storage appliance. The method also includes, upon detecting the failure of the primary secure storage appliance, reassigning the volume to a second secure storage appliance from among the plurality of secure storage appliances, thereby rendering the second secure storage appliance a new primary secure storage appliance.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Inventors: David Dodgson, Joseph Neill, Ralph Farina, Edward Chin, Albert French, Scott Summers
  • Publication number: 20100162083
    Abstract: An ECC controller comprises an ECC encoder, an ECC divider, an ECC constructor and an ECC decoder. The ECC encoder is configured to generate ECC data with different lengths in response to information data to be stored into a flash memory. The ECC divider is configured to divide each ECC datum generated by the ECC encoder into one or more ECC segments according to the length of the ECC datum. The ECC constructor is configured to generate an ECC datum by combining one or more ECC segments for each information datum read from the flash memory. The ECC decoder is configured to correct the errors of the information data read from the flash memory device by using the ECC data generated by the ECC constructor.
    Type: Application
    Filed: December 22, 2008
    Publication date: June 24, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: SHEN MING CHUNG, YI CHENG CHUNG
  • Publication number: 20100153638
    Abstract: There is provided a storage system and method of operating thereof. The storage system comprises a plurality of disk units adapted to store data at respective ranges of logical block addresses (LBAs), said addresses constituting an entire address space divided between a plurality of virtual partitions (VP), and a storage control grid operatively connected to the plurality of disk units and comprising a plurality of data servers, each server having direct or indirect access to the entire address space.
    Type: Application
    Filed: February 11, 2010
    Publication date: June 17, 2010
    Applicant: XSIGNNET LTD.
    Inventors: Yechiel YOCHAI, Leo CORRY, Haim KOPYLOVITZ
  • Publication number: 20100153774
    Abstract: A data storage system, method and a data storage and backup system are provided. The data storage method comprises defining a local storage of the data processing system as a journal vault; storing data in the journal vault by journaling; sending the data from the journal vault to a transmitter; and transmitting the data from the transmitter to a secondary storage. The present invention enhances a write function of a low performance storage device by journaling. In a case where the present invention is applied to a backup system, the performance of the whole backup system can be improved significantly, and the backup system can be extended to a remote site easily. When a storage of a production system fails, the storage system of the present invention can be switched to “production mode” and service resumes to be provided with the shortest downtime.
    Type: Application
    Filed: June 1, 2009
    Publication date: June 17, 2010
    Applicant: BIZCON SOLUTIONS LIMITED
    Inventors: Alex Li Tak Ho, Ping Shum, Jiajie Zheng, Kwun Hok Chang
  • Publication number: 20100153821
    Abstract: In a particular embodiment, a storage device is disclosed that includes a solid-state storage media. The storage device further includes a read/write circuit including an error correction coding (ECC) encoder/decoder adapted to write data and associated ECC information to the solid-state storage media without performing a read-verify operation.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Applicant: Seagate Technology LLC
    Inventors: Stanton MacDonough Keeler, John Edward Moon
  • Publication number: 20100146229
    Abstract: In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 10, 2010
    Applicant: LSI Corporation
    Inventors: Shaohua Yang, Changyou Xu, Weijun Tan, Ching-Fu Wu, Yuan Xing Lee
  • Publication number: 20100146348
    Abstract: A storage unit adapted for use in a processing system includes a controller including at least two compute nodes, each of the compute nodes including a read/write cache and a persistent cache; and machine executable instructions stored within machine readable media, the instructions including instructions for tracking in-flight data in the persistent cache and composing a list of the in-flight data segments after a failure of the controller. A processing system and a method are also provided.
    Type: Application
    Filed: December 8, 2008
    Publication date: June 10, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Aviad Zlotnick