Responding To The Occurrence Of A Fault, E.g., Fault Tolerance, Etc. (epo) Patents (Class 714/E11.021)

  • Publication number: 20080141070
    Abstract: Techniques for identifying UPS-sub-system interconnections using manual data, UPS identification signals, and variations in UPS voltage variations that produce error signals. Once interconnections have been identified an operating system can check the UPS/sub-system topology to isolate potential errors and/or to enable controlled shut-down of sub-systems in case of potential power failure.
    Type: Application
    Filed: February 20, 2008
    Publication date: June 12, 2008
    Inventors: Patrick K. Egan, Todd J. Rosedahl
  • Publication number: 20080141065
    Abstract: A parallel computer system automatically detects various troubles that may occur during computations using the parallel computer system so as to automatically cope with those troubles in such environment as in a design optimization using an evolutionary optimization in which a long time is required for one computation. A parallel computer system, includes a plurality of computing nodes for executing a calculation program and a master node connected to the computing nodes through networks, for performing a parallel computation process in an environment where a long time is required for one time computation as in a design optimization using an evolutionary algorithm.
    Type: Application
    Filed: November 13, 2007
    Publication date: June 12, 2008
    Inventor: Tatsuya Okabe
  • Publication number: 20080133942
    Abstract: A method of installing software on a storage device controlling apparatus which includes at least one channel controller having a circuit board on which are formed a file access processing section receiving requests to input and output data in files as units from an information processing apparatus via a first network and an I/O processor outputting I/O requests corresponding to the requests to input and output data to a storage device; at least one disk controller executing input and output of data into and from the storage device in response to the I/O requests sent from the I/O processor; and a second network connecting the channel controller and the disk controller so as to be able to communicate with each other, the method comprises the step of writing software for enabling the file access processing section to function, into the storage device by communicating with the channel controller via the second network.
    Type: Application
    Filed: November 8, 2007
    Publication date: June 5, 2008
    Applicant: Hitachi Ltd.
    Inventors: Hiroshi Ogasawara, Yutaka Takata, Naotaka Kobayashi, Jinichi Shikawa, Nobuyuki Saika
  • Publication number: 20080133960
    Abstract: A method and apparatus of a supply module having a business object module to least one schema to describe the supply chain data, a XML-based language module to process the at least one schema and a SQL code generator module to sequence of SQL instructions to perform a query of a user where the user the query in the XML-based language.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Inventors: Michael Kwok-Yui Wong, Kezheng Gan
  • Publication number: 20080134009
    Abstract: In a frame sync method, a receiver searches for the presence of an N-symbol long unique word pattern. For each possible frame sync detected, the receiver proceeds to demodulation and FEC processing. After each iteration of the FEC decoder, the detected unique word pattern is compared to the expected one and the frame sync is detected if the number of unique word errors has decreased.
    Type: Application
    Filed: May 2, 2007
    Publication date: June 5, 2008
    Applicant: INMARSAT GLOBAL LIMITED
    Inventors: Paul Febvre, Panagiotis Fines
  • Publication number: 20080133961
    Abstract: A debug card includes a controlling chipset and a VGA connector. The controlling chipset includes a data storage module, a data transforming module, and a VGA controller. The data storage module stores data received from a computer system, which represents the status of the computer system. The data transforming module transforms the data and transmits the transformed data to the VGA controller. The VGA connector interconnects the VGA controller and a VGA display to display the data.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHIEN-CHIH KAO, SHENG-PO CHUNG
  • Publication number: 20080126830
    Abstract: In operating a dual core processor, a register file collects a history of the error state information for each core. The core error state data can be analyzed to understand the recovery sequence of events. The recorded error sequence over time presents a detailed history of the recovery sequence which is useful to understand complex error scenarios.
    Type: Application
    Filed: September 16, 2006
    Publication date: May 29, 2008
    Inventors: Douglas G. Balazich, Michael Billeci, Anthony Saporito, Timothy J. Slegel
  • Publication number: 20080126879
    Abstract: A method and system for generating and obtaining reliable core dump from a multiple partitioned platform is described. The method generated a system core dump by a first operating system in a first partition, in response to detecting a predetermined event. The core dump may be stored in a shared memory accessible to a plurality of operating systems. An interrupt is sent when a core dump is generated. Upon a detection of the interrupt, the core dump may be accessed by a second operating system in a second partition for analysis. Other embodiments of inventions are described in the claims.
    Type: Application
    Filed: September 27, 2006
    Publication date: May 29, 2008
    Inventors: Rajeev Tiwari, Basheer Ahamed, Mansoor Ahamed, Padma Apparao
  • Publication number: 20080123781
    Abstract: A maximum a posteriori probability (MAP) block decoder for decoding a received data block of input samples. The MAP block decoder segments the received data block into at least a first segment and a second segment and calculates and stores alpha values during forward processing of the first segment. The MAP block decoder uses a first selected alpha value calculated during forward processing of the first segment as initial state information during forward processing of the second segment. The first and second segments may overlap each other, such that the last M samples of the first segment are the same as the first M samples of the second segment.
    Type: Application
    Filed: November 29, 2006
    Publication date: May 29, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eran Pisek, Thomas M. Henige
  • Publication number: 20080126849
    Abstract: Certain ones of a plurality of SAS hard disk drives are assigned to different SAS zones using a SAS zoning expander(s). A processor and SAS RAID controller have access to only those SAS hard disk drives assigned to the same zone(s) as the processor and SAS RAID controller. Each SAS RAID controller determines when a RAID hard disk drive in its zone fails, and then notifies the RAID hard disk drive failure to a service enclosure processor (SEP) of the SAS zoning expander. The SEP re-allocates an available hot-spare hard disk drive to the zone of the failed RAID hard disk drive. When the SAS RAID controller detects that a functional hard disk drive is now available in its zone, the RAID image is rebuilt using the zone reassigned hot-spare hard disk drive that then becomes one of the RAID hard disk drives of that zone.
    Type: Application
    Filed: August 28, 2006
    Publication date: May 29, 2008
    Applicant: Dell Products L.P.
    Inventors: Gary B. Kotzur, Kevin Marks
  • Publication number: 20080126780
    Abstract: Embodiments include methods, apparatus, and systems for containing machine check events in a virtual partition. One embodiment is a method of software execution. The method divides a hard partition into first and second virtual partitions and attempts to correct an error in a firmware layer of the first virtual partition.
    Type: Application
    Filed: September 20, 2006
    Publication date: May 29, 2008
    Inventors: Anurupa Rajkumari, Khoa D. Nguyen, Marvin Spinhirne
  • Publication number: 20080127177
    Abstract: A device and a portable storage device which are capable of transferring a rights object (RO) and a method of transferring an RO are provided. The method includes enabling a device to transmit an installation request message to a portable storage device for installing a copy of an original RO present in the device in the portable storage device, enabling the device to install the copy of the original RO in the portable storage device, and enabling the device to receive an installation response message indicating that the copy of the original RO has been successfully installed in the portable storage device from the portable storage device.
    Type: Application
    Filed: November 29, 2007
    Publication date: May 29, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yun-Sang OH, Sang-Gyoo Sim, Yeo-Jin Kim
  • Publication number: 20080120517
    Abstract: The aim of the present invention is to propose a method and a device with the aim of avoid the damage that the desynchronisation of the program counter could cause.
    Type: Application
    Filed: November 15, 2007
    Publication date: May 22, 2008
    Inventors: Christophe Gogniat, Michael John Hill
  • Publication number: 20080115012
    Abstract: A method and infrastructure for a diagnosis and/or repair mechanism in a computer system, that includes an auxiliary service system running on the computer system.
    Type: Application
    Filed: November 15, 2006
    Publication date: May 15, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joefon Jann, Pratap Chandra Pattnaik, Ramanjaneya Sarma Burugula
  • Publication number: 20080109413
    Abstract: A method and device are disclosed for an associative and approximate, analog or digital scanning of databases that allows for the asynchronous accessing of data from a mass storage medium. The invention includes providing dedicated analog and digital circuitry and decision logic at the mass storage medium level for determining a key identifying the data of interest, continuously comparing the key to a signal generated from a reading of the data from the mass storage medium with an approximate or exact matching circuit to determine a pattern match, determining a correlation value between the key and the data as it is read in a continuous fashion, and determining a match based upon a preselected threshold value for the correlation value. The pattern matching technique eliminates any need to compare data based on its intrinsic structure or value, and instead is based on an analog or digital pattern. The key and data may be either analog or digital.
    Type: Application
    Filed: October 31, 2007
    Publication date: May 8, 2008
    Inventors: Ronald Indeck, Ron Cytron, Mark Franklin
  • Publication number: 20080104485
    Abstract: In an embodiment, a source device encodes source information corresponding to a frame, assembles an initial data frame that includes the encoded data blocks, and transmits the initial data frame to a destination device. The destination device decodes the encoded data blocks and assembles a restored version of the initial data frame. The destination device identifies corrupted data blocks and uncorrupted data blocks within the restored version, stores the uncorrupted data blocks, generates a message that identifies the corrupted data blocks, and transmits the message to the source device. In response, the source device encodes source information corresponding to the corrupted data blocks identified in the message, assembles a responsive data frame, and transmits the responsive data frame to the destination device. The destination device produces a corrected data frame from the retransmitted data blocks and the previously-stored uncorrupted data blocks.
    Type: Application
    Filed: January 19, 2005
    Publication date: May 1, 2008
    Inventors: Mikhail Yurievich Lyakh, Konstantin Vladimirovich Zakharchenko, Oleg Borisovich Semenov
  • Publication number: 20080104445
    Abstract: A method of providing a RAID array, comprising providing an array of disks (202a-202f), creating an array layout (200) comprising a plurality of blocks (D1-D26, P1-P10) on each of the disks (202a-202f) and a plurality of disk stripes (204a-204j) that can be depicted in the layout (200) with the stripes parallel to one another and diagonal to the disks, and assigning data blocks (D1-D26) and parity blocks(P1-P10) in the array layout (200) with at least one parity block per disk stripe.
    Type: Application
    Filed: October 31, 2007
    Publication date: May 1, 2008
    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Srikanth ANANTHAMURTHY
  • Publication number: 20080098283
    Abstract: Transmission techniques are provided that improve service continuity and reduce interruptions in delivery of content that can be caused by techniques that occur when the User Equipment (UE) moves from one cell to the other, or when the delivery of content changes from Point-to-Point (PTP) connection to a Point-to-Multipoint (PTM) connection in the same serving cell, and vice-versa. Such transmission techniques enable seamless delivery of content across cell borders and/or between different transmission schemes such as Point-to-Multipoint (PTM) and Point-to-Point (PTP). Mechanisms for adjusting different streams and for recovering content from each data block during such transitions are also provided so that data is not lost during a transition. In addition, mechanisms for realigning data during decoding at a receiving terminal are also provided.
    Type: Application
    Filed: November 29, 2007
    Publication date: April 24, 2008
    Applicant: QUALCOMM Incorporated
    Inventors: Alkinoos Vayanos, Francesco Grilli
  • Publication number: 20080091974
    Abstract: Temperatures of four CPU cores of a multi-core CPU of a mobile body are detected. If the detected temperatures of the CPU cores become high, a clock setting register in a CPU clock-forming unit is set to the highest multiplying factor, and the CPU clock multiplying factors of the other clock setting registers are lowered. The clock frequencies of the CPU cores are lowered except a specified CPU core of a highest priority while maintaining the highest operation clock frequency for the specified CPU core, to thereby lower the temperature of the multi-core CPU. Alternatively, when the specified CPU core becomes abnormal, the processing assigned to it is reassigned to another CPU core of the plurality of CPU cores.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 17, 2008
    Applicant: DENSO CORPORATION
    Inventor: Yasuo Nakashima
  • Publication number: 20080092012
    Abstract: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust VSB data and reordered ATSC data are time multiplexed for transmission to a receiver. The receiver discards the reordered ATSC data or the normally ordered robust VSB data depending upon receiver type or user selection. A robust VSB receiver is able to process the normally ordered robust VSB data upstream of an outer decoder without an interleave thereby avoiding the delay associated with an interleave.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 17, 2008
    Inventors: Wayne Bretl, Richard Citta, Mark Fimoff
  • Publication number: 20080092011
    Abstract: A turbo decoding apparatus comprises: a backward-probability calculation unit that executes backward-probability calculation from time N to time 0 with respect to coded data having an information length N which is encoded with turbo-encoding; a storage unit to store backward-probability calculation results extracted from a plurality of continuous backward-probability calculation results regarding a predetermined section of at intervals of n-time; a forward-probability calculation unit that executes forward-probability calculation from time 0 to time N with respect to the coded data; and a decoded result calculation unit that calculates a decoded result of the coded data through joint-probability calculation using forward-probability calculation results by the forward-probability calculation unit and the backward-probability calculation results stored in the storage unit and backward-probability calculation results obtained through recalculation by the backward-probability calculation unit.
    Type: Application
    Filed: October 12, 2007
    Publication date: April 17, 2008
    Inventor: Norihiro Ikeda
  • Publication number: 20080092013
    Abstract: A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In addition to the memory, the system includes a write module and a read module, each of which is coupled to the memory. The write module is configured to receive a burst of data and write blocks of data from the burst into the memory. The write module is also configured to provide control information to the read logic. The control information includes a rolling burst counter and a burst profile bank identifier for each block. If interleaving is activated, the control information also includes information pertaining to how the read module should interleave the block. If interleaving is not activated, the control information also includes the byte length size of the burst. The read module reads blocks of data from memory in either an interleaved fashion or a non-interleaved fashion in accordance with the control information.
    Type: Application
    Filed: December 12, 2007
    Publication date: April 17, 2008
    Applicant: Broadcom Corporation
    Inventor: Scott HOLLUMS
  • Publication number: 20080092028
    Abstract: A decoding device includes a BM calculator calculating a branch metric in a Log-MAP algorithm from received data and extrinsic information, an ACS operator calculating a maximum value of a path metric based on the branch metric, a correction term calculator calculating a Jacobian correction value of the path metric, and a correction operator correcting the path metric by adjusting a value of the Jacobian correction value based on a size of the received data and adding the adjusted correction value to the maximum value.
    Type: Application
    Filed: October 15, 2007
    Publication date: April 17, 2008
    Applicant: NEC Electronics Corporation
    Inventor: Masao Orio
  • Publication number: 20080082861
    Abstract: An error processing method processes an error generated on a bus of a CPU, by inputting a bus error that is generated on at least one of an instruction bus and a data bus of the CPU to the CPU by a bus error input part, counting the bus error by a bus error counter part of the CPU, and specifying a region of a memory part that is coupled to the CPU based on a value of the bus error counter part.
    Type: Application
    Filed: July 26, 2007
    Publication date: April 3, 2008
    Applicant: Fujitsu Limited
    Inventor: Isao Sasazaki
  • Publication number: 20080082896
    Abstract: According to an example embodiment, a method may include determining an actual location (N) of a burst error in a data block; selecting a burst error pattern that is a correctable error based on adjusting an error pattern syndrome by an adjustment amount (S); and determining a correction vector based on the burst error pattern; shifting the correction vector by an offset amount based on (N) and (S); and correcting the burst error in the data block based on the shifted correction vector.
    Type: Application
    Filed: August 17, 2007
    Publication date: April 3, 2008
    Applicant: Broadcom Corporation
    Inventors: Magesh Valliappan, Velu Pillai
  • Publication number: 20080082866
    Abstract: The embodiments of the present invention disclose a method for isolating a bus failure, which includes: acquiring, from a Compact PCI bus, an address of a target board being accessed; counting retry responses on the Compact PCI bus, wherein the retry responses are generated by access to the target board; sending a reset signal to the target board in response to that the times of the retry responses exceed a retry times threshold. With the embodiments of this invention, the normal operation of a failed device in the system may be restored in time, which may avoid that the bus is hanged up and is favorable for maintenance.
    Type: Application
    Filed: August 22, 2007
    Publication date: April 3, 2008
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Yansong LI
  • Publication number: 20080077838
    Abstract: Apparatus, and an associated method, that reduces the occurrence of generation of redundant requests for retransmission of packet-formatted data, formatted at a physical layer and at a higher-logical layer, such as at an RLP layer. An estimate of an appropriate delay period is formed. The estimate is responsive to communication conditions in the communication system. When a data packet appears to have been inadequately delivered to the RLP logical layer, a DELAY_DETECTION_WINDOW timer is caused to time out the delay period estimated by the estimator. The request for retransmission, generated at the RLP layer, is permitted, upon expiration of the timer if the data packet has not yet been successfully delivered to the RLP layer and the transmitter has not given up the data packet delivery.
    Type: Application
    Filed: October 8, 2007
    Publication date: March 27, 2008
    Inventors: Liangchi Hsu, Mark Cheng
  • Publication number: 20080065937
    Abstract: Basic redundancy information is non-volatily stored in a reserved area of an addressable area of a memory array, and is copied to volatile storage therein at every power-on of the memory device. The unpredictable though statistically inevitable presence of failed array elements in such a reserved area of the memory array corrupts the basic redundancy information established during the test-on wafer (EWS) phase of the fabrication process. This increases the number of rejects, and lowers the yield of the fabrication process. This problem is addressed by writing the basic redundancy data in the reserved area of the array with an ECC technique using a certain error correction code. The error correction code may be chosen among majority codes 3, 5, 7, 15 and the like, or the Hamming code for 1, 2, 3 or more errors, as a function of the fail probability of a memory cell as determined by the EWS phase during fabrication.
    Type: Application
    Filed: September 13, 2007
    Publication date: March 13, 2008
    Applicants: STMicroelectronics S.r.I., Hynix Semiconductor Inc.
    Inventors: Rino Micheloni, Roberto Ravasio, Alessia Marelli
  • Publication number: 20080059832
    Abstract: The invention provides a system attached to a laser beam machine for supporting failure prognosis, warning and restoration operation by monitoring the status of the machine. A laser beam machine 1 has a pallet 20 supported on a bed 10, and subjects a work W1 to laser processing. The management unit 100 attached to the machine 1 is connected via an internet connection to a server 2 at a service center, and also transmits the status of the machine to a cellular phone 3 or a personal computer 4 of an administrator. The management unit 100 has a large image display unit 200, through which the status of the machine is output via messages and audio so as to notify the operator of necessary restoration operations. The procedures of restoration operations are output via image and message, supporting the operation of the operator.
    Type: Application
    Filed: May 11, 2007
    Publication date: March 6, 2008
    Inventors: Tsunehiko Yamazaki, Naoomi Miyakawa
  • Publication number: 20080059862
    Abstract: An apparatus and method for transmitting/receiving a signal in a communication system are provided. A signal reception apparatus of a communication system receives a signal and generates a child Low Density Parity Check (LDPC) codeword vector by decoding the received signal according to a child parity check matrix supporting a first coding rate. The child LDPC codeword vector includes an information vector including A (A?1) information bits, and when the first coding rate is equal to a coding rate for a case where D (D?1) parity bits are punctured among B (B?1)+C (C?1) parity bits included in a parent LDPC codeword vector generated by encoding the information vector according to a parent parity check matrix supporting a second coding rate, a child bipartite graph corresponding to the child parity check matrix is generated such that a parent bipartite graph corresponding to the parent parity check matrix corresponds to an edge merge scheme.
    Type: Application
    Filed: September 4, 2007
    Publication date: March 6, 2008
    Applicant: Samsung Electronics Co., LTD.
    Inventors: Gyu-Bum KYUNG, Seung-Hoon Choi, Hong-Sil Jeong, Dong-Seek Park, Jae-Yeol Kim
  • Publication number: 20080052563
    Abstract: An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an input of a delay circuit and delaying the signal between the input of the delay circuit and an output of the delay circuit for a predetermined amount of time. If a low voltage is detected on the signal after the predetermined amount of time, the high voltage is prevented from propagating to the output of the delay circuit.
    Type: Application
    Filed: May 31, 2007
    Publication date: February 28, 2008
    Applicant: DELL PRODUCTS L.P.
    Inventor: Leroy Jones
  • Publication number: 20080052590
    Abstract: Provided is a method and system for reliably multicasting a data transmission from a server to one or more clients, which may be connected via a control channel and a multicast data channel. In one example, the method includes sending a first data transmission to the clients over the multicast data channel. A response is received over the control channel from at least some of the clients. The response identifies data not received by the responding client. In some examples, the response may indicate that all the data was received. The server determines a minimum retransmission data set based on the responses. The minimum retransmission data set includes at least some of the data not received by the client during the first data transmission. The minimum retransmission data set is sent over the multicast data channel and received by the clients that did not receive it during the first data transmission.
    Type: Application
    Filed: October 29, 2007
    Publication date: February 28, 2008
    Applicant: NOVELL, INC.
    Inventor: Shekhar AMLEKAR
  • Publication number: 20080040543
    Abstract: Times at which requests for a data read or data write from/to a logical volume are received are stored in memory as access times of a RAID group making up the logical volume. When a predetermined time has elapsed after the access time, a number of the hard disk drives according to the redundancy of the RAID group are set to a power saving mode. Assume there are first hard disk drives and second hard disk drives having shorter lifes and the RAID group exceeds a predetermined time after the access time. When the RAID group consists of only the first drives, a number of the first drives according to the redundancy of the RAID group are set to a power saving mode and when it consists of only the second drives, an arbitrary number of second drives are set to a power saving mode.
    Type: Application
    Filed: August 24, 2007
    Publication date: February 14, 2008
    Inventors: Takashi Yamazaki, Kazuo Hakamata, Azuma Kano
  • Publication number: 20080005608
    Abstract: A method and computer program product for error monitoring partitions in a computer system. A partition status buffer (PSB) denotes a status (GOOD, BAD, NOCARE) of each partition of at least two partitions. The BAD status denotes that the partition has encountered at least one error that is currently unrepaired. A global supervisor mapping (GSM) associates each partition (designated as a supervised partition) with a supervisor partition in a one-to-one mapping. The supervisor partition determines its supervised partition from the GSM and ascertains the status of its supervised partition from the PSB. If the status of the supervised partition is BAD then the supervisor partition performs a recovery procedure. The recovery procedure: obtains a grant of access to physical and logical resources of the supervised partition which contains error data of the supervised partition; gathers the error data; sets the status of the supervised partition to the NOCARE status.
    Type: Application
    Filed: September 18, 2007
    Publication date: January 3, 2008
    Inventors: Preetha Kondajeri, Ravi Kulkarni, Manish Misra