In Memories (epo) Patents (Class 714/E11.034)
  • Patent number: 8914704
    Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Debaleena Das, Kai Cheng, Jonathan C. Jasper
  • Patent number: 8898539
    Abstract: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 25, 2014
    Assignee: LSI Corporation
    Inventors: Yang Han, Shaohua Yang, Zongwang Li, Fan Zhang, Anatoli A. Bolotov, Mikhail I. Grinchuk, Paul G. Filseth, Lav D. Ivanovic
  • Patent number: 8826099
    Abstract: According to one embodiment, a memory controller that controls a non-volatile semiconductor memory including a memory cell of 3 bits/cell includes a controller that extracts bits which becomes an error caused by the movement to the adjacent threshold voltage distribution from a first bit and a second bit of data to be written in each of the memory cells to generate a virtual page and an encoding unit that generate an error correcting code for the virtual page and writes the data for three pages and the error correcting code in the non-volatile semiconductor memory.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tokumasa Hara, Osamu Torii
  • Publication number: 20140143630
    Abstract: In accordance with at least one embodiment, a method and apparatus for improving the ability to correct errors in memory devices is described. At least one embodiment provides a way to salvage the part even it has double-bit or multi-bit error from the same ECC section, thus improving product reliability and extending the product lifetime. During a normal read, if a double-bit or multiple-bit error happens, which ECC can detect but cannot fix, the error is corrected by adjusting the read voltage level and reading again to determine the proper read level (and, therefore, the correct value being read). This dynamic read scheme can apply to extrinsic bits from either erase state or program state. It can be also used in a single bit scenario to minimize ECC occurrence and save ECC capacity.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Inventors: Fuchen Mu, Yanzhou Wang
  • Publication number: 20140129874
    Abstract: A method includes, in a non-volatile memory that includes multiple memory blocks, defining a redundancy zone that includes at least an old parity block, a new parity block and multiple active blocks of which one block is defined as an open block. Data is stored in the redundancy zone and the stored data is protected, such that new input data is stored in the open block, redundancy information for the active blocks including the open block is stored in the new parity block, and the redundancy information for the active blocks excluding the open block is stored in the old parity block. Upon filling the open block and the new parity block, an alternative block is assigned to serve as the open block and the new parity block is assigned to serve as the old parity block.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: APPLE INC.
    Inventors: Etai Zaltsman, Julian Vlaiko, Ori Moshe Stern, Avraham Poza Meir
  • Publication number: 20140129905
    Abstract: Various embodiments of the present inventions provide systems and methods for data processing with a flexible LDPC seed.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: LSI CORPORATION
    Inventors: Lei Chen, Shaohua Yang, Johnson Yen
  • Publication number: 20140129896
    Abstract: Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide a first result and to decode a second codeword to provide a second result. The decoder is configured to run up to a particular number of iterations to provide each of the results. A second ECC decoder is configured to decode a third codeword to provide decoded data, wherein the third codeword comprises the first result and the second result. An evaluation module is configured to initiate a recovery scheme responsive to the decoded data including an error.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Sivagnanam Parthasarathy, Mustafa Nazmi Kaynak, Patrick Robert Khayat
  • Publication number: 20140122971
    Abstract: A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Applicant: LSI CORPORATION
    Inventors: Zongwang Li, Lei Chen, Shaohua Yang, Johnson Yen
  • Publication number: 20140122963
    Abstract: Embodiments of apparatus, methods, storage drives, computer-readable media, systems and devices are described herein for identification of die of non-volatile memory for use in remedial action. In various embodiments, a first block may be configured to encode data to be stored in a non-volatile memory as a codeword. In various embodiments, the first block may be configured to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory. In various embodiments, the first block may be configured to generate respective error detection codes for the plurality of die.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Inventors: Ravi H. Motwani, Kiran Pangal
  • Publication number: 20140115422
    Abstract: Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (CAM) to perform logical address translation, b) a minimum CAM function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ECC) method as needed to correct for degrading storage, and/or d) serially generating ECC and using an ECC serial decoder to correct the data.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 24, 2014
    Inventor: Laurence H. Cooke
  • Publication number: 20140101515
    Abstract: A technique for recovering of “squeezed” sectors in a set of sequential sectors such as are used in Shingled Magnetic Recording (SMR) is described. Embodiments of the invention use a programmable erased sector recovery scheme, which is a concatenation of a “Cauchy-type” track erasure correction code, together with a media-error correction code that generates N-weighted parity-sectors per track and is capable of replacing up to N-erased sectors per track in any possible combination.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: HGST NETHERLANDS B.V.
    Inventors: Kei Akiyama, Sridhar Chatradhi, Jonathan Darrel Coker, Martin Aureliano Hassner, Kirk Hwang, Roger William Wood
  • Publication number: 20140101517
    Abstract: A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: HGST NETHERLANDS B.V.
    Inventors: Robert Eugeniu Mateescu, Luiz Franca-Neto, Cyril Guyot, Hessam Mahdavifar, Zvonimir Bandic, Qingbo Wang
  • Publication number: 20140101516
    Abstract: A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix. Each row of the first matrix corresponds to a unique one of the data bits. The control circuit is operable to generate a second matrix having only the rows of the first matrix that correspond to the data bits provided for storage in a subset of the memory cells having stuck-at faults. The control circuit is operable to generate a third matrix having linearly independent columns of the second matrix. The control circuit is operable to encode the data bits to generate encoded data bits and redundant bits using the third matrix.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: HGST NETHERLANDS B.V.
    Inventors: Robert Eugeniu Mateescu, Luiz Franca-Neto, Cyril Guyot, Hessam Mahdavifar, Zvonimir Bandic, Qingbo Wang
  • Publication number: 20140101511
    Abstract: A method, an apparatus, and a computer program product for optimally tuning a memory card in a host device are provided. The apparatus determines at least one tuning parameter associated with the memory card, initiates a reading operation with the memory card, and sends a tuning command to the memory card based on the at least one tuning parameter. The at least one tuning parameter includes a temperature of the memory card, a time elapsed since a last tuning sequence was performed, a number of data blocks sent from the memory card to the host device, and/or a number of transactions between the memory card and the host device. The apparatus also reads data from the memory card, detects a cyclic redundancy check (CRC) error associated with the read data, and sends the tuning command to the memory card upon detecting the CRC error.
    Type: Application
    Filed: November 8, 2012
    Publication date: April 10, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Nir Strauss, Racheli Angel Manor
  • Publication number: 20140101501
    Abstract: An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer. The scan test circuitry is configured to control at least a given one of the scan cells so as to prevent violation of the select signal constraint in conjunction with scan testing. The multiplexer may be, for example, a one-hot multiplexer for which the select signal constraint indicates that only one of the select signal inputs should receive a logic high select signal at a particular time.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 10, 2014
    Applicant: LSI Corporation
    Inventors: Narendra B. Devta Prasanna, Ramesh C. Tekumalla
  • Publication number: 20140095961
    Abstract: A system is described for recovering data from a number of sectors, such as the sectors of a hard disk drive (HDD) disk platter, and so forth. The system receives data from the sectors via a read channel and uses a layered data decoder to recover data from the sectors. A memory is coupled with the processor and configured to retain data received from one or more of the sectors, e.g., in retained sector reprocessing (RSR) embodiments. The system is configured to update messages in different circulant layers of the data decoder's parity-check matrix. The system uses one message update order in a processing iteration, and different message update orders in subsequent reprocessing iterations. In some embodiments, layer reordering is used for RSR. In some embodiments, circulant reordering is used for RSR.
    Type: Application
    Filed: October 3, 2012
    Publication date: April 3, 2014
    Applicant: LSI Corporation
    Inventors: Fan Zhang, Jun Xiao
  • Publication number: 20140089761
    Abstract: A memory controller to detect for an unintentional access to an incorrect location of a memory device and to provide error detection for data retrieved from an intended location of the memory device. In an embodiment, the memory controller services a read request, including retrieving data and an error correction code from a memory location. In another embodiment, the retrieved error correction code is evaluated, based on a combination of the retrieved data and an address identifier of the read request, to determine whether the address identifier of the read request corresponds to the memory location from which the data and error correction code were retrieved.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Inventor: Zion Kwok
  • Publication number: 20140089769
    Abstract: Aspects of the disclosure pertain to a system and method for promoting improved error detection efficiency in a Content-Addressable Memory (CAM). The system and method provide CAM continuous error detection with interleave parity. The system continuously monitors for changes in cell contents and, when (e.g., as soon as) a soft error occurs, the error detection output bit for that entry will change, causing an error flag at chip level. The system can then immediately stop compare operations and rewrite the failing entry. Separate read operations are not needed to check for errors, thereby decreasing overall dynamic power usage and increasing possible search frequency for the system.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: LSI Corporation
    Inventors: Gordon W. Priebe, Carl W. Swanson, David B. Grover, Christopher D. Browning
  • Publication number: 20140082438
    Abstract: A one-time program cell array circuit includes a cell array configured to include a plurality of one-time program memory cells, and to program an inputted program data and output a stored program data as a read data, a code generation circuit configured to generate an error correction code to be programmed in the cell array based on the inputted program data during a program operation; and an error detection circuit configured to detect an error of the read data based on the error correction code and the read data that are outputted from the cell array during a read operation and to be enabled or disabled in response to a first enable signal. The concern caused by applying the error correction scheme to the one-time program cell array circuit may be resolved by controlling the enabling or disabling of an error correction scheme, while increasing reliability.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Inventors: Hyunsu YOON, Youncheul Kim, Kwanweon Kim, Jeongtae Hwang
  • Publication number: 20140075264
    Abstract: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: LSI Corporation
    Inventors: Yang Han, Shaohua Yang, Zongwang Li, Fan Zhang, Anatoli A. Bolotov, Mikhail I. Grinchuk, Paul G. Filseth, Lav D. Ivanovic
  • Publication number: 20140075268
    Abstract: A method for dodging bad page and bad block caused by suddenly power off is disclosed. This method is to avoid a new data from host program to potential hurt block or page caused by power off during NAND flash erasing or programming.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Inventor: Chi Nan Yen
  • Publication number: 20140075265
    Abstract: The present invention provides a method of operating a memory device storing error correcting codes ECCs for corresponding data and including ECC logic to correct errors using the ECCs. The method includes correcting data using ECCs for the data on the memory device, and producing information on the memory device about the use of the ECCs. The method provides the ECC information on an output port of the device in response to a command received on an input port from a process external to the memory device. The present invention also provides a method of controlling a memory device. The method includes sending a command to the memory device requesting ECC information corresponding to data in the memory device, and receiving the ECC information from the memory device in response to the command. The method includes performing a memory management function using the ECC information.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Hsin Yi Ho
  • Publication number: 20140068375
    Abstract: The present invention provides a low density parity check (LDPC) code system and method of using such a system. A transmitted LDPC code block size may be chosen such that the minimum transmitted block size is minimized. Further, the system provides for intermediate LDPC code block size support. Finally, a common decoder architecture may be used to decode different LDPC code rates and block sizes.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Applicant: Hughes Network Systems, LLC
    Inventors: Mustafa Eroz, Lin-Nan Lee
  • Publication number: 20140068373
    Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Michael J. Osborn, Mark D. Hummel, David E. Mayhew
  • Publication number: 20140047300
    Abstract: A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module.
    Type: Application
    Filed: October 28, 2012
    Publication date: February 13, 2014
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Li-Chun Liang, Tien-Ching Wang, Kuo-Hsin Lai
  • Publication number: 20140047296
    Abstract: A memory system provides Error Correcting Code (ECC) protection for data stored in a parity enabled memory. The memory may include designated parity locations for data stored in the memory. During write operations, the system may obtain data to write into the memory, compute ECC protection bits for the data, and store the ECC protection bits in locations in the memory designated as parity locations for the data. During read operations, the system may read data from the memory. The system may also read protection bits for the data from locations designated as parity locations for the data. Then, the system may interpret the protection bits as ECC protection bits instead of as parity bits. The system may provide ECC protection for data without additional overhead or memory configuration changes to the parity enabled memory.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: Broadcom Corporation
    Inventors: Iraj Motabar, Morteza Cyrus Afghahi
  • Publication number: 20140040697
    Abstract: A system for detecting an address or data error in a memory system. During operation, the system stores a data block to an address by: calculating a hash of the address; using the calculated hash and data bits from the data block to compute ECC check bits; and storing the data block containing the data bits and the ECC check bits at the address. During a subsequent retrieval operation, the memory system uses the address to retrieve the data block containing the data bits and ECC check bits. Next, the system calculates a hash of the address and uses the calculated hash and the data bits to compute ECC check bits. Finally, the system compares the computed ECC check bits with the retrieved ECC check bits to determine whether an error exists in the address or data bits, or if a data corruption indicator is set.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventor: Paul N. Loewenstein
  • Publication number: 20140026011
    Abstract: A dynamic error correcting table can be embedded on an integrated circuit memory device. The error correcting table includes entries which are created for data when an error is detected and corrected during a read of the data. During subsequent reads, without intervening write or refresh operations, the entry in the table can be used to correct the error by merging the corrected bit with the data output from the array before it is applied to the ECC logic.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: Shih-Chang Huang, Han-Sung Chen
  • Publication number: 20140013187
    Abstract: A method includes receiving a request to read data at a data storage device from an external device. In response to determining that the data is in a first memory of the data storage device, a first read operation is initiated to read the data from the first memory and a response is sent to the external device. The response indicates an error correction code (ECC) error. A read latency of the first read operation exceeds a reply time period corresponding to the request. The response is sent prior to completion of the first read operation and within reply time period.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 9, 2014
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventor: MORDECHAI BLAUNSTEIN
  • Publication number: 20140006905
    Abstract: The present invention is related to systems and methods for serial application of different decode algorithms to a processing data set.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Inventor: Fan Zhang
  • Publication number: 20140006899
    Abstract: A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: DEBALEENA DAS, KAI CHENG, JONATHAN C. JASPER
  • Publication number: 20140006898
    Abstract: A system and method for partitioning data in long term memory of a flash memory device is disclosed. The method may include the steps of identifying a type of data that has been received and routing the data to one of at least two partitions in the long term memory array. One partition of the flash memory device may be optimized for random data while another is optimized for sequential data. The method includes identifying the type of data and routing the data to the appropriate partition. Data may be analyzed and routed upon receipt or initially stored in a default partition and later analyzed and routed to another partition. The partition for random data may be configured for storing data using a first level of ECC protection while the second may be configured for storing data using a second, stronger level of ECC protection.
    Type: Application
    Filed: July 2, 2012
    Publication date: January 2, 2014
    Inventors: Eran Sharon, Idan Alrod
  • Publication number: 20130339818
    Abstract: A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: CARINGO, INC.
    Inventors: Don BAKER, Paul R.M. CARPENTIER, Andrew KLAGER, Aaron PIERCE, Jonathan RING, Russell TURPIN, David YOAKLEY
  • Publication number: 20130332796
    Abstract: A method of operation of a storage control system includes: generating encoded data having a proportional data distribution for writing to a memory device; identifying a marginal block when an erase block is read from the memory device; and generating a marginal tag for the marginal block, the marginal tag having a non-proportional data distribution different from the proportional data distribution.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Applicant: SMART Storage Systems, Inc.
    Inventor: Robert W. Ellis
  • Publication number: 20130305119
    Abstract: The invention relates to a device and a method for storing binary data in a storage device, in which the binary data is transformed to and stored as ternary data. The storage device uses memory cells capable of storing three states. The device and method furthermore are configured to identify and correct falsified ternary data when reading and outputting the data from storage device.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 14, 2013
    Applicant: Infineon Technologies AG
    Inventors: Thomas Kern, Michael Goessei
  • Publication number: 20130297986
    Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: LSI CORPORATION
    Inventor: Earl T. Cohen
  • Publication number: 20130290808
    Abstract: A method of erasing a non-volatile semiconductor memory device comprising determining a number of bit cells that failed to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further comprises determining whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The erase operation is considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Inventors: Fuchen Mu, Frank K. Baker, JR., Chen He
  • Publication number: 20130283126
    Abstract: Embodiments of systems and methods for detecting errors that occur in association with an access to a memory and providing an associated error status are presented herein. According to one embodiment, an access to a memory may be received, where the access comprises a request tag. A request parity is determined based on the request tag and a stored tag and a stored parity associated with the request tag are also determined. An error correction status is determined based on the stored tag and the stored parity associated with the request tag. Additionally, a parity hotness is determined by comparing the request parity and the stored parity and a tag hotness is determined by comparing the request tag and the stored tag. An error status associated with the access is determined based on the parity hotness, the tag hotness and the error correction status.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Ravindraraj RAMARAJU
  • Publication number: 20130262957
    Abstract: An apparatus is provided that comprises a processor. The processor comprises a cache to store data, a decoder, an error classification module, and an error correction module. The cache stores data, the data encoded as a codeword. The decoder reads the codeword from cache and calculates a syndrome of the codeword using an H-matrix. The error classification module determines an error type of the syndrome. The H-matrix is redesigned such that the columns form a geometrical sequence, and as a result not only the t-bit random errors but also (t+1) bit adjacent errors can be corrected. The error correction module, triggered by the enhanced error classification module, takes one of two sets of inputs depends on the error type (either random or adjacent error) and produces corrected data from the syndrome when the syndrome comprises a detectable and correctable error.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Wei Wu, Shih-Lien L. Lu, Muhammad M. Khellah
  • Publication number: 20130254623
    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 26, 2013
    Inventors: Shaohua Yang, Lav D. Ivanovic, Fan Zhang, Douglas M. Hamilton
  • Publication number: 20130246895
    Abstract: Subject matter disclosed herein relates to methods and/or apparatuses, such as an apparatus that includes first and second groups of memory cells. The first group of memory cells stores multiple digits of program data per memory cell. The second group of memory cells stores a parity symbol per memory cell. Other apparatuses and/or methods are disclosed.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Christophe Laurent, Paolo Amato, Richard Fackenthal
  • Publication number: 20130238955
    Abstract: A method includes initiating a first decode operation of data at an error correction code (ECC) hard bit decoder in a data storage device that includes a controller and a memory. The method further includes, in response to the first decode operation indicating that the data is uncorrectable by the first decode operation, identifying one or more bits of the data that correspond to a disturb condition test pattern, changing a value of the one or more identified bits of the data to generate modified data, and initiating a second decode operation at the ECC hard bit decoder using the modified data.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: MANUEL ANTONIO D'ABREU, STEPHEN SKALA
  • Publication number: 20130238958
    Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Inventor: William Henry Radke
  • Publication number: 20130219244
    Abstract: A nonvolatile memory is configured with blocks as deletion units, each block having several pages that are configured as write units. A controller for the nonvolatile memory includes an error correcting circuit, which detects and corrects an error in data read out of a page in one of the blocks of the nonvolatile memory, the page being referenced by a logical address. The controller also determines an error occurrence when the error cannot be corrected. An error block table is provided to store the logical address where the error occurred, and a physical address corresponding to the logical address.
    Type: Application
    Filed: August 30, 2012
    Publication date: August 22, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeaki KATO, Hitoshi Shimono, Akinori Kamizono
  • Publication number: 20130212448
    Abstract: A method includes receiving data from a buffer of a non-volatile memory. An error correction coding (ECC) operation is initiated to correct bit errors in the data. Correction data is sent to the buffer to correct the bit errors in the data.
    Type: Application
    Filed: March 19, 2012
    Publication date: August 15, 2013
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventor: OMPRAKASH BISEN
  • Publication number: 20130212450
    Abstract: A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder (10) for partial parallel decoding of low-density parity-check convolutional codes, the decoder comprising: a plurality of pipeline processors (11) to receive channel messages and edge-messages; each processor (11) having: a plurality of block processing units (BPUs) (13), each BPU (13) having a plurality of check node processors (CNPs) (14) to process check nodes that enter into the processor (11) and a plurality of variable node processors (VNPs) (15) to process variable nodes that are about to leave the processor (11); and a plurality of Random Access Memory (RAM) blocks (30) for dynamic message storage of the channel messages and the edge-messages; wherein in each processor (11), the VNPs (15) are directly connected to corresponding RAM blocks (30), and the CNPs (14) are directly connected to corresponding RAM blocks (30) such that the connections from the VNPs (15) and CNPs (14) to the corresponding RAM blocks (30) are pre-defined and fixed a
    Type: Application
    Filed: February 10, 2012
    Publication date: August 15, 2013
    Inventors: Chiu Wing SHAM, Xu Chen, Chung Ming Lau, Yue Zhao, Wai Man Tam
  • Publication number: 20130212447
    Abstract: Various embodiments of the present invention provide systems and methods for decoding of non-binary LDPC codes. For example, a low density parity check data decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node message vectors, a check node processor operable to perform check node updates and to generate the check node to variable node message vectors, and a scheduler operable to cause the variable node processor to use check node to variable node message vectors from multiple decoding iterations when performing the variable node updates for a given decoding iteration.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Inventors: Zongwang Li, Chung-Li Wang, Changyou Xu
  • Publication number: 20130205181
    Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving and arranging read data in array that includes m rows and n columns of entries, with each entry including at least one sector. In the array, mr+s locations are assigned to parity entries, such that each row has at least r parity entries. The parity entries correspond to a partial-maximum distance separable (PMDS) code that allows recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s is an integer greater than zero. The write data and the associated parity entries are written to the set of storage devices.
    Type: Application
    Filed: February 2, 2012
    Publication date: August 8, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
  • Publication number: 20130205182
    Abstract: An apparatus for a dual mode low density parity check (LDPC) decoder including edge random access memory (RAM), last-in-first-out/first-in-first-out (LIFO/FIFO) RAM, channel RAM, and parallel datapath engines, where the datapath engines include a standard belief propagation decoding (SBD) datapath and a layered belief propagation decoding (LBD) datapath, where the SBD datapath includes a shifter, an accumulator, multiplexers, and a g( )_sbd calculator, and where the LBD datapath includes the shifter, the multiplexers, and a g?( )_lbd calculator.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 8, 2013
    Applicant: HUGHES NETWORKS SYSTEMS, LLC.
    Inventors: Marwan Adas, Shruti Dhingra, Shumin Zhang
  • Publication number: 20130198587
    Abstract: A memory system includes a semiconductor memory device, a memory controller for controlling the semiconductor memory device, and a memory buffer connected between the semiconductor memory device and the memory controller. The memory buffer is configured to perform error correction coding (ECC) on first data that is received from the memory controller to be stored in the semiconductor memory device and to perform ECC on second data read from the semiconductor memory device.
    Type: Application
    Filed: September 12, 2012
    Publication date: August 1, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JEONG-KYOUM KIM, JUNG HWAN CHOI, SEOK HUN HYUN, SEONG JIN JANG