Abstract: An error detection structure is proposed for a multilevel memory device including a plurality of memory cells each one being programmable at more than two levels ordered in a sequence, each level representing a logic value consisting of a plurality of digits, wherein the structure includes means for detecting errors in the values of a selected block of memory cells; the structure further includes means for partitioning the digits of each memory cell of the block into a first subset and a second subset, the digits of the first subset being unchanged in the values of a first and a second ending range in the sequence, the means for detecting errors only operating on the digits of the second subset of the block.

Abstract: A logical central processing unit (logical CPU) selects a target device. When the target device is shared by another logical CPU, the logical CPU determines whether the logical CPU is in charge of exclusively making diagnosis of the target device. When the target device is not shared by another logical central processing unit or when the logical CPU is exclusively in charge of making diagnosis of the target device, the logical CPU makes diagnosis of the target device and stores a result of diagnosis in a storage unit.

Abstract: A method of testing a SIP that has a CPU, a nonvolatile memory and a volatile memory. First, the CPU is used to test the memories. Then the CPU is tested separately. Preferably, the programs for testing the memories are pre-stored in and loaded from the nonvolatile memory into the volatile memory and are executed by the CPU in the volatile memory. Preferably, the test results are stored in the nonvolatile memory.

Abstract: A memory control apparatus includes a reading unit, an inserting unit, an identifying unit, a determining unit, and an outputting unit. The reading unit reads data from the memory. The inserting unit inserts a dummy error at an insertion position in the data thereby obtaining error data. The identifying unit identifies an error position at which an error has occurred in the error data. The determining unit determines whether the insertion position matches the error position. When the insertion position matches the error position, the outputting unit outputs corrected data obtained by correcting an error at the error position.

Abstract: A debug device include a programmable logic device (11) with debugging source codes burnt thereinto; a PCI connector (16) connected with the programmable logic device; a LPC connector (17) connected with the programmable logic device; a first display module (13) connected with the programmable device for showing codes of a port 80; a second display module (14) connected with the programmable device for showing codes of a selected port of 80h to 87h; and a button (15) connected with the programmable logic device for selecting the selected port of 80h to 87h. When the debugging device is used to debug a motherboard with PCI or LPC bus during a POST routine, the debugging device receives datum from the PCI or LPC bus and outputs corresponding datum to the first and second display modules, thereby showing codes of at least one port of 80h to 87h.

Abstract: A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.

Abstract: When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts.

Abstract: There is provided an error determination program executed by an information processor included in an electronic apparatus that includes a device installation section capable of installing any one of a plurality of devices having different formats, a host controller acting as an intermediary between the information processor and the device installed in the device installation section, and a storage circuit storing an error determination information table that includes a plurality of pieces of error determination information for determining a presence or absence of any error in a plurality of responses to a plurality of commands from the devices installable in the device installation section, by associating the pieces of error determination information with a combination of the formats of the installable devices and the commands executable by the devices.

Abstract: A method for operating a processor in data processing system comprises: asserting a debug control signal to cause the processor to enter a debug operating mode; initializing a plurality of shared processor resources with debug configuration information, wherein the plurality of shared processor resources are shared between a normal operating mode and the debug operating mode; executing instructions with the processor while in the debug operating mode; re-initializing the processor in response to a reset event; and preventing the reset event from re-initializing a predetermined portion of the debug configuration information in the plurality of shared processor resources. This allows processor debugging through reset events without losing the debug information.

Abstract: A semiconductor memory device comprising: a memory array having a data area and a check code area; refresh control means which controls a refresh operation in a data holding state; operation means which executes an encoding operation for generating the check code using a bit string in the data area, and executes a decoding operation for performing the error detection/correction of the data using the check code; encode control means for controlling an encode process in which in a change to the data holding state, a first and second code are written in the check code area; and decode control means for controlling a decode process in which at the end of the data holding state, first and second bit error correction based on each code are alternately performed, and the first and the second bit error correction are performed at least twice respectively.

Abstract: A system and method of recognizing resources of a computer comprising a system serial number and a broken hardware unit comprising a non-volatile memory unit and enablement definition data relating to functions of the broken hardware unit, wherein the method comprises starting the computer; entering a serial number in a read/write non-volatile memory field of the non-volatile memory unit; reading the read/write non-volatile memory field; and matching the serial number of the read/write non-volatile memory field with the system serial number. The method may further comprise detecting failure of the broken hardware unit after the starting of the computer. Preferably, a reading that the serial number of the read/write non-volatile memory field matches with the system serial number permits acceptance of the enablement definition data of the broken hardware unit.

Abstract: Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected value; a determination result selection section selecting, for each memory, terminal unit determination results from the terminal correspondence determination sections; a memory correspondence determination section determining whether writing succeeded to each memory, based on the selection result by the determination result selection section; an identifying section identifying a test signal supply section connected to the memory to which writing succeeded and a test signal supply section connected to the memory to which writing failed; and a mask treatment section instructing each test signal supply section whether to perform re-testing, according to whether writing s

Abstract: A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU). The auxiliary processor unit (APU) processes a trace instruction. When a trace instruction is identified by the APU, the APU signals the CPU with a pipeline stall signal for stalling the CPU and checks for an enabled trace engine as specified by the trace instruction. When the trace engine for the trace instruction is enabled, then the trace data is written into a trace buffer. The APU signals the CPU with an op done signal for allowing the CPU to continue with instruction processing.

Abstract: An embodiment of a method for providing technical support service includes generating a plurality of problem resolutions that are determined to resolve an identified technical problem; attributing weights to each of said plurality of problem resolutions according to frequency of use; and in response to a request to resolve said identified problem, selecting a problem resolution from among said plurality of problem resolutions based at least in part on said attributed weights.

Abstract: Methods and apparatus to track the health of integrated circuit structures are described. In an embodiment, a counter may be updated when the status of a portion of a storage unit (e.g., a cache) transitions to a defective status (e.g., as determined by reference to one or more corresponding status bits). The value stored in the counter may be compared with a threshold value, e.g., to generate a signal that is indicative of whether the threshold value has been exceeded. Other embodiments are also described.

Abstract: A method for facilitating basic input and output system (BIOS) testing is provided. In the method, a BIOS program code to be tested is loaded into a memory unit by a BIOS debugging card to execute a boot operation testing. The method of BIOS testing utilizes an uninterruptible power supply memory disposed on the motherboard. The uninterruptible power supply memory is powered with a battery, thus it can store the data of a command in executing during shutdown. By using this characteristic of the uninterruptible power supply memory, the tester can still obtain the debugging code last stored during the previous boot from the uninterruptible power supply memory when rebooting, thus preventing the debugging code generated in the BIOS debugging flow from disappearing due to the abnormal shutdown and resulting in the failure to get the source of the problem for the tester, increasing the efficiency of debugging.

Abstract: A radio frequency identifier (RFID) active/passive tag is provided to identify failed sub-CRU and location within a higher level CRU. When an error occurs on the base blade or within one of the sub-CRUs, the embedded processor writes failure information to the RFID. RFID tags may also contain data identifying the locations, of the sub-CRUs of the blade. Thus, when there is a failure, the RFID may report the failed component as well as the location of a failed sub-CRU. Sub-CRUs may also include an embedded processor and RFID tag. When a service action is initiated to repair or replace a blade, the RFID tag may be read by a RFID reader. The RFID reader device may then present failure information, including the identification of the failed sub-CRU and other associated information to the operator. The RFID reader device may also request associated information from a server computer.

Abstract: A system, method of automated testing and control of networked devices is provided. One or more test cases are defined in a test plan for execution against a plurality of networked devices. The test cases are created using a command defined grammar comprising verbs which characterize how commands or actions should be performed. Abstraction markers allow for device-specific characteristics to be mapped to a target device, without modification of the test cases and the test plan itself. The verbs and abstraction markers, once mapped to a target device form device-specific commands comprising actions and device-specific characteristics which are executed against the target networked device. The resulting responses are parsed against expected responses and a result or verdict is assigned. By providing command grammar and abstraction capability a common test plan and test cases can be applied across a range of diverse networked devices without require user intervention or modification.

Abstract: A test system employing a test controller compressing data, a data compressing circuit and a test method are provided. The test system includes a tester, a device under test (DUT), and a test controller receiving a first clock signal and serial data bits output from the DUT, compressing the serial data bits by m bits (m?4) in response to a second clock signal to generate a signature signal, and outputting the signature signal to the tester. The tester compares a computed signature signal to a 1-bit signature signal to determine whether the DUT is operating poorly or not.

Abstract: A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core for reference according to a first clock signal with a value captured in a taking-out scan chain to be tested through an operation of a processing core to be tested according to a second clock signal, a diagnosing unit which determines a timing failure in the logic circuit to be tested on the basis of a result of comparison by the comparator, and an adjuster which adjusts at least either a second cycle or a delay amount of the second clock signal. It is possible to examine a position of the timing failure or the number of the timing failures in the integrated circuit diagnosed as that its logic is normal but the timing failure occurs therein.

Abstract: An evaluation circuit and method for detecting faulty data words in a data stream is disclosed. In one embodiment the evaluation circuit according to the invention includes a first linear automaton circuit and also a second linear automaton circuit connected in parallel, each having a set of states z, which have a common input line for receiving a data stream Tn. The first linear automaton circuit and the second linear automaton circuit are designed such that a first signature and a second signature, respectively, can be calculated. Situated downstream of the two linear automaton circuits are respectively a first logic combination gate and a second logic combination gate, which compare the signature respectively calculated by the linear automaton circuit with a predeterminable good signature and output a comparison value.

Abstract: A self-testing message displaying system suitable for a computer is provided. The computer has multiple hardware devices, and the basic input/output system performs a power on self-test sequence on the computer and outputs a self-testing code when one of the hardware devices is error. The self-testing message displaying system includes a mother board and a display device. The mother board having a memory is disposed in the computer, and the memory stores the device codes corresponding to the hardware devices. The display including an on screen display control device is electrically connected to the mother board and used to store the on screen display symbols corresponding to the codes of the hardware devices. The on screen display control device is capable of accessing the device codes corresponding to the self-testing codes from the memory, such that the display device displays the on screen display symbols corresponding to the device codes.

Abstract: Outlier detection methods and apparatus have light computational resources requirement, especially on the storage requirement, and yet achieve a state-of-the-art predictive performance. The outlier detection problem is first reduced to that of a classification learning problem, and then selective sampling based on uncertainty of prediction is applied to further reduce the amount of data required for data analysis, resulting in enhanced predictive performance. The reduction to classification essentially consists in using the unlabeled normal data as positive examples, and randomly generated synthesized examples as negative examples. Application of selective sampling makes use of an underlying, arbitrary classification learning algorithm, the data labeled by the above procedure, and proceeds iteratively.