Power (voltage Islands) Patents (Class 716/127)
  • Patent number: 8205184
    Abstract: A method for laying out a power wiring of a semiconductor device including an analog circuit and a digital circuit includes: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a maximum current node from nodes of the digital circuit when a substrate noise violation exists in a voltage value of a node of the analog circuit, the maximum current node having a maximum amount of current flowing into the node of the analog circuit; searching a path of a current flowing into the maximum current node in the digital circuit; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Mikiko Sode
  • Patent number: 8185862
    Abstract: Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: May 22, 2012
    Assignee: Algotochip Corporation
    Inventors: Ananth Durbha, Pius Ng, Gary Oblock, Suresh Kadiyala, Satish Padmanabhan
  • Patent number: 8171446
    Abstract: A method for designing a semiconductor device includes computing a contact resistance value based on an allowable power supply voltage drop set for a second position corresponding to a given region of a second power supply line on a second wiring layer different from a first wiring layer, and computing a number of vias for the given region based on a result of a comparison between a resistance value of a via coupling a first power supply line and the second power supply line and the contact resistance value.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: May 1, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshio Inoue
  • Patent number: 8165852
    Abstract: A simulation apparatus of semiconductor device includes a first calculator, a second calculator, a third calculator, a fourth calculator, and a controller. The first calculator applies a voltage to an area which functions as a virtual electrode, and setting a pseudo-Fermi level of a first carrier in the area functioning as the virtual electrode to calculate a first carrier density. The second calculator analyzes continuous equation of a second carrier to calculate a second carrier density. The third calculator uses the first carrier density as a function of an electrostatic potential, and solving a first equation of the function and a Poisson's equation to calculate an electrostatic potential and the first carrier density expressed by the function. The fourth calculator calculates a current density of the first carrier to calculate a current flowing. The controller controls the voltage applied to the virtual electrode.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: April 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Enda
  • Patent number: 8161446
    Abstract: A system and method of connecting a macro cell to a system power supply network is disclosed. In a particular embodiment, the method includes determining a distance of an edge of the macro cell from a power line or a ground line of the system power supply network. The method further includes selectively adding at least one line to the system power supply network.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: April 17, 2012
    Assignee: QUALCOMM Incorporated
    Inventor: Li Qiu
  • Publication number: 20120084745
    Abstract: A method of designing integrated circuits includes providing a design of an integrated circuit at a first scale, wherein the integrated circuit includes a shrinkable circuit including a first intellectual property (IP); and a non-shrinkable circuit including a second IP having a hierarchical structure. A marker layer is formed to cover the non-shrinkable circuit, wherein the shrinkable circuit is not covered by the marker layer. The electrical performance of the non-shrinkable circuit is simulated using a simulation tool, wherein the simulated non-shrinkable circuit is at a second scale smaller than the first scale.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Yi Liu, Chung-Hsing Wang, Yung-Chin Hou, Lie-Szu Juang
  • Patent number: 8151238
    Abstract: In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is changed according to the current threshold value, design rule data base, and power supply wiring density so as not to exceed the current threshold value.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: April 3, 2012
    Assignee: Panasonic Corporation
    Inventors: Kouji Fujiyama, Takahiro Nagatani, Atsushi Takahashi
  • Patent number: 8146035
    Abstract: Approaches for estimating power consumption of a circuit from a circuit design. According to one embodiment, a representation of the circuit design specifies a plurality of circuit elements for implementing the circuit design. The circuit elements are matched to structural templates. Each structural template is representative of one or more circuit elements and has associated information descriptive of one or more toggle rates. Respective estimated toggle rates are determined for the circuit elements of the circuit design based on the information descriptive of one or more toggle rates associated with the matched structural templates. An estimated power consumption level is determined as a function of the estimated toggle rates of the circuit elements, and data indicative of the estimated power consumption level is output.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: March 27, 2012
    Assignee: Xilinx, Inc.
    Inventors: Paul R. Schumacher, Smitha Sundaresan, Alan Frost, Pradip K. Jha
  • Patent number: 8136074
    Abstract: To automatically arrange vias on a printed circuit board so as to satisfy a predetermined condition. A printed circuit board design support method for causing a computer to execute a ground conductive area identifying conductive areas which can be used as grounds of a printed circuit board having a plurality of conductive layers, an extracting an overlapping conductive area in which the conductive areas identified in the ground conductive area identifying are two-dimensionally overlapped with one another, and an automatic arranging interlayer connection members configured to electrically connect at least two layers with one another among the plurality of conductive areas in the overlapping conductive area extracted in the extracting at an interval within a predetermined distance.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: March 13, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Toshisato Sadamatsu
  • Patent number: 8132142
    Abstract: Various methods and apparatuses are described in which an integrated circuit is organized into rows and columns of macro cells having a layout architecture that includes at least two metal layers and a plurality of traces carrying three or more different potentials of voltage routed by the metal layers. A first, a second, and a third adjacent metal layers extend across the integrated circuit. The plurality of traces carry three or more different potentials of voltage and are routed in the metal layers. A first power trace supplies a VDD voltage potential. A second power trace supplies a VSS voltage potential. A third power trace supplies a third voltage potential to support sleep modes and retain data during sleep modes. All three power supply traces connect to one or more transistors in a first macro cell.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: March 6, 2012
    Assignee: Synopsys, Inc.
    Inventors: Deepak D. Sherlekar, Gene Sluss, Tushar Gheewala
  • Patent number: 8104011
    Abstract: A method of circuit design for an integrated circuit (IC) can include identifying a plurality of routing resources, wherein each of the plurality of routing resources is associated with a reliability measure, and selecting routing resources for use in routing a circuit design for the according to, at least in part, the reliability measures. The circuit design for the can be routed using the selected routing resources.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: January 24, 2012
    Assignee: Xilinx, Inc.
    Inventors: Prasanna Sundararajan, Carter Hamilton, Ian L. McEwen
  • Patent number: 8095905
    Abstract: Provided is a power supply wiring structure which comprises a first and a second power supply wirings, which are disposed on different planes to cross each other two-dimensionally. The first and second power supply wirings are interlayer-connected by a first via at a crossing area where those power supply wirings cross each other. An extension wiring which is formed by partially extending from the crossing area along a wiring extending direction of other power supply wiring is provided at least to either the first power supply wiring or the second power supply wiring. The extension wiring and either the first power supply wiring or the second power supply wiring, which are disposed on a different plane from the extension wiring to face the extension wiring, are interlayer-connected by a second via. Thereby, generation of electro migration can be suppressed.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: January 10, 2012
    Assignee: Panasonic Corporation
    Inventor: Atsushi Takahata
  • Patent number: 8086980
    Abstract: A improved method for very-early validation of voltage region physical power distribution networks uses initial floor plan and early power grid data to identify physical power connection problems associated with voltage regions defined in multi-supply voltage microprocessor chip designs. Since all checking algorithms are floor plan-based and do not require complete circuit data, they are executable very early in the design phase. As a result, power region-related problems can be resolved much sooner than by using conventional full-chip physical design checking and power grid analysis methods.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventor: Dieu Q. Phan Vogel
  • Patent number: 8082139
    Abstract: Methods and systems for simulating an electronic system in a high level modeling system (HLMS). A design block and certain signals of the electronic system are selected. The selected signals include internal signals of the design block that are not ports of the design block. The electronic system is simulated in the HLMS, which includes a hardware-based co-simulation platform and a software-based co-simulation platform. A hardware realization of the design block is automatically generated and the design block is emulated in the hardware based co-simulation platform using the hardware realization of the design block. A sequence of values is displayed for the selected signals of the electronic system. During the simulation of the electronic system in the HLMS, the sequence of values for the internal signals of the design block and another sequence of values for the ports of the design block are transferred between the co-simulation platforms.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: December 20, 2011
    Assignee: Xilinx, Inc.
    Inventors: Jonathan B. Ballagh, Michael D. Hirsch
  • Patent number: 8079007
    Abstract: A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: December 13, 2011
    Assignee: Active-Semi, Inc.
    Inventors: Steven Huynh, Matthew A. Grant, Gary M. Hurtz, David J. Kunst, Trey A. Roessig
  • Patent number: 8065652
    Abstract: Various embodiments of the invention comprise methods and systems for determining when or whether to use hard rules or preferred rules during global routing of an electronic design. In some embodiments, the entire routable space is first routed with hard rules during global routing while ensuring the design may be embedded. The design is then analyzed with preferred rules where the overcongested areas are marked as “use hard rule” and areas not overcongested are marked as “use preferred rule.” The methods or the systems thus ensure that the design remains routable throughout the process while improving timing, manufacturability, or yield by reserving routing space for the preferred rules.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: November 22, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey Scott Salowe, Charles T. Houck
  • Patent number: 8046728
    Abstract: A first library cell and a second library cell each includes a plurality of metal layers, and a metal track direction of the odd metal layers of the first library cell is perpendicular to that of the odd metal layers of the second library cell. An integrated circuit design method applied to these library cells includes the steps of rotating the second library cell to cause the metal track direction of the odd metal layers of the second library cell to be parallel to that of the odd metal layers of the first library cell, and placing the first library cell and the second library cell in an identical integrated circuit design.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: October 25, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chien-Cheng Liu
  • Patent number: 8037443
    Abstract: A system, method and computer program product are provided for optimizing an altered hardware design utilizing power reports. In use, a first hardware design is synthesized. Additionally, a first power report is generated for the synthesized first hardware design. Further, the first hardware design is altered. Further still, the altered hardware design is synthesized. Also, a second power report is generated for the synthesized altered hardware design. Furthermore, the altered hardware design is optimized utilizing the first power report and the second power report.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: October 11, 2011
    Assignee: Calypto Design Systems, Inc.
    Inventors: Venkatram Krishnaswamy, Vipul Gupta
  • Publication number: 20110246959
    Abstract: The present invention discloses a method, system, and design structure for making voltage environment consistent for reused sub modules in chip design, wherein each reused sub module is connected to a power grid of the chip through power connection points on a power ring of the sub module, the method including: adjusting numbers and locations of power connection points of a plurality of reused sub modules, such that the numbers of the power connection points and locations of the corresponding power connection points are identical for the plurality of reused sub modules; adjusting power wires of the plurality of reused sub modules on the power grid which are connected the power connection points, such that voltages at the corresponding power connection points are consistent for the plurality of reused sub modules. The present invention may reduce timing variation of reused sub modules in chip design and finally achieve an objective of reducing design complexity and work load and shortening the design period.
    Type: Application
    Filed: February 22, 2011
    Publication date: October 6, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xiao Feng Tang, Chen Xu, Jia Lian Tang, Xia Li
  • Publication number: 20110239180
    Abstract: An aspect of the present invention is a method for laying out a power wiring of a semiconductor device.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 29, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: MIKIKO SODE
  • Patent number: 8028259
    Abstract: Validation of full-chip power distribution networks can be performed very early, and continuously throughout the design cycle, to detect real physical power connection problems and enable early correction of power grid designs using early floor plan and power grid design data. Common power connection and distribution errors are automatically addressed as an integral part of the early chip floor planning and chip power build processes providing efficient solutions requiring no extra wiring resource to be implemented and reducing the runtime of required final full-chip physical design checks, and the overall design cycle.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: September 27, 2011
    Assignee: International Business Machines Corporation
    Inventor: Dieu Q. Phan Vogel
  • Patent number: 8015534
    Abstract: A method, apparatus, and recording medium including computer instructions for estimating the size of a core section of a semiconductor integrated circuit are provided. The method includes calculating a total net length of wires of nets and usable channel length of the core section by referring to circuit information and a layout parameter that are used to design the semiconductor integrated circuit. The method includes determining a size of the core section that satisfies conditions based on total net length and usable channel length.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takashi Kurihara, Kazutaka Takeuchi
  • Patent number: 8006218
    Abstract: The invention discloses a power mesh arrangement method utilized in an integrated circuit having multiple power domains. The arrangement method includes: forming a first partial local power mesh according to a position of a first power domain; forming a second partial local power mesh according to a position of a second power domain; forming a global power mesh, utilized for providing powers needed by the first and the second power domains; coupling the first partial local power mesh to the global power mesh and the first power domain; and coupling the second partial local power mesh to the global power mesh and the second power domain.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: August 23, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Lin Chuang
  • Patent number: 7996811
    Abstract: A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: August 9, 2011
    Assignee: MOSAID Technologies Incorporated
    Inventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
  • Patent number: 7986036
    Abstract: An arrangement scheme for a power/ground (P/G) network of an integrated circuit is provided. Rows of standard cells in the integrated circuit are horizontally arranged. The P/G network has horizontal and vertical metal lines arranged in different metal layers. The horizontal metal lines have horizontal power metal lines and horizontal ground lines. The vertical metal lines have vertical power metal lines and vertical ground lines. The power lines and the ground lines in the horizontal metal lines are respectively interconnected with the power lines and the ground lines of the vertical metal lines. The width of the horizontal metal wires in the P/G network is such that the horizontal power metal lines only cover the power lines in the rows of the standard cells, while the horizontal ground metal lines only cover the ground lines of the rows of the standard cells.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: July 26, 2011
    Assignee: VIA Technologies, Inc.
    Inventor: Xiaoshan Chen
  • Patent number: 7987441
    Abstract: A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: July 26, 2011
    Assignee: Apache Design Solutions, Inc.
    Inventors: Gerald L. Frenkil, Srinivasan Venkatraman
  • Patent number: 7984398
    Abstract: Systems and methods are disclosed herein which compensate for the loss in design information that occurs when the design is represented in traditional functional descriptions. An automated multiple voltage/power state design process includes creating a plurality of design objects; processing a design definition according to the voltage effects design object; and generating a modified design output such that communication between a plurality of design process steps, wherein the plurality of design process steps include a parsing step, a RTL simulation step, a synthesis step, a gate simulation step, formal verification step, and physical design and verification step in accordance with the voltage effects design object.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: July 19, 2011
    Assignee: Synopsys, Inc.
    Inventor: Srikanth Jadcherla
  • Patent number: 7979724
    Abstract: An integrated circuit (IC) chip containing a plurality of voltage islands containing corresponding functional blocks that can be selectively fenced, i.e., powered down, while saving the states of the corresponding inputs, and unfenced in order to manage power consumption of the chip. Each fencable functional block includes a power switch and state-saving circuitry for saving the state of the inputs to that functional block. A power modulation unit (PMU) generates fencing signals that control the power switches and state-saving circuitries so as to selectively fence the corresponding functional blocks. The PMU generates the fencing signals as a function of one or more operating arguments.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Henry R. Hottelet, Sebastian T. Ventrone
  • Patent number: 7975251
    Abstract: A design method includes creating power supply planes in each layer of a circuit board, from CAD data of the circuit boards whereby the power supply planes form one power supply conductor interconnect and supply power or connect to ground, expanding the shape of the power supply planes by a predetermined width, creating power supply pairs which are formed by opposing portions wherein two power supply planes existing in different layers are separated by an insulator and correcting the parameter by use of the mesh area.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: July 5, 2011
    Assignee: Fujitsu Limited
    Inventor: Shogo Fujimori
  • Patent number: 7975253
    Abstract: An object is to simplify a power supply noise analysis model of a circuit board. CAD data of the circuit board is obtained from a CAD apparatus, and overlapping power supply islands among power supply islands existing in different layers of the circuit board are extracted as a power supply pair. Nodes are arranged in the extracted power supply pair, and the nodes of the power supply pair are projected on the power supply islands to which the power supply pair belongs. A mesh region which encloses each node is determined for each power supply island, and impedance (L, R, C) between nodes is calculated. Then, a power supply noise analysis model is created based on the impedance between nodes in each layer, and a capacitance between layers.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 5, 2011
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Iwakura, Shogo Fujimori, Tendou Hirai, Hitoshi Chida, Kazuyoshi Kanei, Koutarou Nimura
  • Patent number: 7966589
    Abstract: The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventors: Pascal A. Nsame, Anthony J. Perri, Lansing D. Pickup, Sebastian T. Ventrone, Matthew R. Welland
  • Patent number: 7954078
    Abstract: A method to produce an information structure in computer readable memory that specifies power source hierarchy information for an RTL circuit design that includes multiple function instances encoded in computer readable memory, comprising: providing associations within the memory between respective function instances of the RTL design and respective power domains so as to define respective primary power domains relative to the RTL design; specifying in the memory respective secondary power domains; and providing associations within the memory that are indicative of respective power source relationships between respective primary power domains and corresponding respective secondary power domains.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: May 31, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Qi Wang, Pinhong Chen, Mitchell W. Hines
  • Patent number: 7945885
    Abstract: A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: May 17, 2011
    Assignee: MOSAID Technologies Incorporated
    Inventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
  • Patent number: 7945875
    Abstract: This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: May 17, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Alok Anand, Sajish Sajayan
  • Publication number: 20110113398
    Abstract: An integrated circuit (IC) design with multiple metal layers containing cells requiring secondary power supply. After placing the cells and stripes of a primary power/ground grid in metal layers of the IC design, specific cells are provided with secondary power stripes in a first metal layer. The secondary power stripes are designed in such a way that each secondary power/ground stripe exhibits a full overlap with a stripe of a corresponding primary power/ground grid in a different metal layer. Subsequently, signals from the IC design are routed, and power vias between the primary power/ground grid stripes and the secondary power/ground stripes are generated.
    Type: Application
    Filed: October 22, 2010
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joachim Keinert, Douglass T. Lamb, Peter J. Osler
  • Patent number: 7886261
    Abstract: A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode control circuit, and a low-power enable input coupled to the first low-power mode control circuit and the second low-power mode control circuit. This arrangement allows the programmable logic integrated circuit device to transition into and out of low-power mode in response to a single signal from system control logic, so that the system control logic can be designed without detailed understanding of the inner workings of the programmable logic integrated circuit device or its programmed design.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: February 8, 2011
    Assignee: Actel Corporation
    Inventors: Kenneth Irving, Vishal Aggrawal, Prasad Karuganti
  • Publication number: 20100270681
    Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.
    Type: Application
    Filed: July 12, 2010
    Publication date: October 28, 2010
    Inventors: Steven C. Bird, Linda M. Mazaheri, Bob Needham, Phuong Rosalynn Duong
  • Patent number: 7162624
    Abstract: A system for initializing hardware of a computer system includes a board support package (BSP) (20) and a ROM monitor (30). The BSP includes: a basic initialization module (21) for initializing a CPU, a Flash, etc.; an advanced initialization module (22) for initializing serial ports, an Ethernet, etc., for configuring parameters related to system operation and an interrupt service program; a function library (23) for storing various functions for performing configuration and modification of parameters of the hardware; and a boot loader (24) for determining whether parameters of the hardware need to be configured, and for booting an operating system or the ROM monitor based on the determination. The ROM monitor includes a command line editor (31) for inputting commands by users, a command translator (32) for translating the commands into computer-readable instructions, and a function invoking module (33) for invoking functions from the function library based on the instructions.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: January 9, 2007
    Assignees: Hong Fu Jin Precision Ind. (Shenzhen) Co., Ltd., Hon Hai Precision Ind. Co., Ltd.
    Inventors: Xin Zeng, Tang He