Abstract: A system, method, and computer program product for computing device mismatch variation contributions to circuit performance variation. Embodiments estimate which individual devices in a simulated circuit design have the largest impact on circuit performance, while requiring far fewer simulations than traditional multivariate linear regressions. When the samples exceed the mismatch parameters, a linear model is solved by least squares. Otherwise, a linear model is solved by orthogonal matching pursuit (OMP), and if that solution is too inaccurate then a new mixed method builds a better linear model. If the linear solution is too inaccurate, a full linear and quadratic model is made using OMP to select the most important variables, and the full model is fitted using OMP with selected cross terms. The embodiments summarize the output variance in each device, and rank the mismatch contributions based on the summarized contributions.

Abstract: The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons.

Abstract: A method of designing an optical photomask includes providing a target pattern, correcting the target pattern with an OPC model, adjusting the target pattern and/or the OPC model, and correcting a first corrected pattern. The target pattern indicates a target shape of a pre-pattern opening in a photoresist layer on a semiconductor substrate. Correcting the target pattern includes using an optical proximity correction (OPC) model to generate OPC output information that includes edge placement error (EPE) information, a first corrected pattern, and/or a simulated contour of the pre-pattern opening. Adjusting the target pattern and/or the OPC model includes adjusting with OPC based adjustments that are based on the OPC output information. Correcting the first corrected pattern includes using the OPC model in response to the OPC based adjustments to generate a second corrected pattern.

Abstract: Methods for modifying a layout design of an integrated circuit using model-based retargeting are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial integrated circuit layout design, correcting the initial layout design for etch-induced lithography errors to generate an etch-corrected layout design, and fragmenting the etch-corrected layout design to generate a fragmented layout design comprising a plurality of fragments. The method further includes performing a bridging condition simulation and a pinching condition simulation on the fragmented layout design and calculating a required movement for at least one fragment of the fragmented layout design based on the bridging condition simulation and the pinching condition simulation.

Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

Abstract: A mask includes a main pattern for resolving a target pattern to be formed on a substrate and an auxiliary pattern not resolving. Values of parameters of the main pattern and the auxiliary pattern are set. An image is calculated that is formed when the main pattern and the auxiliary pattern determined by the values of the parameters of the main pattern and the auxiliary pattern are projected by a projection optical system. Based on a result of the calculation that is performed by modifying the values of the parameters of the main pattern and the auxiliary pattern, the values of the parameters of the main pattern and the auxiliary pattern are determined to generate data of the mask including the main pattern and the auxiliary pattern determined.

Abstract: Computationally intensive electronic design automation operations are accelerated with algorithms utilizing one or more graphics processing units. The optical proximity correction (OPC) process calculates, improves, and optimizes one or more features on an exposure mask (used in semiconductor or other processing) so that a resulting structure realized on an integrated circuit or chip meets desired design and performance requirements. When a chip has billions of transistors or more, each with many fine structures, the computational requirements for OPC can be very large. This processing can be accelerated using one or more graphics processing units.

Abstract: A method of performing optical proximity correction for preparing a mask projected onto a wafer by photolithography includes the following steps. An integrated circuit layout design comprising a first feature and a second feature is obtained, wherein the first feature overlaps a first boundary of two structures in the wafer. An edge of the first feature close to the second feature pertaining to a specific trend section of an experimental chart having trend sections is recognized. An optical proximity correction value is evaluated for the edge through a computer system by a rule corresponding to the specific trend section. The layout design is compensated with the optical proximity correction value.

Abstract: A method for optical proximity correction (OPC) is disclosed, in which a set of VSB shots is determined, where the set of shots can approximately form a target reticle pattern that is an OPC-compensated version of an input pattern. The set of shots is simulated to create a simulated reticle pattern. A substrate image is calculated, based on using the simulated reticle pattern in an optical lithographic process to form the substrate image. A system for OPC is also disclosed.

Abstract: There is provided a method for generating a pattern. A pattern is generated by selecting a cell from a cell library including a plurality of cells, adding, to the interior of the selected cell, a second pattern different from a first pattern of the selected cell, performing a first optical proximity correction (OPC) onto the pattern of the selected cell including the first pattern and the second pattern, performing a second optical proximity correction onto a pattern of a plurality of cells in which the selected cell including first pattern and second pattern, which have been subjected to the first optical proximity correction, and another of the cells are proximately arranged and generating the pattern including the patterns of the plurality of cells which have been subjected to the second optical proximity correction.

Abstract: A layout correcting method and a layout correcting system are provided. The layout correcting method includes the following steps. An integrated circuit design layout is provided. A plurality of performance parameters of the integrated circuit design layout are analyzed. A plurality of devices under test is selected according to the performance parameters. A computer simulating process is performed on the devices under test and a direct probing process is performed on the devices under test. The direct probing process is an on-chip test for comparing each device under test and an environment condition thereof by a Boolean algebra algorithm. A plurality of differences between the results of the computer simulating process and the direct probing process is analyzed. The integrated circuit design layout is corrected according to differences between the results of the computer simulating process and the direct probing process.

Abstract: Aspects of the invention relate to techniques for mask rule checking based on curvature information. The curvature information comprises convex curvature information and concave curvature information. The convex curvature information for a vertex of a mask feature may comprise a convex curvature value derived based on the size of a circle that passes through the vertex, is tangent to an edge and does not cross any other edges. The concave curvature information for the vertex may comprise a concave curvature value derived based on the size of a circle that is tangent to two edges that form the vertex and does not cross any other edges, and of which distance from the vertex measured from the nearest point is no more than a predetermined number. The generated curvature information is compared with threshold curvature information to determine mask rule violations.

Abstract: A smooth process is provided in the present invention. The smooth process is applied to a retarget layout, wherein the retarget layout is dissected into a plurality of segments. Furthermore, the retarget layout comprises a first original pattern, a first adding pattern and a second adding pattern. The smooth process includes changing the second adding pattern to a first smooth pattern. Latter, a second smooth pattern is added to extend from a bottom of the first smooth pattern and a tail portion of the first adding pattern is shrunk to a third smooth pattern. After the smooth process, an optical proximity correction process is applied to the smooth layout to produce an optical proximity correction layout.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas.

Abstract: A mask data verification apparatus compares a design layout with design layout patterns stored in an existing-type library and extracts a design layout pattern found to be neither equal nor similar as a new-type design layout pattern. The mask data verification apparatus generates mask data using OPC/RET with reference to a new design layout pattern stored in a new-type library and performs post-verification. The mask data verification apparatus can previously verify a new design layout pattern, shorten a semiconductor device manufacturing period, ensure efficient development, and improve a manufacturing yield.

Abstract: A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.

Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a plurality of circular or nearly-circular shaped beam shots can form a non-circular pattern on a surface. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming non-circular patterns on a surface using a plurality of circular or nearly-circular shaped beam shots is also disclosed.

Abstract: Described herein is a method for simulating an image formed within a resist layer on a substrate resulting from an incident radiation, the substrate having a first feature and a second feature underlying the resist layer, the method comprising: simulating a first partial image using interaction of the incident radiation and the first feature without using interaction of the incident radiation and the second feature; simulating a second partial image using the interaction of the incident radiation and of the second feature without using the interaction of the incident radiation and the first feature; computing the image formed within the resist layer from the first partial image, and the second partial image; wherein the interaction of the incident radiation and the first feature is different from the interaction of the incident radiation and the second feature.

Abstract: Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of density by comparing a first density of a first set of the features with a second density of a second set of the features; determining a region on the layer of a first feature to be resolved by the first mask; and inserting, within the region, a polygon to be resolved by the second mask based on the difference of density.

Abstract: The present invention relates to methods and systems for designing gauge patterns that are extremely sensitive to parameter variation, and thus robust against random and repetitive measurement errors in calibration of a lithographic process utilized to image a target design having a plurality of features. The method may include identifying most sensitive line width/pitch combination with optimal assist feature placement which leads to most sensitive CD (or other lithography response parameter) changes against lithography process parameter variations, such as wavefront aberration parameter variation. The method may also include designing gauges which have more than one test patterns, such that a combined response of the gauge can be tailored to generate a certain response to wavefront-related or other lithographic process parameters. The sensitivity against parameter variation leads to robust performance against random measurement error and/or any other measurement error.

Abstract: According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a non-measurement region based on data in the measurement region and the virtual data are included.

Abstract: Aspects of the invention relate to techniques for detecting and correcting electrical hotspots in a layout design for a circuit design comprising an analog circuit. Layout parameters for device instances associated with electrical constraints are first extracted. Based on the extracted layout parameters, electrical parameter variations for the device instances may be computed to identify one or more electrical hotspots in the layout design. A sensitivity analysis of the one or more electrical hotspots is performed to generate repair hints. Based on the repair hints, the layout design is adjusted.

Abstract: A semiconductor inspection apparatus identifies regions of a reticle or semiconductor wafer appropriate for cell-to-cell inspection by analyzing a semiconductor design database. Appropriate regions can be identified in a region map for use by offline inspection tools.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns is disclosed, wherein the method comprises a splitting step being configured to be aware of requirements of a co-optimization between at least one of the sub-patterns and an optical setting of the lithography apparatus used for the lithographic process. Device characteristic optimization techniques, including intelligent pattern selection based on diffraction signature analysis, may be integrated into the multiple patterning process flow.

Abstract: A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout.

Abstract: Integrated circuit design techniques are disclosed. In some methods, a target layout design having a geometric pattern thereon is received. A set of fast-bias contour (FBC) rules is applied to the target layout design to provide an electronic photomask having FBC-edits. The FBC-edits differentiate the electronic photomask from the target layout design, and the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design. A lithography process check is performed on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design.

Abstract: Aspects of the invention relate to techniques of layout decomposition for triple patterning lithography. Data of a coloring graph are derived from layout data for a layout design. The coloring graph is simplified through graph reduction and graph partitioning processes. The graph partitioning process comprises separating biconnected components. The graph partitioning process may further comprise separating subgraphs connected by one or two edges. Based on the simplified coloring graph, the layout design is decomposed to generate decomposition information. The decomposition process may comprise applying a heuristic method for coloring if needed. The decomposition information may comprise information of one or more layout regions that cannot be decomposed.

Abstract: A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process is disclosed. The method includes defining an initial H-mask and an initial V-mask corresponding to the target pattern; identifying horizontal critical features in the H-mask and vertical critical features in the V-mask; assigning a first phase shift and a first percentage transmission to the horizontal critical features, which are to be formed in the H-mask; and assigning a second phase shift and a second percentage transmission to the vertical critical features, which are to be formed in the V-mask. The method further includes the step of assigning chrome to all non-critical features in the H-mask and the V-mask.

Abstract: Various embodiments include approaches for calibrating a model for a lithographic printing process. Some embodiments include a computer-implemented method for calibrating a model for a lithographic printing process. Some approaches include: identifying parameters for a model of the lithographic printing process; assembling a population of design content including potentially printable features that can be printed by the lithographic printing process; preparing at least one matrix expressing a similarity between the potentially printable features in terms of the parameters for the model; determining a manifold of smaller dimensionality than the parameters for the model which exhibit maximum variation in similarity within the at least one matrix; and selecting a sample dataset of the potentially printable features from the manifold.

Abstract: Aspects of the invention relate to techniques for applying edge fragment correlation information to optical proximity correction. Neighbor-aware edge adjustment values for the edge fragments are computed based on edge placement error values and edge fragment correlation information. The computation comprises: selecting a group of edge fragments around a center edge fragment, calculating preliminary neighbor-aware edge adjustment values based on the edge placement error values and the edge fragment correlation information for the group of edge fragments, storing the preliminary neighbor-aware edge fragment adjustment value for the center edge fragment, and repeating the selecting, the calculating and the storing with each of the edge fragments being the center edge fragment. The computed neighbor-aware edge adjustment values are combined with conventional edge adjustment values and the edge fragments are adjusted accordingly. The process may be repeated for a number of times.

Abstract: A method and system for fracturing or mask data preparation for charged particle beam lithography are disclosed in which a plurality of charged particle beam shots is determined that will form a pattern on a surface using a multi-beam charged particle beam writer, where the sensitivity of the pattern on the surface to manufacturing variation is reduced by increasing edge slope.

Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.

Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Abstract: A method for printing a periodic pattern having a first symmetry and a first period into a photosensitive layer. The method includes providing a mask bearing a pattern of at least two overlapping sub-patterns which have a second symmetry and a second period, the features of each sub-pattern being formed in a transmissive material, providing a substrate bearing the layer, arranging the mask with a separation from the substrate, providing light having a central wavelength for illuminating the mask to generate a light-field in which light of the central wavelength forms a range of intensity distributions between Talbot planes, illuminating said mask pattern with said light while maintaining the separation or changing it by a distance whereby the photosensitive layer is exposed to an average of the range of intensity distributions, wherein the light transmitted by each sub-pattern is shifted in phase relative to that transmitted by another sub-pattern.

Abstract: There is provided a method comprising: examining the location of one or more feature(s) of the one or more component(s) of a circuit arrangement to determine the displacement of the location of said one or more associated communication contact(s) with respect to a designed location for the communication contact(s), and providing corrective communication path layout data of said circuit arrangement based upon the said displacement(s).

Abstract: Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.

Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.

Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein base dosages for a plurality of exposure passes are different from each other. Methods for manufacturing a reticle and manufacturing an integrated circuit are also disclosed, wherein a plurality of charged particle beam exposure passes are used, with base dosage levels being different for different exposure passes.

Abstract: A method of layout pattern modification includes the following steps: step 1: performing an OPC process on a layout containing a plurality of square patterns to obtain a plurality of post-OPC patterns in correspondence with the plurality of square patterns; step 2: performing a manufacturing rule check on each of the plurality of post-OPC patterns to identify, from the plurality of post-OPC patterns, one or more post-OPC patterns violating the manufacturing rule; and step 3: rotating at least one of the one or more post-OPC patterns violating the manufacturing rule; and step 4: performing a manufacturing rule check on each of the rotated and non-rotated post-OPC patterns, if no post-OPC pattern violating the manufacturing rule is identified, finishing the process; otherwise, if one or more post-OPC patterns violating the manufacturing rule are identified, continuing to perform step 3 and step 4.

Abstract: One embodiment relates to a pattern data system for maskless electron beam lithography. The system includes a renderer that receives pre-exposure die image data, performs rendering of the pre-exposure die image data to generate raster data. The system further includes a plurality of data distributors communicatively coupled to the renderer. Each data distributor adapts the raster data to characteristics of an associated pattern writer. Other embodiments, aspects and feature are also disclosed.

Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage.

Abstract: The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time.

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields.

Abstract: A method of calculating process corrections for a lithographic tool, and associated apparatuses. The method comprises measuring process defect data on a substrate that has been previously exposed using the lithographic tool; fitting a process signature model to the measured process defect data, so as to obtain a model of the process signature for the lithographic tool; and using the process signature model to calculate the process corrections for the lithographic tool.

Abstract: A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.

Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a plurality of exposure passes are used, and where the sum of the base dosage levels for all of the exposure passes does not equal a normal dosage. Methods for manufacturing a reticle and manufacturing an integrated circuit are also disclosed, wherein a plurality of charged particle beam exposure passes are used, and where the sum of the base dosage levels for all of the exposure passes is different than a normal dosage.

Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.

Abstract: A charged particle beam writing apparatus includes a storage unit configured to store writing data in which there are defined a plurality of figures and resizing information indicating, with respect to each of the plurality of figures, a resizing status whether or not to perform resizing and a resizing direction used when performing resizing, a judgment determination unit configured to input the writing data and judge, with respect to each of the plurality of figures, the resizing status whether or not to perform resizing and the resizing direction used when performing resizing, a resize processing unit configured to resize, with respect to each of the plurality of figures, a dimension of a figure concerned in a judged resizing direction when it is judged to perform resizing, and a writing unit configured to write a pattern onto a target workpiece with using a resized figure and a charged particle beam.