Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns is disclosed, wherein the method comprises a splitting step being configured to be aware of requirements of a co-optimization between at least one of the sub-patterns and an optical setting of the lithography apparatus used for the lithographic process. Device characteristic optimization techniques, including intelligent pattern selection based on diffraction signature analysis, may be integrated into the multiple patterning process flow.

Abstract: A verification support apparatus for an integrated circuit.

Abstract: Integrated circuit design techniques are disclosed. In some methods, a target layout design having a geometric pattern thereon is received. A set of fast-bias contour (FBC) rules is applied to the target layout design to provide an electronic photomask having FBC-edits. The FBC-edits differentiate the electronic photomask from the target layout design, and the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design. A lithography process check is performed on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design.

Abstract: A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process is disclosed. The method includes defining an initial H-mask and an initial V-mask corresponding to the target pattern; identifying horizontal critical features in the H-mask and vertical critical features in the V-mask; assigning a first phase shift and a first percentage transmission to the horizontal critical features, which are to be formed in the H-mask; and assigning a second phase shift and a second percentage transmission to the vertical critical features, which are to be formed in the V-mask. The method further includes the step of assigning chrome to all non-critical features in the H-mask and the V-mask.

Abstract: Various embodiments include approaches for calibrating a model for a lithographic printing process. Some embodiments include a computer-implemented method for calibrating a model for a lithographic printing process. Some approaches include: identifying parameters for a model of the lithographic printing process; assembling a population of design content including potentially printable features that can be printed by the lithographic printing process; preparing at least one matrix expressing a similarity between the potentially printable features in terms of the parameters for the model; determining a manifold of smaller dimensionality than the parameters for the model which exhibit maximum variation in similarity within the at least one matrix; and selecting a sample dataset of the potentially printable features from the manifold.

Abstract: Aspects of the invention relate to techniques of layout decomposition for triple patterning lithography. Data of a coloring graph are derived from layout data for a layout design. The coloring graph is simplified through graph reduction and graph partitioning processes. The graph partitioning process comprises separating biconnected components. The graph partitioning process may further comprise separating subgraphs connected by one or two edges. Based on the simplified coloring graph, the layout design is decomposed to generate decomposition information. The decomposition process may comprise applying a heuristic method for coloring if needed. The decomposition information may comprise information of one or more layout regions that cannot be decomposed.

Abstract: A method for printing a periodic pattern having a first symmetry and a first period into a photosensitive layer. The method includes providing a mask bearing a pattern of at least two overlapping sub-patterns which have a second symmetry and a second period, the features of each sub-pattern being formed in a transmissive material, providing a substrate bearing the layer, arranging the mask with a separation from the substrate, providing light having a central wavelength for illuminating the mask to generate a light-field in which light of the central wavelength forms a range of intensity distributions between Talbot planes, illuminating said mask pattern with said light while maintaining the separation or changing it by a distance whereby the photosensitive layer is exposed to an average of the range of intensity distributions, wherein the light transmitted by each sub-pattern is shifted in phase relative to that transmitted by another sub-pattern.

Abstract: There is provided a method comprising: examining the location of one or more feature(s) of the one or more component(s) of a circuit arrangement to determine the displacement of the location of said one or more associated communication contact(s) with respect to a designed location for the communication contact(s), and providing corrective communication path layout data of said circuit arrangement based upon the said displacement(s).

Abstract: The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in order to assist the designers to anticipate the variations to improve the final yield of the products.

Abstract: Described herein is a method for a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic imaging apparatus, the lithographic process having a plurality of design variables, the method comprising: calculating a gradient of each of a plurality of evaluation points or patterns of the lithographic process, with respect to at least one of the design variables; and selecting a subset of evaluation points from the plurality of evaluation points or patterns based on the gradient.

Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.

Abstract: An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features.

Abstract: Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein, and preferably including optimizing a source, a mask, and the projection optics. The projection optics is sometimes broadly referred to as “lens”, and therefore the joint optimization process may be termed source mask lens optimization (SMLO). SMLO is desirable over existing source mask optimization process (SMO), partially because including the projection optics in the optimization can lead to a larger process window by introducing a plurality of adjustable characteristics of the projection optics. The projection optics can be used to shape wavefront in the lithographic projection apparatus, enabling aberration control of the overall imaging process.

Abstract: The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time.

Abstract: In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Abstract: A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields.

Abstract: A method of calculating process corrections for a lithographic tool, and associated apparatuses. The method comprises measuring process defect data on a substrate that has been previously exposed using the lithographic tool; fitting a process signature model to the measured process defect data, so as to obtain a model of the process signature for the lithographic tool; and using the process signature model to calculate the process corrections for the lithographic tool.

Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.

Abstract: An approach for providing a fragmentation scheme for lithographic fills is provided. In a typical embodiment, a plurality of shapes in a lithographic (e.g., dummy) fill will be grouped/classified into a first set of shapes (e.g., a representative set of shapes) and a second set of shapes (e.g., a similar set of shapes). A set of points will be identified along the edges of the first set of shapes (e.g., at corners of the edges and at positions along the edges that are in alignment with corners of adjacent shapes) to yield an initial mask output. This initial mask output will be copied to the second set of shapes to yield a final mask output which may then be outputted using such an optimized fragmentation scheme.

Abstract: A photolithography mask design is simplified. In one example, a target mask design is optimized for a photolithography mask. Medial axes of the design and assist features on the optimized mask are identified. These are simplified to lines. Lines that are distant from a respective design feature are pruned. The remaining lines are simplified and then thickened to form assist features.

Abstract: A method of SRAF printing using etch-aware SRAF print avoidance engines and the resulting device are provided. Embodiments include performing mask to resist simulations for a mask having both a plurality of features to be formed on a substrate and a plurality of sub resolution assist features (SRAFs); detecting SRAFs of the plurality that will print through to a resist; checking dimensions of the detected SRAFs to determine whether one or more of the SRAFs will etch through to the substrate; modifying the one or more of the SRAFs; and forming the mask after the one or more of the SRAFs have been modified.

Abstract: Computer-implemented techniques for pixel source optics calculations using spatial coherence are disclosed. Pixelated sources are used for source-mask co-optimization to enhance semiconductor lithography. Calculation of a partially coherent imaging system is used for optical-lithography simulation. The spatial coherence property of neighboring source points is used to reduce imaging calculation complexity. Two or more neighboring points are treated as one pseudo-spatially coherent area element.

Abstract: The present disclosure relates to a method of forming a reusable cut mask or trim mask that can be used for multiple design levels, and an associated apparatus. In some embodiments, the method is performed by determining positions of a plurality of mask cuts for a reusable cut mask or a reusable trim mask. Shapes are then routed along a routing path having a plurality of design levels. The routing path intersects one or more of the plurality of mask cuts at positions that form distinct shapes that connect nodes of an integrated chip sharing a same electric network. By routing shapes on a plurality of design levels to intersect one or more of the plurality of mask cuts, the cut masks can be reused between the plurality of levels, therefore decreasing mask costs during fabrication.

Abstract: Approaches for generating test cases for design rule checking are provided. A method includes extracting coordinates of an error marker in an integrated circuit design. The method also includes creating an error polygon using the coordinates. The method additionally includes selecting polygons in the design that touch the error polygon. The method further includes identifying a rectangle that encloses the selected polygons. The method also includes generating a test case based on data of the design contained within the rectangle. The extracting, the creating, the selecting, the identifying, and the generating are performed using a computer device.

Abstract: A method for forming a mask layout is described. A plurality of phase shapes are formed on either side of a critical feature of a design layout of an intergrated circuit chip having a plurality of critical features. A plurality of transition edges are identified from the edges of each phase shape. Each transition edge is parallel to critical feature. A transition space is identified as defined by one of the group including two transition edges and one transition edge. A transition polygon is formed by closing each transition space with at least one closing edge. Each transition polygon is transformed into a printing assist feature. A mask layout is formed from the printing assist features and critical features.

Abstract: A method of forming a pattern includes forming a plurality of target patterns, forming a plurality of pitch violating patterns that make contact with the plurality of target patterns and are disposed between the plurality of target patterns, classifying the plurality of pitch violating patterns into a first region and a second region adjacent to the first region, and forming an initial pattern corresponding to one of the first region and the second region.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (IC) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one IC chip; obtaining user input data about the at least one IC chip; and running an IC library defining program using the chip design data in its original format and the user input data in its original format, the running of the IC library defining program including: determining a process variation for the at least one IC chip based upon the chip design data and the user input data; converting the process variation into shape variation data; and providing the shape variation data in a text format to a scatterometry modeling program for use in the scatterometry analysis.

Abstract: Data associated with a substrate can be processed by measuring a property of at least a first type of specific features and a second type of specific features on a substrate. The first type of specific features is measured at a first plurality of locations on the substrate to generate a first group of measured values, and the second type of specific features is measured at a second plurality of locations on the substrate to generate a second group of measured values, in which the first and second groups of measured values are influenced by critical dimension variations of the substrate. A combined measurement function is defined based on combining the at least first and second groups of measured values. At least one group of measured values is transformed prior to combining with another group or other groups of measured values, in which the transformation is defined by a group of coefficients.

Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

Abstract: A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a multilayer electronic structure and a method of manufacture is presented.

Abstract: The present invention relates to a photolithography capacity planning system and a non-transitory computer readable media thereof. The photolithography capacity planning system includes a cost calculation module, a capacity calculation module, a demand calculation module, and a data processing module. The cost calculation module calculates a production cost, an unfulfilled demand cost, and a mask cost of the photolithography manufacturing process. The capacity calculation module calculates a capacity of light sources, a capacity of shared equipments, and a capacity of specified equipments of the photolithography manufacturing process. The demand calculation module calculates a quantity of unfulfilled demand. The data processing module produces a planning result.

Abstract: An inspection data generator generates inspection data used to inspect a pattern transferred onto the same material layer using exposure processes. An input part of the generator receives first layout data for a mask used in a first exposure process and second layout data for a mask used in a second exposure process, and receives a measured value of a misalignment between a first transfer pattern actually transferred onto the material layer in the first exposure process and a second transfer pattern actually transferred onto the material layer in the second exposure process. A processor unit generates the inspection data by shifting the first layout data and the second layout data from each other by an amount corresponding to the measured value and then combining the first layout data with the second layout data. An output part outputs the inspection data to inspect the pattern transferred onto the material layer.

Abstract: A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.

Abstract: The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.

Abstract: A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.

Abstract: A process and apparatus are provided for generating and evaluating one or more metrics for analyzing the design and manufacture of semiconductor devices. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.

Abstract: A method for optimizing masks used for forming conductive features and a method for creating the mask features on an IC device are disclosed. An exemplary embodiment includes receiving a design database including a plurality of conductive features. First and second features suitable for joining are identified from the plurality of conductive features. A joined feature corresponding to the first and the second features is characterized. A cut shape configured to separate the first and second features from the joined feature is also characterized. The joined feature is categorized into a first conductive mask, the cut shape is categorized into a cut mask, and a third feature is categorized into a second conductive mask. The categorized shapes and features of the first conductive mask, the second conductive mask, and the cut mask are provided for manufacturing a mask set corresponding to the categorized shapes and features.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a first plurality of features defined in a first layer and a second plurality of features defined in a second layer; converting the IC design layout to a topological diagram having nodes, chains and arrows; and identifying alignment conflict based on the topological diagram using rules associated with loop and path count.

Abstract: Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell.

Abstract: A method for making a mask for an integrated circuit (IC) design includes receiving an IC design layout having a plurality IC features and performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout. The method also includes inserting a phase-bar (PB) to the TFSL, performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout and providing the modified IC design layout for fabrication of the mask.

Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.

Abstract: A method includes establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer. At least one of a row of shots or a column of shots is shifted relative to an adjacent row or column of shots to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout. One of the initial shot layout and the at least one additional shot layout is selected as a final shot layout. The wafer is exposed to light using the final shot layout.

Abstract: A method for pattern modification for making an integrated circuit layout is disclosed. The method includes determining a feature within a pattern of the integrated circuit layout that can be rearranged; determining a range in which the feature can be repositioned; for the feature, determining a preferred position function that exhibits extreme values at preferable positions; and rearranging the position of the feature within the range to match an extreme value of the function.

Abstract: Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of density by comparing a first density of a first set of the features with a second density of a second set of the features; determining a region on the layer of a first feature to be resolved by the first mask; and inserting, within the region, a polygon to be resolved by the second mask based on the difference of density.

Abstract: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing illumination source and projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).

Abstract: In an imaging recipe creating apparatus that uses a scanning electron microscope to create an imaging recipe for SEM observation of a semiconductor pattern, in order that the imaging recipe for measuring the wiring width and other various dimension values of the pattern from an observation image and thus evaluating the shape of the pattern is automatically generated within a minimum time by the analysis using the CAD image obtained by conversion from CAD data, an CAD image creation unit that creates the CAD image by converting the CAD data into an image format includes an image-quantizing width determining section, a brightness information providing section, and a pattern shape deformation processing section; the imaging recipe being created using the CAD image created by the CAD image creation unit.