Abstract: A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi-material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide range of etch behavior and geometry to provide in a virtual fabrication system a semi-physical approach to modeling multi-material etches based on a small set of input parameters that characterize the etch behavior.

Abstract: A pattern designing method, including the steps of carrying out transfer simulation calculation and step simulation calculation by using physical layout data produced from circuit design data, and comparing a result of the transfer simulation calculation and the step simulation calculation with a preset standard; and carrying out calculation for electrical characteristics by using parameters obtained from the physical layout when as a result of the comparison, the preset standard is fulfilled, and carrying out calculation for the electrical characteristics by reflecting the result of the transfer simulation calculation and the step simulation calculation in the parameters when as the result of the comparison, the preset standard is not fulfilled, thereby extracting the parameters.

Abstract: A computer determines a component optimal yield point for each component of the plurality of components, where the component optimal yield point represents the process parameter values where maximum yield is achieved for a component. The computer determines a weight factor for each component of the plurality of components, where the weight factor represents an importance of a component to the semiconductor device. The computer then determines an overall optimal yield point based on the component yield point and weight factor determined for each component of the plurality of components, the overall optimal yield point representing the process parameter values where maximum yield is achieved for the semiconductor device.

Abstract: Systems and methods for process aware metrology are provided. One method includes selecting nominal values and one or more different values of process parameters for one or more process steps used to form the structure on the wafer, simulating one or more characteristics of the structure that would be formed on the wafer using the nominal values, and determining parameterization of the optical model based on how the one or more characteristics of the structure vary between at least two of the nominal values and the one or more different values.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process.

Abstract: A position control system to control the position of a movable object, including a position measurement system configured to determine an actual position related quantity of the movable object; a set-point generator to provide a position related set-point signal of the movable object; a comparator to provide an error signal on the basis of a comparison of the actual position related quantity and the position related set-point signal, a controller to provide a control signal on the basis of the error signal, a feed-forward device to provide a feed-forward signal on the basis of the position related set-point signal, and one or more actuators to act on the movable object on the basis of the control signal and the feed-forward signal, wherein the feed-forward device includes a disturbance force correction table including estimations of disturbance forces exerted on the movable object in dependence of a position of the movable object.

Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns is disclosed, wherein the method comprises a splitting step being configured to be aware of requirements of a co-optimization between at least one of the sub-patterns and an optical setting of the lithography apparatus used for the lithographic process. Device characteristic optimization techniques, including intelligent pattern selection based on diffraction signature analysis, may be integrated into the multiple patterning process flow.

Abstract: Embodiments relate to polygon recovery from a +1/?1 description of a plurality of polygons of a very large scale integrated (VLSI) mask for production of a VLSI semiconductor device. An aspect includes receiving a set of data comprising the +1/?1 description of the plurality of polygons of the VLSI mask, the +1/?1 description comprising a plurality of corners. Another aspect includes determining a 4-directional data structure, a Mm value comprising a first limit value, and a Mp value comprising a second limit value for each of the plurality of corners. Another aspect includes recovering the plurality of polygons from the set of data by assigning each of the plurality of corners to a single polygon based on the 4-directional data structure, the Mm value, and the Mp value of each of the plurality of corners, and determining an order of the respective corners of each polygon.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.

Abstract: An integrated circuit is formed using an lithographic process including a stage of forming a lithographic layer from a plurality of separately printed pattern layers. Within the integrated circuit there is formed a circuit including at least two devices that are matched devices such that the performance of the circuit is degraded if the match devices deviate from having matched performance characteristics. Dummy contacts 32 (structural features) are provided within the circuit design so as to force allocation of functional contacts (structural features) of the matched devices into the same pattern layer thereby reducing inter-device variation in contact position and/or size.

Abstract: A method comprises: (a) transforming a layout of a layer of an integrated circuit (IC) or micro electro-mechanical system (MEMS) to a curvilinear mask layout; (b) replacing at least one pattern of the curvilinear mask layout with a previously stored fracturing template having approximately the same shape as the pattern, to form a fractured IC or MEMS layout; and (c) storing, in a non-transitory storage medium, an e-beam generation file including a representation of the fractured IC or MEMS layout, to be used for fabricating a photomask.

Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.

Abstract: Methodology enabling a reduction of edge and strap cell size, and the resulting device are disclosed. Embodiments include: providing first and second NW regions on a substrate; providing first and second RX regions on the first and second NW regions, respectively; providing a contact on the substrate connecting the first and second RX regions; and providing a dummy PC on the substrate connecting the first and second RX regions. Other embodiments include: determining an RX region of an IC design; determining a PPLUS mask region extending along a horizontal direction and being on an entire upper surface of the RX region; determining a NW region extending along a vertical direction and separated from the RX region; and comparing an area of an overlap of the NW region and PPLUS mask region to a threshold value.

Abstract: In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (?f). In some embodiments, the sensitivity to changes in ?f is reduced by varying the charged particle surface dosage for a portion of the pattern. Methods for forming patterns on a surface, and for manufacturing an integrated circuit are also disclosed, in which pattern sensitivity to changes in ?f is reduced.

Abstract: A method of computational lithography includes collecting a critical dimension (CD) data set including CD data from printing a test structure including a set of gratings which provide a plurality of feature types including different ratios of line width to space width, where the printing includes a range of different focus values. The CD data is weighted to form a weighted CD data set using a weighting algorithm (WA) that assigns cost weights to the CD data based its feature type and its magnitude of CD variation with respect to a CD value for its feature type at a nominal focus (nominal CD). The WA algorithm reduces a value of the cost weight as the magnitude of variation increases. At least one imaging parameter is extracted from the weighted CD data set. A computational lithography model is automatically calibrated using the imaging parameter(s).

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.

Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.

Abstract: A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.

Abstract: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).

Abstract: A design layout includes a conductive line level, at least one underlying conductive line level, and a via design level for vertically interconnecting structures in the conductive line level and the at least one underlying conductive line level. Stitch shapes are identified in the conductive line level. Test shapes are generated to determine whether vias formed in the area of the stitch shapes can extend to the at least one underlying conductive line level without contacting preexisting design shapes in the at least one underlying conductive line level structure and whether a new design shape can be inserted into the at least one underlying conductive line level with electrical isolation. As many new design shapes are inserted as possible to prevent extension of collateral via structures below the top surface of underlying metal line structures in a physical metal interconnect structure implementing the design layout.

Abstract: A method of optical proximity correction (OPC) includes the following steps. At first, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into at least a first region and at least a second region. Then, several iterations of OPC calculations are performed to the layout pattern, and a total number of OPC calculations performed in the first region is substantially larger than a total number of OPC calculations performed in the second region. Afterwards, a corrected layout pattern is outputted through the computer system onto a mask.

Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.

Abstract: An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edge segments are in conflict so that a user may remove the conflict to achieve a better OPC result. In another embodiment of the invention, edge segments are assigned a priority such that the correction of a lower priority edge does not hinder a desired OPC correction of a higher priority edge.

Abstract: Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.

Abstract: Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).

Abstract: A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.

Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. The initial design layout comprises a first pattern, such as a mandrel pattern, and a second pattern, such as a passive fill pattern. An initial cut pattern is generated for the initial design layout. Responsive to identifying a design rule violation associated with the initial cut pattern, the initial design layout is modified to generate a modified initial design layout. An updated cut pattern, not resulting in the design rule violation, is generated based upon the modified initial design layout. The updated cut pattern is applied to the modified initial design layout to generate a final design layout. The final design layout can be verified as self-aligned multiple patterning (SAMP) compliant.

Abstract: A method for assembling an electrical circuit includes measuring actual values of components of a given type that are held in a stock, and storing the measured actual values in a computerized stock-record. An actual property of an electrical circuit under assembly is determined. Based on the determined actual property, and on a specified response of the circuit, a required value is calculated for a set of one or more of the components of the given type. Responsively to the calculated required value, the stock-record is searched, and a set of one or more of the components is selected from the stock and assembled into the circuit.

Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.

Abstract: In a method and apparatus for quantitatively evaluating two-dimensional patterns, a reference coordinate system is set in order to convert pattern edge information (one-dimensional data) acquired by measurement using an existing critical dimension machine into coordinate data. Thus, a pattern is converted into coordinate information. Next, a function formula is determined from this coordinate information by approximate calculation and a pattern is represented by the mathematical expression y=f(x). Integrating y=f(x) in the reference coordinate used when calculating the coordinate data gives the area of the pattern, whereby it is possible to convert the coordinate data to two-dimensional data.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.

Abstract: An inspection method for a photo-mask in a semiconductor process is provided. First, a first photo-mask with a first wafer anchor point (1st wafer FAM) is provided. Then, Dmax and Dmin are calculated according to the 1st wafer FAM. A second photo-mask and a second mask anchor point (2nd mask FAM) of the second photo-mask are provided. A CD average, and a CD range of the second photo-mask are measured. Finally, the second photo-mask is inspected by using equation A and/or equation B: CD average?2nd mask FAM<Dmax?CD range/2??(equation A) 2nd mask FAM?CD average<Dmin?CD range/2??(equation B).

Abstract: A method of optical proximity correction (OPC) includes the following steps. First, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into a first sub-layout pattern and a second sub-layout pattern. Then, an OPC calculation based on a first OPC model is performed on the first sub-layout pattern so as to form a corrected first sub-layout pattern and an OPC calculation based on a second OPC model is performed on the second sub-layout pattern so as to form a corrected second sub-layout pattern. Afterward, the corrected first sub-layout pattern and the corrected second sub-layout pattern are output from the computer system into a photomask.

Abstract: Disclosed are a method, apparatus, and program product for routing an electronic design using double patterning that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patterning, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.

Abstract: A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a set of diffraction-orders, the IC layout including a set of features defined by a set of target edges, analyzing the diffraction pattern with a merit function to estimate printability of the IC layout, monitoring a change in value of the merit function as a position of at least one of the set of target edges is adjusted across a range, and retargeting the set of target edges based on the monitoring of the merit function.

Abstract: Some embodiments of the invention provide a method for identifying and displaying odd loops and hints for resolution of the odd loops in an IC design layout for printing on multiple masks. The method of some embodiments identifies the hints by evaluating the effectiveness and feasibility of different potential resolutions, ensuring that hints do not create additional odd loops. The method of some embodiments also displays indications of the odd loops and the hints which a user can use to troubleshoot an odd loop violation. The method of some embodiments also prioritizes or scores the resolution hints to facilitate efficient troubleshooting of odd loop violations.

Abstract: A system for preparing mask data to create a desired layout pattern on a wafer with a multiple exposure photolithographic printing system. In one embodiment, boundaries of features are expanded to create shields for those features, or portions thereof, that are not oriented in a direction that are printed with greater fidelity by an illumination pattern used in the multiple exposure printing system.

Abstract: Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.

Abstract: A method includes receiving a layout file for a reticle used to pattern a first die location in a computing apparatus, the layout file defining a plurality of kerf features. A flare map calculation area for the first die location covering at least a portion of a kerf region surrounding the first die location is defined in the computing apparatus. Features in the layout file into the region corresponding to the flare map calculation area that are associated with the patterning of die locations neighboring the first die location are copied in the computing apparatus to generate a modified layout file. A flare map of the portion of the kerf region included in the flare map calculation area based on the modified layout file is calculated in the computing apparatus.

Abstract: The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.

Abstract: A method for producing an electrical circuit includes providing a substrate having a first pattern of features and defining a second pattern comprising a net of interconnected circuit elements. Different respective transformation rules are specified for different ones of the circuit elements. The second pattern is modified by applying the respective transformation rules to the circuit elements so as to align the circuit elements with the features in the first pattern, and the modified second pattern is applied to the substrate.

Abstract: A method and system arrangement for controlling and determining mask operation activities. Upon obtaining chip physical layout design data and running resolution enhancement technology on the chip physical layout design to generate mask features which may include any sub-resolution assist features, a placement sensitivity metric is determined for each of the generated mask features or edge fragments. In one alternative embodiment an edge placement sensitivity metric is determined for each edge of the generated mask features or edge fragments. The determined sensitivity metrics for each feature are classified and applied to subsequent mask operational activities such as post processing, write exposure and mask repair.

Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.

Abstract: A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask.

Abstract: A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.