Abstract: In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.

Abstract: Emulation of a target system with a host system is disclosed. Two or more target system code instructions may be grouped into one or more fragments. A main translation function may be implemented by translating each fragment into a corresponding set of position-independent instructions executable by the host system. A target processor may be emulated by executing the corresponding set of position-independent executable instructions with the host system.

Abstract: In one embodiment, an apparatus for directory-based web service distribution is disclosed. The apparatus includes a directory and a request client to initiate a request for a web service, the request client including an application middleware having invocation framework with embedded distribution logic to distribute the request to a destination pod, the destination pod to compute a subset of a state associated with the web service, wherein the distribution logic to distribute the request based on a lookup value extracted from the request and submitted to the directory to determine the destination pod. Other embodiments are also disclosed.

Abstract: A method and system for emulating a byte-wise programmable memory in a sector-wise erasable memory, where emulating a byte-wise programmable memory in a sector-wise erasable memory is based on dividing the sector-wise erasable memory in a plurality of sectors, dividing each of the sectors into several memory locations suitable to store containers, with each container having a header and a payload portion, and storing a data value relating to an application in the payload portion of one of the containers and header information identifying the application in the header in an available container. The containers can be block containers, and the data portion can have two or more payload values. The storing action can be performed in such a way that the two or more payload values in the payload portion together uniquely represent the data value.

Abstract: A system and method for managing data, such as in a data warehousing, analysis, or similar applications, where dataflow graphs are expressed as reusable map components, at least some of which are selected from a library of components, and map components are assembled to create an integrated dataflow application. Composite map components encapsulate a dataflow pattern using other maps as subcomponents. Ports are used as link points to assemble map components and are hierarchical and composite allowing ports to contain other ports. The dataflow application may be executed in a parallel processing environment by recognizing the linked data processes within the map components and assigning threads to the linked data processes.

Abstract: A system and methods are disclosed for providing integrated software development environment for the design, verification and validation of advanced automotive safety systems. The system allows automotive software to be developed on a host computer using a collection of computer programs running simultaneously as processes and synchronized by a central process. The software disclosed uses separate synchronized processes, permitting signals from disparate sources to be generated by a simulation running on the host computer or from actual sensors and data bus signals coming from and going to actual vehicle hardware which is connected to their bus counterparts in the host computer on a real-time basis. The methods disclosed are for providing an Algorithm Prototyping, Analysis and Test through an integrated framework for dynamic data modeling and application development.

Abstract: A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.

Abstract: A technique for transferring binary instructions from a computer system to an external platform is described herein. The process extracts binary instructions from the computer system. The instructions include a function at a register location. The process disassembles the binary instructions to produce an intermediate representation of the function. An interruption is inserted at the register location linked to a routine call. The process analyzes the intermediate representation for data dependency to identify internal data references for the routine call and external data references to produce a data dependence representation. The process reconfigures the data dependence representation to produce a reconfigured representation, whose control flow logic produces a logic hierarchy representation for the function.

Abstract: In some embodiments, antivirus/malware behavior-based scanning (emulation) is accelerated by identifying known code sequences and executing pre-stored native-code routines (e.g. decompression, decryption, checksum routines) implementing the functionality of the known code sequences before returning to the emulation. During emulation, target machine code instructions are compared to a set of known signatures. If a known code sequence is identified, the emulator calls a native code routine and caches the current instruction address. If the emulator subsequently reaches a cached address, a native code routine may be called without scanning the data at the address for known signatures. Signature scanning may be performed selectively for instructions following code flow changes (e.g. after jump, call or interrupt instructions).

Abstract: An apparatus and a method for Java array interception using bytecode manipulation and data flow analysis. In one embodiment, a user-provided object class is identified. An array access operation of the user-provided object class is intercepted. The intercepted array access operation is translated with an emulator class of a native Java array. The translated array access operation is sent to an emulator class to determine whether to dispatch to the native Java array or an alternate data source.

Abstract: In cooperation between each data center and a WAN, virtual machine migration is carried out without interruption in processing so as to enable effective power-saving implementation, load distribution, or fault countermeasure processing. Each node located at a boundary point between the WAN and another network is provided with a network address translation (NAT) function that can be set dynamically to avoid address duplication due to virtual machine migration. Alternatively, each node included in the WAN is provided with a network virtualization function; and there are implemented a virtual network connected to a data center for including a virtual machine before migration, and a virtual network connected to a data center for including the virtual machine after migration, thereby allowing coexistent provision of identical addresses. Thus, the need for changing network routing information at the time of virtual machine migration can be eliminated, and a setting change for migration accomplished quickly.

Abstract: A technique for reliably replaying operations in electronic-design-automation (EDA) software is described. In this technique, the EDA software stores operations performed by a user during a design session, as well as any replay look-ahead instructions, in a log file. When repeating the first operation, the replay look-ahead instruction ensures that the same state is obtained in the EDA environment as was previously obtained. For example, if an interrupt occurred when the first operation was previously performed, the replay look-ahead instruction may specify when the interrupt occurred during the performance of the operation so that the effect of the interrupt may be simulated when replaying the first operation.

Abstract: Methods and systems for register mapping in emulation of a target system on a host system are disclosed. Statistics for use of a set of registers of a target system processor are determined. Based on the statistics a first subset of the target system registers, including one or more most commonly used registers is determined. The registers in the first subset are directly mapped to a first group of registers of a host system processor. A second subset of the set of target system registers is dynamically mapped to a second group of registers of the host system processor.

Abstract: The computer system of the present invention emulates target instructions. The computer system includes a processing unit for branching to collective emulation coding for emulating plural of target instructions created beforehand collectively, thereby processing those instructions collectively according to the coding when those target instructions are combined so as to be processed collectively and a memory for storing the collective emulation coding.

Abstract: A method and system for detecting and removing a hidden pestware file is described. One illustrative embodiment detects, using direct drive access, a file on a computer storage device; determines whether the file is also detectable by the operating system by attempting to access the file using a standard file Application-Program-Interface (API) function call of the operating system; identifies the file as a potential hidden pestware file, when the file is undetectable by the operating system; confirms through an automated pestware-signature scan of the potential hidden pestware file that the potential hidden pestware file is a hidden pestware file; and removes automatically, using direct drive access, the hidden pestware file from the storage device.

Abstract: Native code corresponding to an invalidated trace is re-used in a system emulator. A first trace is identified. A dropped second trace is identified. The dropped second trace is associated with a first native code for emulating the second trace. If the identified first trace corresponds to the dropped second trace, the first native code is associated to the first trace, and the first native code is executed. If the identified first trace does not correspond to the dropped second trace, a second native code for emulating the first trace is created, the second native code is associated with the first trace, and the second native code is executed.

Abstract: A system and method for infeasible path detection includes performing a static analysis on a program to prove a property of the program. If the property is not proved, infeasible paths in the program are determined by performing a path-insensitive abstract interpretation. Information about such infeasible paths is used to achieve the effects of path-sensitivity in path-insensitive program analysis.

Abstract: Embodiments of a producer graph oriented programming framework with scenario support have been presented. In one embodiment, a request to evaluate potential impacts by a change on an application program is received. The application program includes a set of producers, each having at least an instance and a method associated with the instance. Responsive to the request, the application program may be simulated with the change while the existing states and existing outputs of the producers are preserved.

Abstract: A computer language translator that translates all or any portion thereof of source code in an original computer language to source code in a target computer language, which may then be translated back to the original language while still maintaining concept, syntax, form of expression, and formatting of the original source code.

Abstract: The present invention provides a method and system for optimization of an intermediate representation in a graphical modeling environment. A first intermediate representation is provided. At least one optimization technique is applied to the first intermediate representation. A second intermediate representation is generated responsive to the application of the at least one optimization technique to the first intermediate representation.

Abstract: A method and system for an unattended installation of any type of a guest operating system (GOS) on a Virtual Machine (VM). Proposed method and system allow users to create an executable script, which provides automation of any GOS installation on the VM. User actions, such as mouse clicks and keyboard strokes, performed during GOS installation are recorded. The delays, time periods between clicks and strokes are recorded as well. All of this information is incorporated into an executable script. The script, when executed, simulates/reproduces GOS action sequence. This sequence reflects the behavior of GOS itself executed on a VM. The executable script is OS-independent and runs on top of system OS.

Abstract: A method and corresponding device provides for automatically detecting a protocol for a load testing routine. The method includes the steps of, for an application to be load tested, executing the application and recording communications between a first tier and a second tier during the execution. The recording step includes recording modules loaded by the application, recording network traffic and Web traffic, comparing the recorded modules, network traffic and Web traffic to a rule set, and based on the comparing step, selecting one or more protocols appropriate for load testing the application. Finally, the method includes the step of generating a script based on the recorded communications and the protocols, where the script specifies the protocols.

Abstract: System and methods for assembling electronic devices (110) using removable programmable active processing modules (120) are provided. An active processing module includes a first input/output (I/O) interface (202) and a second I/O interface (204). The active processing module also includes a controller (206) communicatively coupled to the first and the second I/O interfaces, where the controller is configured for selectively operating the active processing module in a programming mode or at least one component mode. In the programming mode, the active processing module is enabled to receive a plurality of operating parameters from a first electronic device via the first I/O interface to configure the active processing module to provide a functionality of a component for a second electronic device via at least one of the first and the second I/O interfaces. In the component mode, the active processing module is configured to operate according to the plurality of operating parameters.

Abstract: Software managing long names in an application programming interface receives a request to perform a requested operation on one or more fields, the application comprising a first operation operable to perform the requested operation on at least one field type. The software determines whether the field type of any of the fields is incompatible with the first operation. If the field types of the one or more fields are compatible with the first operation, then the software performs the requested operation on the one or more fields using the first operation. If the software determines that the field type of at least one of the fields is incompatible with the first operation, then it converts the request into a call for a second operation operable to perform the requested operation on the one or more fields and performs the requested operation using the second operation.

Abstract: An information processing system includes a preparation machine with an installed image; an execution machine on which the installed image is virtually installed; and a virtualizer for virtualizing the installed image on the execution machine to produce a virtually installed image by using a hierarchy of selective virtualizers, wherein the virtualizing is selective such that not all operations of the executing software of the installed image at any particular level are virtualized.

Abstract: One embodiment of the present invention sets forth a technique for representing and managing a multi-architecture co-processor application program. Source code for co-processor functions is compiled in two stages. The first stage incorporates a majority of the computationally intensive processing steps associated with co-processor code compilation. The first stage generates virtual assembly code from the source code. The second stage generates co-processor machine code from the virtual assembly. Both the virtual assembly and co-processor machine code may be included within the co-processor enabled application program. A co-processor driver uses a description of the currently available co-processor to select between virtual assembly and co-processor machine code. If the virtual assembly code is selected, then the co-processor driver compiles the virtual assembly into machine code for the current co-processor.

Abstract: Input from a text editor containing lines of text of a script is received, commands to control objects in a simulation are identified in the lines of text in the editor, a state of the simulation is updated in accordance with the input and the commands, and the simulation is displayed in a graphical display. A computer program enables a user to walk around in a simulation, with the events in the simulation determined by pre-written scripts.

Abstract: Via an internal bus 69, a host emulation unit 61 of a control procedure unit 60 loads a program under development into, and sends program execution control commands to, a program under development execution unit 70 which includes an engine processor. In response to these program execution control commands, the program under development execution unit 70 performs execution starting, stopping, pausing, or resumption of the program under development. On the other hand, execution mode setting information for the program under development is sent from an execution mode setting unit 62 of the control procedure unit 60 via the internal bus 69 to the program under development execution unit 70, in response to commands from the user. Based upon this execution mode setting information, the program execution operation by the engine processor is controlled by the program under development execution unit 70.

Abstract: An associated development-support apparatus for a semiconductor device enables highly accurate debugging and verification of operations. An emulator stub acquires event information by using a communication control unit, where the event is generated in a debugger, the event information is generated by a debugger stub according to an event, and transmitted by the debugger stub through a communication network. An emulator control unit analyzes the acquired event information, and controls an emulator according to the analyzed event so as to perform emulation processing which virtually emulates operations of the semiconductor device corresponding to the event based on hardware design information. The emulator stub acquires results of the event which is generated in association with the operations of the semiconductor device virtually emulated by the emulator, and notifies the debugger of the results of the event through the communication network and the debugger stub.

Abstract: A method and apparatus for processor emulation using speculative forward translation are disclosed. A potential candidate for forward translation is identified from one or more portions of target system code. A priority for forward translation is assigned to the potential candidate. It is determined whether the potential candidate is a valid candidate for forward translation. If valid, the potential candidate is translated with a host system to produce one or more corresponding blocks of translated code executable by the host system.

Abstract: A method and system for a software driver of a graphics controller to work with a display codec. The software driver may be configured to work with different display codecs at different periods of time while using a default configuration. Other embodiments are also described.

Abstract: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a <variable#, offset> pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.

Abstract: In one embodiment, a method comprises receiving an application that describes functions according to a prescribed symbol manipulation language, the prescribed symbol manipulation language a non-Turing complete language that does not permit partial functions and describes the functions independent of any attribute of any computing system; identifying, in the application, a distribution annotation that identifies a candidate element in the application, the candidate element configured for execution in a distributed computing operation by a distributed computing system comprising two or more distributed computing devices; generating one or more variants of the application based on executing a nondestructive transformation of the application relative to prescribed equality axioms, at least one of the variants containing a corresponding semantically-equivalent variation of the candidate element; and selecting one of the variants as an optimization for execution of the application by the distributed computing syste

Abstract: A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended.

Abstract: A data backup system is provided for backing up data files from a data source and for securing those data files against accidental modification or deletion. The system comprises storage and a data protection component that includes an application programming interface defining a command set. The system can also comprise a backup application that is configured to use the commands of the command set. The data protection component allows applications that use the commands of the command set, such as the backup application, to access the storage of the system. The data protection component prevents operating systems and applications that do not use the commands of the command set from accessing the storage. The data protection function of the data protection component can optionally be disabled to allow open access to the storage.

Abstract: An emulation system that provides the functionality of an emulated computer on a host computer pre-processes the object code file to be emulated to reduce the run-time overhead due to parsing the object code. The emulator uses pre-programmed functions that model each instruction of the emulated computer. An object code file is pre-parsed to generate a translated file which includes a sequence of function calls corresponding to the sequence of instructions in the code file. The translated file is compiled to generate a corresponding translated object-code file. The translated object-code file is executed in the emulation environment on the host computer. The emulation system also includes a standard mode in which the object code file is emulated by sequentially parsing each instruction in the object code file and invoking an appropriate one of the preprogrammed functions in the emulated environment.

Abstract: An RPM subsystem can be installed on a system that has its own native packaging subsystem. The RPM subsystem is initially delivered as a package wrapped in the non-RPM format of the native packaging system and installed. When an RPM package is installed, the RPM subsystem is also configured to create a stub entry in the native packaging, non-RPM system. The stub entry may contain the normal package information, such as name, version, description, as well as a list of files contained in a package. The stub may also contain uninstallation logic, which serves as a “callback” into the RPM subsystem during package removal and causes the RPM subsystem to remove the package when invoked. Removal of a RPM package via RPM tools also causes the removal of the stub entry.

Abstract: A method, system and program product for optimizing emulation of a suspected malware. The method includes identifying, using an emulation optimizer tool, whether an instruction in a suspected malware being emulated by an emulation engine in a virtual environment signifies a long loop and, if so, generating a first hash for the loop. Further, the method includes ascertaining whether the first hash generated matches any long loop entries in a storage and, if so calculating a second hash for the long loop. Furthermore, the method includes inspecting any long loop entries ascertained to find an entry having a respective second hash matching the second hash calculated. If an entry matching the second hash calculated is found, the method further includes updating one or more states of the emulation engine, such that, execution of the long loop of the suspected malware is skipped, which optimizes emulation of the suspected malware.

Abstract: Arbitrary, unmodified code and/or software may be executed directly on a host processor operating in a virtualized mode using hardware virtualization support and performance counters. The arbitrary software may be run on the host processor until the host processor exits from the virtualized mode. An end execution time may be calculated in response to the host processor exiting from the virtualized mode. An event may then be handled based on an execution time at which the host processor exited from the virtualized mode and a time at which a scheduled event was to occur.

Abstract: Disclosed are new approaches for building an application for a specific platform. Source code files may be compiled to an intermediate module and transmitted to a build server along with metadata describing a target operating environment. The build server selects an application template including an application shell suitable for the target operating environment. The application shell may be bound to the intermediate module by modifying the application shell to verify a signature of the intermediate module prior to executing it. The application shell may include a binary executable for executing the intermediate module in the target environment. Also disclosed is an approach for providing access to an application on a subscription or trial basis.

Abstract: In some embodiments, antivirus/malware behavior-based scanning (emulation) is accelerated by identifying known code sequences and executing pre-stored native-code routines (e.g. decompression, decryption, checksum routines) implementing the functionality of the known code sequences before returning to the emulation. During emulation, target machine code instructions are compared to a set of known signatures. If a known code sequence is identified, the emulator calls a native code routine and caches the current instruction address. If the emulator subsequently reaches a cached address, a native code routine may be called without scanning the data at the address for known signatures. Signature scanning may be performed selectively for instructions following code flow changes (e.g. after jump, call or interrupt instructions).

Abstract: In emulation of a target system on a host system one or more blocks of target system code may be translated with the host system to produce one or more corresponding blocks of translated code. Translating the target system code may include linking two or more blocks of translated code together to form a chain such that a look-up in a first translated block in the chain will directly branch to a second translated block. The target system code may be analyzed for the presence of one or more native target system instructions indicating modification of the target system code during execution. If such native target system instructions are present some or all of the blocks of translated code may be marked potentially invalid. The one or more blocks marked as potentially invalid may be re-translated and one or more instructions in the blocks of translated code may be overridden without undoing the chain.

Abstract: A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA's to a higher-performance one of the ISA's. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

Abstract: A method (and system) for performing an emulation of an operation of a target computing system, includes interpreting a target instruction, recognizing an unused capacity of a host system when the host system is interpreting the instruction, and performing a translation of the instruction without increasing a time of interpreting the instruction.

Abstract: A product rate calculation system operating as a rating server (e.g., a process executing on a server computer system, or a process executing on the same computer system as a client process but serving information to the client process) advantageously provides a flexible insurance rating calculation system that can easily be modified and expanded, while still providing quick, and even real-time responsiveness to product rate requests. The product rate calculation system includes an interface to a product information database and a cache for storing product rate information for efficient reuse. The product rate information includes product rate expressions that are parsed and evaluated by an expression evaluation routine to determine a product rate. As part of the evaluation process, additional product rate information (such as look-up table data and numerical constants) as well as consumer information can be used.

Abstract: Assigns suitable registers to a plurality of variables. A compiler converts a source program into instructions for a processor having: a simultaneously used variable acquisition section which obtains, with respect to each of a plurality of variables used in the source program, some of the other variables used simultaneously with the variable; an allocation sequence generation section which generates a plurality of allocation sequences between the plurality of variables to allocate each variable to one of the plurality of registers different from those to which some of the other variables used simultaneously with the variable are allocated; an allocation priority acquisition section which obtains allocation priorities indicating to which one of the plurality of registers each variable is allocated with priority; and a register allocation section which allocates the variables to registers in accordance with an allocation sequence selected on the basis of the allocation priorities.

Abstract: A method of simulating a program. Compiled and interpretive techniques are combined into a just-in-time cached compiled technique. When an instruction of a program simulation is to be executed at run-time, a table of compiled instructions is accessed to determine whether compiled data for the instruction is stored in the table. If the compiled data is not therein, the instruction is compiled and stored in the table. The compiled data is returned to a simulator that is executing the program simulation. In another embodiment, before storing new information in the table, another table may be consulted to determine if the location to which the new information is to be stored is protected. If the table location is protected, the new information is not stored in the table. Rather, the new information is simply passed on to the simulator.

Abstract: A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.

Abstract: A method, system and computer program product are provided for creating software that can be used to reformat incoming insurance-related data into a format that conforms to the requirements or preferences of the receiving party. In particular, the software generated is capable of causing a particular action to be taken which will result in the transfer of the received data from one format to another in response to certain conditions being met. These conditions are defined by a decision table, from which the software is automatically generated. A means is further provided for using the received data, which has been reformatted where necessary, to create a user-friendly table that defines the rules and parameters of a particular insurance policy. The table is capable of being easily understood by those unfamiliar with the intricacies of insurance claim processing and programming code, and is further capable of being read by a claims processing engine when processing an insurance claim.

Abstract: Processor emulation using fragment level translation is disclosed. A target system having a main target processor, a secondary target processor element and an instruction memory associated with the secondary target processor element may be emulated with a host system having one or more host processors and a host memory. Two or more target system code instructions for the secondary target processor may be grouped into one or more fragments with known starts and ends. A data structure that maps the host memory locations of the starts and ends may be maintained. Each fragment may be translated into a corresponding set of position-independent translated fragments executable by the host system. The translated fragments may be loaded into one or more of the host processors. If a memory layout for target system code corresponding to the one or more fragments has changed, the fragments may be dynamically re-linked, without re-translation, and executed.