Abstract: Efficient statistical profiling in embedded computing devices, such as video games, uses a hybrid random distribution of sampling points for more accurate reconstruction of executing code. Transmission of only function start addresses and corresponding representation of the call graph data reduces the memory overhead and increases communication speed.

Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler generates machine code corresponding to a set of elements including a general purpose element and a special purpose element. The compiler identifies a portion in an arrangement of relationally connected operators that corresponds to a special purpose element. The compiler also determines whether the portion meets a condition to be mapped to the special purpose element. The compiler also converts the arrangement into an automaton comprising a plurality of states, wherein the portion is converted using a special purpose state that corresponds to the special purpose element if the portion meets the condition. The compiler also converts the automaton into machine code. Additional apparatus, systems, and methods are disclosed.

Abstract: An application executing on a computing device may invoke a function call of a first function. The computing device may support a bundled application library of functions and a native library of functions. It may be determined that code for executing the first function exists in both the bundled application library and the native library, and the application may execute the first function using the code in the native library. While the application continues execution on the computing device, the application may invoke a function call of a second function. It may be determined that, of the bundled application library and the native library, the code for executing the second function exists in the bundled application library. The application may execute the second function using the code in the bundled application library.

Abstract: Cooperative program code transformation includes receiving a transformation hint request, obtaining a suitable transformation hint, and providing the suitable transformation hint such that it is used to transform at least a portion of the program code and generate optimized code.

Abstract: A system, method, and computer program product are provided for determining settings for a device. In use, a plurality of parameters associated with a device is identified. Additionally, one or more settings associated with the device are determined, based on the plurality of parameters.

Abstract: Presently described is a decompilation method of operation and system for parsing executable code, identifying and recursively modeling data flows, identifying and recursively modeling control flow, and iteratively refining these models to provide a complete model at the nanocode level. The nanocode decompiler may be used to determine if flaws, security vulnerabilities, or general quality issues exist in the code. The nanocode decompiler outputs in a standardized, human-readable intermediate representation (IR) designed for automated or scripted analysis and reporting. Reports may take the form of a computer annotated and/or partially human annotated nanocode listing in the above-described IR Annotations may include plain English statements regarding flaws and pointers to badly constructed data structures, unchecked buffers, malicious embedded code or “trap doors,” and the like. Annotations may be generated through a scripted analysis process or by means of an expert-enhanced, quasi-autonomous system.

Abstract: A system, method, and computer program product are provided for determining a monotonic set of presets. In use, a plurality of parameters associated with a product or service is identified. Additionally, a monotonic set of presets associated with the product or service are determined, based on the plurality of parameters.

Abstract: An information processor has an older version program and a latest version program of the same application software installed thereon. The information processor includes: an older version detection unit that detects the older version program installed on the information processor; a path name modification unit that modifies a first path name of a file storing the older version program to a second path name if the older version detection unit detects the older version program; and a start program file generation unit that generates a start program file storing a start program. The start program file generation unit generates the start program file as a file having the first path name, after the path name modification unit executes the path name modification.

Abstract: A system, method, and computer program product are provided for calculating settings for a device, utilizing one or more constraints. In use, a plurality of parameters associated with a device is identified. Additionally, one or more constraints are determined, utilizing the plurality of parameters. Further, one or more settings are calculated for the device, utilizing the one or more constraints and the plurality of parameters.

Abstract: A mechanism is provided for process-aware code migration. A plurality of nodes and a plurality of edges are annotated within a call graph with information from execution data for executing the code and a topology of the data processing system to form an annotated call graph. Each node in the plurality of nodes is clustered into an associated cluster based on a subset of attributes used from the execution data or the topology to generate the annotated call graph to form a clustered call graph comprising a plurality of clusters. The execution data associated with each cluster in the plurality of clusters is process mined to form an existing process model. Processes identified within the existing process model are mapped to a proposed business-process model thereby forming a set of correlations between the existing process model and the proposed business-process model.

Abstract: A compilation method is provided for correcting compiler errors that include compiler internal errors and errors produced by running a validation suite. The method includes running a compiler on a computer and storing a set of optimization levels in memory accessible by the compiler. The method includes receiving a source file with the compiler that includes a user-defined optimization level to be used in compiling the source file. The method includes identifying a set of functions within the source file and using compiler components to compile these functions using the original optimization level. When the compiling results in an internal error occurring and being reported for one or more of the functions, the method includes using an optimization adjustment module to process the internal error and assign an adjusted or lower optimization level to the one or more functions and recompiling of these functions again with the lower optimization level.

Abstract: A system, method, and computer program product are provided for determining whether parameter configurations meet predetermined criteria. In use, predetermined criteria associated with a software element are identified. Additionally, it is determined whether each of a plurality of different parameter configurations meets the criteria, utilizing a directed acyclic graph (DAG).

Abstract: The present technology is directed to accurately identifying code execution rhythms from a running program, even when they are occasionally irregular. The present technology is capable of detecting and inferring the rhythms without any prior knowledge or expectations of rates or number of rhythms present in a running program. These code execution rhythms can then be used to further understand and analyze the behavior of a running program, for example, by exposing various rhythms that might have been unknown/unrealized, irregularity of rhythms, or by analyzing the behavior of functions on a per frame basis under different rhythms.

Abstract: Technologies are generally provided for optimizing virtual machine performances at a datacenter and managing sudden resource demand changes by co-residing applications on same virtual machines through a flexible resource demand certification approach. A flexible resource demand certificate may be generated for applications including predetermined operating compilation architectures that run well but have different resource demands. A Just-In-Time (JIT) compiler may be directed to selected target settings for a combination of operational parameter settings such that the co-residing applications can share resources without overloading system resources. Applications to be migrated to a new datacenter or a new virtual machine at a datacenter may be assigned and adjusted according to their and potential co-residing applications' certificates providing optimized resource usage.

Abstract: A computer-implemented method for compilation of applications includes storing, at a server, a plurality of variants, wherein each of the plurality of variants describes a distinct client architecture. A plurality of optimized binaries for an application are maintained at the server, wherein the plurality of optimized binaries correspond to different variants in the plurality of variants. The server receives a request from a client to download the application, wherein the request includes a reference to a first variant that describes the client's architecture. A determination is made that the first variant corresponds to a first optimized binary of the plurality of optimized binaries, and the server provides the first optimized binary to the client.

Abstract: Illustrative embodiments disclose setting refresh rates for different portions of a shared screen in a sharing session. A processor sets an initial refresh rate for the sharing session. The processor selects a portion of the shared screen. The processor selects a refresh rate for the selected portion of the shared screen that is different from the initial refresh rate for the sharing session. The processor refreshes the selected portion based on the selected refresh rate and a portion not selected based on the initial refresh rate.

Abstract: Illustrative embodiments disclose setting refresh rates for different portions of a shared screen in a sharing session. A processor sets an initial refresh rate for the sharing session. The processor selects a portion of the shared screen. The processor selects a refresh rate for the selected portion of the shared screen that is different from the initial refresh rate for the sharing session. The processor refreshes the selected portion based on the selected refresh rate and a portion not selected based on the initial refresh rate.

Abstract: A computer program product and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.

Abstract: A system and associated methods are disclosed for profiling the execution of program code by a processor. The processor provides an instruction set with special profiling instructions for efficiently determining the bounds and latency of memory operations for blocks of program code. Information gathered regarding the bounds and latency of memory operations are used to determine code optimizations, such as allocation of memory for data structures in memory more local to the processor.

Abstract: A system and method for efficient compilation and invocation of function type calls in a virtual machine (VM), or other runtime environment, and particularly for use in a system that includes a Java Virtual Machine (JVM). In accordance with an embodiment, the system comprises a virtual machine for executing a software application; a memory space for the application byte code comprising callsites generated using a function type carrier; a bytecode to machine code compiler which performs MethodHandle invocation optimizations; a memory space for the compiled machine code; and a memory space for storing software objects as part of the software application. The system enables carrying the function type from the original MethodHandle to a callsite in the generated bytecode, including maintaining generics information for a function type acquired from a target function, and generating a callsite based on the generics information for the function object invocation.

Abstract: A method of generating an executable that operates as a compiler includes: receiving a unified input description containing syntax rules for both regular and context-free expressions and interspersed code; generating a common internal representation from the unified input description; checking regular expressions in the common internal representation; checking context-free expressions in the common representation; checking the interspersed code; and outputting the executable.

Abstract: A device generates code with a technical computing environment (TCE) based on a model and information associated with a target processor, registers an algorithm with the TCE, automatically sets optimization parameters applied during generation of the code based on the algorithm, executes the generated code, receives feedback based on execution of the generated code, and uses the feedback to automatically update the optimization parameters and to automatically regenerate the code with the TCE until an optimal code is achieved for the target processor.

Abstract: Redundant run-time type information is removed from a compiled program. The redundant type information may be unneeded and/or duplicate. Unneeded type information is removed by selecting instances of type information from read only data sections of object files. The entire compiled program is searched for instructions that use the instances. The instances that do not correspond to such instructions are removed from the object files. Duplicate type information is removed by selecting instances of type information from read only data sections of object files. The read only data sections of the other object files in the compiled program are then searched for the selected instances. The selected instances that exist in the read only data sections of the other object files are removed. Redundant type information may be removed from individual object files before concatenation into a single binary file and/or from a single binary file after concatenation.

Abstract: In a method for dynamically replacing code within a software application on a device, an annotated code segment that performs a function according to a first data policy is received. The computer determines an alternate segment that performs the function according to a second data policy.

Abstract: A computer-implemented method and apparatus for transforming code to embedded environments, the method comprising: receiving program code not complying with a limitation of an embedded computing environment; transforming at least part of the program code to modified program code in order for the modified program code to be in compliance with the limitation; and storing the modified program code on a storage device. wherein the modified program code complies with the limitation of the embedded computing environment.

Abstract: Systems, methodologies, computer-readable media, and other embodiments associated with ordering instructions are described. One exemplary system embodiment can include an analysis logic configured to analyze executable instructions from an executable program. A re-write logic can be configured to re-order selected load instructions within the executable program based on latency times for the selected load instructions.

Abstract: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.

Abstract: Techniques are described for unifying static and dynamic compiler optimizations in source code bases. In an embodiment, a first compiler compiles source code of a target function to generate ahead-of-time (AOT) compiled machine code. A second compiler compiles the source code to generate an intermediate representation (IR) of the target function. In response to determining that the target function should be just-in-time (JIT) compiled, the AOT-compiled machine code for the target function is linked to the IR of the target function. During runtime, a physical processor executes AOT-compiled machine code of an executable program. When the target function is encountered for the first time, a JIT compiler is invoked. The JIT compiler generates JIT-compiled machine code for the target function. The physical processor executes the JIT-compiled machine code in place of the AOT-compiled machine code for the target function.

Abstract: A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access within the transaction, the access is performed without access barriers. However, if the annotation field is in a default state representing no previous access during a pendancy of the transaction, then a mode of the processor is determined. If the processor mode is in implicit mode, an access handler/barrier is asynchronously executed. Conversely, in an explicit mode, a flag is set instead of asynchronously executing the handler. In addition, during compilation convert explicit and convert implicit instructions are inserted to intelligently convert modes for precompiled and newly compiled binaries.

Abstract: A mechanism is described for facilitating dynamic and efficient fusion of computing instructions according to one embodiment. A method of embodiments, as described herein, includes monitoring a software program for a program region having fusion candidate instructions for a fusion operation at a computing system; evaluating whether the macro operation of the candidate instructions is valuable to the software program; and performing the fusion operation if it is evaluated to be valuable.

Abstract: A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.

Abstract: Systems for program analysis include a high-level scanning tool configured to perform a high-level analysis on a program using a processor to generate one or more high-level findings; one or more low-level scanning tools, each configured to perform a low-level analysis on the program using a processor to generate a low-level finding; and a mapping module configured to map the one or more low-level findings to the high-level findings to generate a concise combination report that categorizes each finding according to the highest-level analysis that produces the finding.

Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler generates machine code corresponding to a set of elements including a general purpose element and a special purpose element. The compiler identifies a portion in an arrangement of relationally connected operators that corresponds to a special purpose element. The compiler also determines whether the portion meets a condition to be mapped to the special purpose element. The compiler also converts the arrangement into an automaton comprising a plurality of states, wherein the portion is converted using a special purpose state that corresponds to the special purpose element if the portion meets the condition. The compiler also converts the automaton into machine code. Additional apparatus, systems, and methods are disclosed.

Abstract: In one embodiment, a decision tree is evaluated in interpreted mode while statistics are collected. The decision tree is then represented as source code, and each decision in the decision tree is annotated with instructions determined based on the collected statistics. The source code is compiled into machine code, and the machine code is optimized based on the instructions annotating each decision in the decision tree.

Abstract: A system and method automatically inserts pipelines into a high-level program specification. An Intermediate Representation (IR) builder creates one or more graphs or trees based on the high-level program specification. A scheduler iteratively applies a bounded scheduling algorithm to produce an execution schedule for the IR minimizing overall execution time for a given number of pipeline stages. A Hardware Description Language (HDL) code generator may utilize the pipelined, scheduled IR to generate optimized HDL code corresponding to the high-level program specification. An annotated version of the high-level program specification showing where the pipelines have been inserted may be displayed allowing additional design exploration.

Abstract: A method, computer program product, and system for performing a hybrid dependency analysis is described. According to an embodiment, a method may include computing, by one or more computing devices, one or more dynamic hints based on a finite set of executions of a computer program. The method may further include performing, by the one or more computing devices, a hybrid dependence analysis of one or more statements of the computer program.

Abstract: A dynamic code translator with isoblocking uses a return trampoline having branch instructions conditioned on different isostates to optimize return address translation, by allowing the hardware to predict that the address of a future return will be the address of trampoline. An IP relative call is inserted into translated code to write the trampoline address to a target link register and a target return address stack used by the native machine to predict return addresses. If a computed subject return address matches a subject return address register value, the current isostate of the isoblock is written to an isostate register. The isostate value in the isostate register is then used to select the branch instruction in the trampoline for the true subject return address. Sufficient code area in the trampoline instruction set can be reserved for a number of compare/branch pairs which is equal to the number of available isostates.

Abstract: There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

Abstract: There are provided methods and computer program products for generating code for an architecture encoding an extended register specification. A method for generating code for a fixed-width instruction set includes identifying a non-contiguous register specifier. The method further includes generating a fixed-width instruction word that includes the non-contiguous register specifier.

Abstract: Processing a dataflow program by a program development tool includes analyzing an actor defined by the dataflow program to identify original sequences of actions that can be reformulated to achieve greater execution parallelism while maintaining the same functionality as the original sequences. A processed dataflow program is produced comprising processed dataflow program instructions and decision point program instructions. The processed dataflow program instructions comprise alternative sequences of reformulated actions that achieve greater execution parallelism while maintaining the same functionality as the identified one or more original sequences. The decision point program instructions direct processing equipment to select and execute one or more of the alternative sequences of reformulated actions, wherein selection is based on state and token information in existence at the time of selection.

Abstract: A system and method for automatically modifying a native code module accessed in a user software application are described herein. The user software application may include virtual machine bytecode. Access to the native code module may be detected during execution of the virtual machine bytecode. The native code module may be automatically modified by adding instrumentation code to determine various types of information regarding execution of the native code module, and the access may be directed to the modified native code module.

Abstract: A system including an input compiler that receives a unified input description containing syntax rules for both regular and context-free expressions and interspersed code, the first compiler configured to translate the unified input description into a common internal representation is disclosed. The system also includes a regular expression checker, a context-free expression checker, a code checker and a second compiler coupled to the code checker.

Abstract: An instruction processing method includes generating a translated code block for an instruction, among instructions included in a target program to be executed and for which a number of executions through sequential interpretation is greater than or equal to a threshold, and storing the generated translated code block in a first storage unit and removing part or all of the translated code block from the first storage unit at a given timing, wherein the generating reduces the threshold with respect to the number of executions over a given period of time after the part or all of the translated code block is removed.

Abstract: Techniques for automatic license entitlement calculation. A method includes decomposing a license metric definition into metric-generic and metric-specific logic, compiling the metric-specific logic to generate intermediate code, interpreting the metric-generic logic and dynamically loading the intermediate code to execute a license entitlement calculation.

Abstract: Techniques for automatic license entitlement calculation. A method includes decomposing a license metric definition into metric-generic and metric-specific logic, compiling the metric-specific logic to generate intermediate code, interpreting the metric-generic logic and dynamically loading the intermediate code to execute a license entitlement calculation.

Abstract: A method of integrating an existing source code into a target source code, the method including mapping a plurality of candidate mappings between a change point of the existing source code and a plurality of change points of the target source code, selecting a candidate mapping of the plurality of candidate mappings, automatically updating the existing source code based on the candidate mapping having been selected, and transplanting the existing source code having been updated into the target source code.

Abstract: A system and method for monitoring the performance and execution flow of a target application and generating a corresponding data model are provided. The system and method comprise attaching to a thread or process of a target application and tracking the execution of subroutines using instrumentation commands. Data representing the execution flow of the various subroutines, subroutine calls, and their performance is gathered and used to generate data models representing the threads and processes of the application. The data models are optionally merged and/or pruned. A visualization of the data models is generated indicating relevant points of interest within the target application's execution flow.

Abstract: Apparatuses and methods may provide for determining a level of performance for processing one or more loops by a dynamic compiler and executing code optimizations to generate a pipelined schedule for the one or more loops that achieves the determined level of performance within a prescribed time period. In one example, a dependence graph may be established for the one or more loops, and each dependence graph may be partitioned into stages based on the level of performance.

Abstract: A system and method for improving software maintainability, performance, and/or security by associating a unique marker to each software code-block; the system comprising of a plurality of processors, a plurality of code-blocks, and a marker associated with each code-block. The system may also include a special hardware register (code-block marker hardware register) in each processor for identifying the markers of the code-blocks executed by the processor, without changing any of the plurality of code-blocks.

Abstract: Apparatus, systems, and methods for a compiler are described. One such compiler generates machine code corresponding to a set of elements including a general purpose element and a special purpose element. The compiler identifies a portion in an arrangement of relationally connected operators that corresponds to a special purpose element. The compiler also determines whether the portion meets a condition to be mapped to the special purpose element. The compiler also converts the arrangement into an automaton comprising a plurality of states, wherein the portion is converted using a special purpose state that corresponds to the special purpose element if the portion meets the condition. The compiler also converts the automaton into machine code. Additional apparatus, systems, and methods are disclosed.