Process Scheduling Patents (Class 718/102)
  • Patent number: 9794136
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for allocating tasks to computing nodes using multiple resource allocators. One of the methods includes providing, by each resource allocator of a plurality of resource allocators, a first request to compute a first score to each computing node of a plurality of computing nodes, the first score representing a measure of availability for the computing node to take a particular task. A first score is received from each of the plurality of computing nodes and the nodes are ranked according to the first scores. A second request is provided to a highest-ranked computing node to compute a second score. If the difference between the first score and the second score satisfies a threshold, assigning the task to the highest-ranked computing node if and only if the difference between the first score and the second score satisfies the threshold.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: October 17, 2017
    Assignee: Pivotal Software, Inc.
    Inventors: Onsi Joe Fakhouri, Alex Paul Suraci, Amit Kumar Gupta
  • Patent number: 9788018
    Abstract: Error concealment techniques for video decoding are described. For example, a video decoder after finding a corrupted picture in a bit stream, finds a suitable neighbor for the corrupted picture. For example, the video decoder favors pictures with the same parity as the corrupted picture and considers picture order count and picture corruption in choosing a neighbor. The decoder then modifies syntax elements for the encoded video in the bit stream to allow the neighbor to be used in concealing the corruption in the corrupted picture. The modification of syntax elements can depend on the particular video decoder implementation. For example, in a software-only multithreaded video decoder, a task graph is modified, while in a system utilizing video acceleration, syntax elements for reference lists are modified.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: October 10, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yongjun Wu, Naveen Thumpudi, Daniel Dinu, William R. Sanders
  • Patent number: 9785587
    Abstract: A method for executing an application in a multitasking system is provided. The application is composed of at least one task for which the temporal triggering is specified in a first temporal reference frame that is asynchronous relative to the physical time, called first external clock domain, defined by a synchronous basic clock with changes of state of a peripheral device of the system. The method comprises a set of steps executed by the system upon reception of an occurrence of an interrupt in order to render the execution of the task deterministic or quasi-deterministic.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: October 10, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Mathieu Jan, Christophe Aussagues, Vincent David, Matthieu Lemerre
  • Patent number: 9780992
    Abstract: The present invention relates to a method for selecting a virtual slot to start up an instance of an application in a distributed system comprising a plurality of physical machines distributed on a network, each physical machine housing at least one virtual machine, and each virtual machine comprising at least one virtual slot for running an application instance in said virtual machine. The method according to the invention comprises selecting an application slot to start up an instance of an application including the following steps: determining a set of free application slots, i.e., those not occupied by an application instance in use, computing a score for each free application slot, the score computation depending on at least one constraint, selecting the application slot to start up the considered application instance, said selected application slot being that having the best score.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 3, 2017
    Assignee: SCHNEIDER ELECTRIC INDUSTRIES SAS
    Inventors: Pierre Dufrene, Guenther Schmitt
  • Patent number: 9778955
    Abstract: A system includes a plurality of queues configured to hold tasks and state information associated with such tasks. The system further includes a plurality of listeners configured to query one of the plurality of queues for a task, receive, in response to querying one of the plurality of queues for a task, a task together with state information associated with the task, effect processing of the received task, and communicate a result of the received task to another queue of the plurality of queues, the another queue of the plurality of queues being selected based on the processing of the received task.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 3, 2017
    Assignee: ALLSCRIPTS SOFTWARE, LLC
    Inventor: Jason Daniel Petit
  • Patent number: 9778943
    Abstract: Systems and methods for timer-based virtual processor scheduling. An example method may comprise: selecting, by a hypervisor executing on a computer system, an active virtual processor among two or more virtual processors; determining a first time period being less than a second time period, the second time period equal to a time remaining till a next scheduled timer interrupt of a timer communicatively coupled to the active virtual processor; and suspending the active virtual processor for at least the first time period.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: October 3, 2017
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Uri Lublin
  • Patent number: 9766866
    Abstract: One embodiment sets forth a method for efficiently determining memory resource dependencies between instructions included in a software application. For each instruction, a dependency analyzer uses overlapping search techniques to identify one or more overlaps between the memory elements included in the current instruction and the memory elements included in previous instructions. The dependency analyzer then maps objects included in the instructions to a set of partition elements wherein each partition element represents a set of memory elements that are functionally equivalent for dependency analysis. Subsequently, the dependency analyzer uses the set of partition elements to determine memory dependencies between the instructions at the memory element level.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: September 19, 2017
    Assignee: NVIDIA Corporation
    Inventor: Julius Vanderspek
  • Patent number: 9766885
    Abstract: A system includes a plurality of arithmetic devices configured to execute arithmetic processes in parallel. Each of plurality of arithmetic devices is configured to: determine whether a time period from the start of collective communication to reception from another arithmetic device involved in the collective communication is equal to or shorter than a predetermined threshold, determine a target arithmetic device that is among the plurality of arithmetic devices and for which a waiting scheme involved in the collective communication is to be changed when the time period is determined to be equal to or shorter than the predetermined threshold, and transmit, to the target arithmetic device, an instruction to change the waiting scheme involved in the collective communication.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: September 19, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Masahiro Miwa
  • Patent number: 9760399
    Abstract: The performance of a device can be improved by intelligently terminating (or otherwise operationally adjusting) applications, services, or processes that the user is unlikely to access on the device. Information such as system event data and hint data can be obtained from various sources and fed to one or more predictor algorithms, which can determine the likelihood that a user will access various applications over a period of time. Other determinations can be made as well, such as which applications are most likely causing degradation in performance. Various termination actions can be selected to be performed, which can in some cases adjust the applications selected for termination by an operating system of the device. Once a set of actions is selected, those termination actions can be performed for the associated application(s) at least to the extent needed to restore health of the device.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: September 12, 2017
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Thomas Grant Fraser, Timothy Daniel Clark, Shah Pavel Jamal, Anderson Kailodge Quach, Vincent Edward Bannister
  • Patent number: 9760506
    Abstract: A data processing system comprising a plurality of data inputs and of data outputs for processing input data and providing processed data to a data output. The system comprises a plurality of data processing hardware units, each being configured to process data within a predetermined latency and according to a data processing task of a predetermined type. The system further comprises a memory for storing a predetermined latency for each of the data processing hardware units and a controller configured to determine a type of a data processing task to be executed as a function of a source of data to be processed or of a destination of processed data and further configured to select one data processing hardware unit as a function of the determined type of the task to be executed and of latency constraints associated with the task to be executed.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: September 12, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Arnaud Closset, Pascal Rousseau
  • Patent number: 9753465
    Abstract: A method for controlling a data center, comprising a plurality of server systems, each associated with a cooling system and a thermal constraint, comprising: a concurrent physical condition of a first server system; predicting a future physical condition based on a set of future states of the first server system; dynamically controlling the cooling system in response to at least the input and the predicted future physical condition, to selectively cool the first server system sufficient to meet the predetermined thermal constraint; and controlling an allocation of tasks between the plurality of server systems to selectively load the first server system within the predetermined thermal constraint and selectively idle a second server system, wherein the idle second server system can be recruited to accept tasks when allocated to it, and wherein the cooling system associated with the idle second server system is selectively operated in a low power consumption state.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 5, 2017
    Assignee: The Research Foundation for The State University of New York
    Inventor: Kanad Ghose
  • Patent number: 9753780
    Abstract: In an example embodiment, a method of operating a task scheduler for one or more processors is provided. A topology of one or more processors is obtained, the topology indicating a plurality of execution units and physical resources associated with each of the plurality of execution units. A task to be performed by the one or more processors is received. Then a plurality of available execution units from the plurality of execution units is identified. An optimal execution unit is then determined, from the plurality of execution units, to which to assign the task, based on the topology. The task is then assigned to the optimal execution unit, after which the task is sent to the optimal execution unit for execution.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 5, 2017
    Assignee: SYBASE, INC.
    Inventors: Mohammed Abouzour, John Smirnios
  • Patent number: 9755988
    Abstract: Disclosed are methods and systems for processing a workload among a plurality of computing resources that optimizes the processing price per workload. The method includes breaking the workload into two or more tasks each having a size optimized based on (i) a price history of one or more of the plurality of computing resources and (ii) a predicted duration to complete processing of each of the respective tasks; and sending one of the two or more tasks to a computing resources for which the size of the tasks is optimized.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: September 5, 2017
    Assignee: Sonian, Inc.
    Inventors: Gregory L. Arnette, Timothy Dysinger
  • Patent number: 9740714
    Abstract: According to one embodiment of the present invention, a system with a plurality of memories, generates a first filter associated with a first memory, and generates one or more second filters each associated with a corresponding memory. Each second filter is generated with a size at least partially accommodated within the storage capacity of the associated memory. The system determines absence of items from a set by selectively probing the generated filters in an ascending order of data access speed to the associated memories and aborts further probing for an item in response to a probe indicating that the item is absent from the set. Embodiments of the present invention further include a method and computer program product for testing set membership in substantially the same manners described above.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: August 22, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gopi K. Attaluri, Ronald J. Barber, Naresh K. Chainani, Vijayshankar Raman
  • Patent number: 9734170
    Abstract: According to one embodiment of the present invention, a system with a plurality of memories, generates a first filter associated with a first memory, and generates one or more second filters each associated with a corresponding memory. Each second filter is generated with a size at least partially accommodated within the storage capacity of the associated memory. The system determines absence of items from a set by selectively probing the generated filters in an ascending order of data access speed to the associated memories and aborts further probing for an item in response to a probe indicating that the item is absent from the set. Embodiments of the present invention further include a method and computer program product for testing set membership in substantially the same manners described above.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gopi K. Attaluri, Ronald J. Barber, Naresh K. Chainani, Vijayshankar Raman
  • Patent number: 9733982
    Abstract: A computer calculates memory access rates for respective tasks on basis of hardware monitor information obtained by monitoring operating states of hardware during execution of an application program. The tasks correspond to respective syntax units specified in the application program. The computer assigns, on basis of the calculated memory access rates, a first task to a socket in a processor in response to an instruction for executing the first task.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: August 15, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yasuyuki Ohno, Kaname Mita, Naoki Sueyasu
  • Patent number: 9734078
    Abstract: A method for resetting of memory locks in a transactional memory system. The method includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The method further includes determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Nathan Fontenot, Ryan Patrick Grimm, Robert Cory Jennings, Jr., Joel Howard Schopp, Michael Thomas Strosaker
  • Patent number: 9734098
    Abstract: A method of managing a memory bus includes identifying sub-operations required for execution of commands, maintaining a list of released sub-operations containing only released unexecuted sub-operations directed to individual dies that are identified as available, accessing the dies until the list is empty, subsequently, polling to identify dies that are available, and subsequently resuming accessing the dies by executing only sub-operations from the list until the list is empty.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: August 15, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lee Gavens, Daniel Lee, Meiqing He, Christopher Dinh
  • Patent number: 9727382
    Abstract: A parallelization method includes: obtaining profiling information for each job step of a job by performing profiling of the job to be executed on an electronic device; determining at least one job step to be parallelized on a central processing unit (CPU) and at least one heterogeneous unit of the electronic device among a plurality of job steps of the job based on the profiling information; determining a unit to process each unit data among the CPU and the heterogeneous unit based on the profiling information, with respect to the determined at least one job step; and determining a unit to process each task among the CPU and the heterogeneous unit based on the profiling information, with respect to at least one job step including a plurality of separately executable tasks in the determined at least one job step.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehan Koh, Anuradha Oberoi, GopalaKrishna Puligedda Sharma, Raghavan Velappan, Priyank Popatlal Faldu
  • Patent number: 9727447
    Abstract: A system, method, and computer program product are provided for automated exploratory testing. In use, a plurality of actions to be performed as a test flow in an exploratory test associated with at least one testing project are identified. Additionally, a plurality of additional options are identified for each performed action of the plurality of actions of the test flow that are capable of being performed instead of one or more of the plurality of actions in the test flow. Further, a graph is generated showing all combinations of the plurality of first actions and the plurality of additional options as a possible scope of the exploratory test associated with the at least one testing project. In addition, the graph is modified based on received input, the received input identifying one or more test flows to execute as the exploratory test associated with the at least one testing project.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: August 8, 2017
    Assignees: Amdocs Software Systems Limited, Amdocs Development Limited
    Inventor: Sharon Elgarat
  • Patent number: 9723080
    Abstract: A storage apparatus includes a storage unit for storing data read/written by a host computer and provides the host computer with a storage area of the storage unit as one or more volumes. The storage management computer includes a first memory for storing task information including contents of an operation process performed on the storage apparatus, as well as a scheduled starting time and scheduled termination time of a process. In the case where first task information is stored in the first memory, when resources used in the process of second task information stored in the first memory are the same as resources used in the process of the first task information, the storage management computer computes times required for executing the first task information and the second task information, based on a time during which the processes of the first and second task information conflict with each other.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: August 1, 2017
    Assignee: HITACHI, LTD.
    Inventors: Tsukasa Shibayama, Yukinori Sakashita, Masayasu Asano
  • Patent number: 9720729
    Abstract: A runtime environment allows a scheduler in a process of a computer system to be finalized prior to the process completing. The runtime environment causes execution contexts that are inducted into the scheduler and execution contexts created by the scheduler to be tracked. The runtime environment finalizes the scheduler subsequent to each inducted execution context exiting the scheduler and each created execution context being retired by the scheduler.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: August 1, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Paul Ringseth, Genevieve Fernandes, Rick Molloy, Rahul Patil
  • Patent number: 9721566
    Abstract: At a first electronic device with a display and a microphone: sampling audio input using the first microphone; in accordance with the sampling of audio input using the first microphone, sending stop instructions to a second electronic device with a second microphone, the second electronic device external to the first electronic device, wherein the second electronic device is configured to respond to audio input received using the second microphone, and wherein the stop instructions instruct the second electronic device to forgo responding to audio input received using the second microphone, wherein responding to audio input received using the second microphone comprises providing perceptible output.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: August 1, 2017
    Assignee: Apple Inc.
    Inventors: Brandon J. Newendorp, Evan S. Dibiase
  • Patent number: 9715406
    Abstract: An operating system provides a pool of worker threads servicing multiple queues of requests at different priority levels. A concurrency controller limits the number of currently executing threads. The system tracks the number of currently executing threads above each priority level, and preempts operations of lower priority worker threads in favor of higher priority worker threads. A system can have multiple pools of worker threads, with each pool having its own priority queues and concurrency controller. A thread also can change its priority mid-operation. If a thread becomes lower priority and is currently active, then steps are taken to ensure priority inversion does not occur. In particular, the current thread for the now lower priority item can be preempted by a thread for a higher priority item and the preempted item is placed in the lower priority queue.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: July 25, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pedro Teixeira, Arun Kishan
  • Patent number: 9715411
    Abstract: A technique for mapping logical threads to physical threads of a simultaneous multithreading (SMT) data processing system includes mapping one or more logical threads to one or more physical threads based on a selected SMT mode for a processor. In this case, respective resources for each of the one or more physical threads are predefined based on the SMT mode and an identifier of the one or more physical threads. The one or more physical threads are then executed on the processor utilizing the respective resources.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Richard William Doing, Brian R. Konigsburg, David Stephen Levitan, Kevin Neal Magill
  • Patent number: 9710309
    Abstract: One aspect provides a method including: identifying a task to be scheduled for execution on an information handling device having a big core and a little core; in a state where the big core is available, scheduling the task for execution on the little core using a core signature for the task; directing the task to the little core for execution based on the scheduling; and executing the task on the little core. Other aspects are described and claimed.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: July 18, 2017
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Mark Charles Davis, Howard Locker, Daryl Cromer, Scott Edwards Kelso
  • Patent number: 9712646
    Abstract: An operation (such as a relational query) may be processed on a processing engine (such as a relational database server) on behalf of a client. A conventional processing involves the delivery of the operation to the processing engine, which executes the entire operation to completion and returns a result data set. It may be more efficient to allocate part of the operation to be performed on the client, but a developer may be unable or unavailable to rewrite the operation in a distributed manner. Instead, the operation may be automatically partitioned into a pre-engine client portion, a processing engine portion, and a client portion, and the instructions of each portion may be automatically allocated respectively to the client, the server, and the client. The partitioning may be adjusted to conserve computing resources, such as bandwidth and storage, and the instructions may be reordered to improve the processing of the operation.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: July 18, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Erik Meijer, Dinesh Chandrakant Kulkami, Matthew J. Warren, Anders Hejlsberg
  • Patent number: 9703573
    Abstract: Embodiments are directed to a heterogeneous system for dynamically mapping library calls to one of a plurality of processing platforms. The plurality of processing platforms include a central processing unit (CPU) and one or more acceleration units as co-processing units. The system includes an interposer configured to intercept the library calls from an application programming interface (API) and to map the library calls to one of the plurality of processing platforms according to a classification scheme based on an affinity table. The affinity table includes call signatures representing input parameters of sample library calls. Furthermore, the affinity table includes one or more performance parameters of the sample library calls for each of the processing platforms. The performance parameters indicate the performance of the sample library calls on the respective processing platform. Also included are a related method and a related computer program product.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heiner Giefers, Raphael Polig
  • Patent number: 9699120
    Abstract: Disclosed example methods for network switch control include accessing link characteristics for a plurality of network switches. The disclosed example methods also include comparing the link characteristics for the plurality of network switches with resource characteristics associated with a data processing function to determine a first one of the network switches on which to execute the data processing function. The disclosed example methods also include scheduling data processing function to be executed by the first one of the network switches.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: July 4, 2017
    Assignee: AT&T Intellectual Property II, L.P.
    Inventor: Joseph B. Weinman, Jr.
  • Patent number: 9690617
    Abstract: Embodiments of adjustment of a task execution plan at runtime by a task execution engine configured to receive a plan compilation task, the plan compilation task comprising a task execution plan, are provided. An aspect includes receiving a first plan compilation task by the task execution engine through a plan compilation interface. Another aspect includes modifying a task execution plan of the first plan compilation task in response to receiving a second plan compilation task by the task execution engine, the second plan compilation task comprising a task execution plan for modifying the task execution plan of the first plan compilation task. Yet another aspect includes reading a next task in the task execution plan of the first plan compilation task and initiating the next task by the task execution engine.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jun Jie J. Jiang, Xin Pei Lang, Liu Xin Peng, Jin Liang Shi, Xiao Ji Tian, Xiu Cheng Wu, Jun Hong Zhao
  • Patent number: 9690361
    Abstract: An analog frontend (AFE) interface is dynamically programmable based on a determined operating state. The AFE includes hardware to interface with multiple different sensors. The AFE includes analog processing hardware that can select input data from one of the multiple sensors. The analog processing hardware is coupled to a processor that computes features from the sensor, where the features represent selected operating condition information of the AFE for the sensor. The processor is to determine one of multiple discrete operating states of the AFE for the sensor based on the computed features and dynamically adjust operation of the AFE to interface with the sensor based on the determined operating state. Dynamically adjusting the operation of the AFE includes controlling a configuration of the AFE that controls how the AFE receives the input sensor data from the sensor.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Oguz H Elibol, Varvara Roula Kollia, Esha John, Ryan M Field
  • Patent number: 9672073
    Abstract: Distributing work in a distributed computing environment that includes multiple nodes. An individual node can receive a work assignment, which can then be divided into a plurality of work units. A first work unit can then be distributed to a first worker node. At least a portion of the first work unit can be re-distributed to a second worker node in response to determining that the first worker node has experienced a failure condition with respect to the first work unit.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: June 6, 2017
    Assignee: SYBASE, INC.
    Inventors: Kurt Wilhelm Deschler, Kaushal Mittal, Curtis Grant Johnson, Victor Mesenzeff, Jr., William Harrison Cox
  • Patent number: 9672064
    Abstract: The following relates generally to computer system efficiency improvements. Broadly, systems and methods are disclosed that improve efficiency in a cluster of nodes by efficient processing of tasks among nodes in the cluster of nodes. Assignment of tasks to compute nodes may be based on learned CPU capabilities and I/O bandwidth capabilities of the compute nodes in the cluster.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: June 6, 2017
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Shekhar Gupta, Christian Fritz, Johan de Kleer
  • Patent number: 9674302
    Abstract: A computing resource associated with a user is scheduled to undergo a transition. Prior to the scheduled transition, the computing resource is placed in a pending state. The user is notified that the computing resource is scheduled to undergo the transition. In response to an input received from the user, the computing resource is allowed to undergo the transition when the input indicates that the transition can proceed.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: June 6, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Ahmed Usman Khalid, Eric Samuel Stone, Nikita Pinski, Alexander Kulikov, Derek Solomon Pai
  • Patent number: 9658887
    Abstract: A single workload scheduler schedules sessions and tasks having a tree structure to resources, wherein the single workload scheduler has scheduling control of the resources and the tasks of the parent-child workload sessions and tasks. The single workload scheduler receives a request to schedule a child session created by a scheduled parent task that when executed results in a child task; the scheduled parent task is dependent on a result of the child task. The single workload scheduler receives a message from the scheduled parent task yielding a resource based on the resource not being used by the scheduled parent task, schedules tasks to backfill the resource, and returns the resource yielded by the scheduled parent task to the scheduled parent task based on receiving a resume request from the scheduled parent task or determining dependencies of the scheduled parent task have been met.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 23, 2017
    Assignee: International Business Machines Corporation
    Inventors: Alicia E. Chin, Yonggang Hu, Zhenhua Hu, Jason T S Lam, Zhimin Lin
  • Patent number: 9658883
    Abstract: A controller apparatus obtains job history information including execution records of one or more jobs not registered in a scheduler. Based on the job history information, the controller apparatus then estimates resource usage during execution time periods initially scheduled for jobs registered in the scheduler. This resource usage includes that of at least one of the jobs not registered in the scheduler which is to be executed together with the registered jobs on an information processing apparatus. When the estimated resource usage satisfies predetermined conditions, the controller apparatus schedules jobs including the registered jobs and the at least one of the non-registered jobs.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: May 23, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shinji Nagasawa, Yuta Kojima
  • Patent number: 9658893
    Abstract: Systems and methods for multilayered resource scheduling are provided. A system may include a user interface, an upper level scheduler, at least one lower level scheduler, and a reporting module. The user interface may receive a plurality of tasks. The upper level scheduler may sort the plurality of tasks into tasks with identical resource requirements. The lower level scheduler may be operable to receive resource requirements associated with a task. The lower level scheduler may ascertain compute resources sufficient to execute the task on a machine in a compute farm and advertise the compute resources as matching the resource requirements. The lower level scheduler may further receive a request to execute the task on the machine. The compute resources may be controlled to execute the tasks with the identical resource requirements without further scheduling operations. The lower level scheduler may control the compute resources to execute the task.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: May 23, 2017
    Assignee: Runtime Design Automation
    Inventors: Jeremy Minor, Stuart Taylor
  • Patent number: 9652288
    Abstract: A method for adaptively allocating resources to a plurality of jobs. The method comprises selecting a first policy from a plurality of policies for a first job in the plurality of jobs by using a policy selection mechanism, allocating at least one resource to the first job in accordance with the first policy, and in response to completion of the first job, updating the policy selection mechanism to obtain an updated policy selection mechanism by using at least one processor. Updating the policy selection mechanism comprises evaluating the performance of the first policy with respect to the first job by calculating a value of a metric of utility for the first policy based on conditions associated with execution of the first job and updating the policy selection mechanism based on the calculated value and a delay of execution of the first job.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: May 16, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Navendu Jain, Ishai Menache, Ohad Shamir
  • Patent number: 9647973
    Abstract: Items of an item set may be stored by an item server (e.g., mail messages comprising a mailbox stored by a mail server) that supports the application of actions, but only within a constraint (e.g., a maximum duration or computational resources consumed by the action). The application of complex actions to large item sets may exceed the constraint if performed in one request. Moreover, the request may be made by a user interface of a user device, but the user interface may stall while interoperating with the item server to perform the action. Instead, a background process may issue a sequence of requests applying the action to respective batches of items within the constraint. This architecture may enable the user interface to remain responsive to the user while the action is performed, and even to be terminated without jeopardizing the completion of the action upon the item set.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: May 9, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: David Bruce Lindsay, Geoffrey M. Clark, Baskaran Dharmarajan, Ashutosh Tewari
  • Patent number: 9645848
    Abstract: Systems and methods are provided for scheduling homogeneous workloads including batch jobs, and heterogeneous workloads including batch and dedicated jobs, with run-time elasticity wherein resource requirements for a given job can change during run-time execution of the job.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hani T. Jamjoom, Dinesh Kumar, Zon-Yin Shae
  • Patent number: 9645849
    Abstract: Systems and methods are provided for scheduling homogeneous workloads including batch jobs, and heterogeneous workloads including batch and dedicated jobs, with run-time elasticity wherein resource requirements for a given job can change during run-time execution of the job.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hani T. Jamjoom, Dinesh Kumar, Zon-Yin Shae
  • Patent number: 9639678
    Abstract: Embodiments are directed to providing an identity risk score as part of an authentication assertion, applying operating heuristics to determine an operating application's validity and to providing identity risk scores to requesting third parties. In one scenario, an authentication server receives from a cloud service portal various user credentials from a user. The user credentials identify a user to the authentication server. The authentication server verifies the user's identity using the received credentials and generates an identity risk score based on one or more identity factors. The identity factors indicate a likelihood that the user is a valid user. The authentication server encapsulates the generated identity risk score in an authentication assertion and sends the authentication assertion that includes the generated identity risk score to the cloud service portal.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 2, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: George M. Moore
  • Patent number: 9639529
    Abstract: A complete document management system is disclosed. Accordingly, systems and methods for managing data associated with a data storage component coupled to multiple computers over a network are disclosed. Systems and methods for managing data associated with a data storage component coupled to multiple computers over a network are further disclosed. Additionally, systems and methods for accessing documents available through a network, wherein the documents are stored on one or more data storage devices coupled to the network, are disclosed.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 2, 2017
    Assignee: Commvault Systems, Inc.
    Inventors: Anand Prahlad, Srinivas Kavuri, Rajiv Kottomtharayil, Arun Prasad Amarendran, Brian Brockway, Marcus S. Muller, Andreas May
  • Patent number: 9639401
    Abstract: A multicore adaptive scheduler of tasks in an ARINC 653-compliant avionics system allocates flight critical tasks execution time equivalent to their worst case execution time and allocates quality-driven tasks minimum execution time equivalent to their minimum completion time. The scheduler may also offset the start time of a task or define an upper bound for completion time of a quality-driven task. The scheduler generates and executes partition schedules of tasks, reallocating execution time unused by completed tasks and reallocating execution time from interrupt handlers to tasks preempted by interrupts. The scheduler may also analyze the viability of a generated schedule. The scheduler uses rate limiting and flow control techniques to ensure a predictable amount of execution time to be reallocated for interrupt handling.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: May 2, 2017
    Assignee: Rockwell Collins, Inc.
    Inventors: Joshua R. Bertram, Branden H. Sletteland
  • Patent number: 9632852
    Abstract: A messaging system implements messaging among application servers and databases, utilizing other servers that implement messaging brokers. A large flood of incoming messages can bring down messaging brokers by overflowing the message queues, negatively impacting performance of the overall system. This disclosure in some embodiments detects and identifies “flooders” in a timely manner and isolates their message traffic to dedicated queues to avoid impacting other system users. Subsequently, a preferred system de-allocates the queues and returns the messaging system to normal operation when flooding conditions subside, and “sweeps” up any remaining orphan messages.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: April 25, 2017
    Assignee: SALESFORCE.COM, INC.
    Inventors: Hui Lam Kwong, Xiaodan Wang, Vipul Modani, John B. Buisson
  • Patent number: 9632822
    Abstract: A multi-core device and a multi-thread scheduling method thereof are disclosed. The multi-thread scheduling method includes the following steps: recording thread performance-associated parameters for a thread; and performing a thread load balancing between multiple central processing units of a multi-core processor of the multi-core device. The thread load balancing is performed according to a thread critical performance condition of the thread and the thread critical performance condition is determined based on the thread performance-associated parameters.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: April 25, 2017
    Assignee: HTC CORPORATION
    Inventors: Wen-Yen Chang, Chih-Tsung Wu, Ching-Tsung Lai
  • Patent number: 9632566
    Abstract: The present embodiments provide a system that dynamically controls power consumption in a computing device. During operation, the system measures the performance of the computing device while executing a work-loop. Next, the system determines a derived completion time for the work-loop based on the measured performance. (For example, the derived completion time can be an expected completion time, a maximum completion time, or more generally a completion time distribution.) The system then determines a deadline-proximity for the work-loop based on a comparison between the derived completion time and a deadline for the work-loop. (For example, the deadline-proximity can be an expected deadline-proximity, a minimum deadline-proximity, or more generally a deadline-proximity distribution.) Finally, the system controls the power consumption of the computing device based on the determined deadline-proximity for the work-loop.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 25, 2017
    Assignee: Apple Inc.
    Inventor: Daniel J. Culbert
  • Patent number: 9632826
    Abstract: A task is marked as dependent upon a preceding task. The task that is attempted to be taken for execution from a head of a pending task queue that is marked is deferred. The deferred task is removed from the pending task queue and placed in a deferred task queue. The deferred task is reinserted back into the pending task queue for execution upon determining that the preceding tasks are completed.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ron Edelstein, Yariv Bachar, Oded Sonin
  • Patent number: 9626219
    Abstract: An information processing apparatus capable of executing processing in a background, comprises a control unit configured to, when processing is executed in accordance with a request from an application, control execution of other processing in the background, wherein the control unit suppresses, in accordance with the request from the application, so that the other processing is not executed in the background, and releases the suppression when, in a case where a request for release of suppression is not instructed from the application, a predetermined interval elapses from when the suppression started.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 18, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yasutomo Shimizu
  • Patent number: 9619282
    Abstract: One aspect provides a method including: identifying a task to be scheduled for execution on an information handling device having two or more cores of different size; determining an appropriate scheduling of the task for execution on the two or more of cores of different size, wherein the appropriate scheduling of the task is determined via a core signature for the task; directing the task to an appropriate core for execution based on the appropriate scheduling determined; and executing the task on the appropriate core. Other aspects are described and claimed.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: April 11, 2017
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Mark C. Davis, Daryl C. Cromer, Howard J. Locker, Scott E. Kelso